IDT ICS86004-02

PRELIMINARY
ICS86004-02
62.5MHZ TO 250MHZ, 1-TO-4 LVCMOS/
LVTTL ZERO DELAY CLOCK BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS86004-02 is a high performance 1-to-4
ICS
LVCMOS/LVTTL Clock Buffer and a member of
HiPerClockS™ the HiPerClockS™family of High Performance Clock
Solutions from IDT. The ICS86004-02 has a fully
integrated PLL and can be configured as zero
delay buffer and has an input and output frequency range of
62.5MHz to 250MHz. The external feedback allows the device
to achieve “zero delay” between the input clock and the output
clocks. The PLL_SEL pin can be used to bypass the PLL for
system test and debug purposes. In bypass mode, the reference clock is routed around the PLL and into the internal output divider.
• Four LVCMOS/LVTTL outputs, 7Ω typical output impedance
ICS86004-02 has a special feature that when CLK is LOST, it
will disable the output to logic LOW.
• Output skew: 45ps (typical)
• Single LVCMOS/LVTTL clock input
• CLK accepts the following input levels: LVCMOS or LVTTL
• Output frequency range: 62.5MHz to 250MHz
• Input frequency range: 62.5MHz to 250MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Fully integrated PLL
• Cycle-to-cycle jitter, (F_SEL = 1): 35ps (typical)
• Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
• 5V tolerant input
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
compliant packages
CONTROL INPUT FUNCTION TABLE
Input
F_SEL
Input/Output
Frequency Range (MHz)
Minimum
Maximum
0
125
250
1
62.5
125
BLOCK DIAGRAM
PLL_SEL
PIN ASSIGNMENT
Pullup
Q0
÷8
0
Q1
CLK Pulldown
1
Q2
PLL
0
FB_IN Pulldown
1:1
Q3
1
Q1
GND
Q0
F_SEL
VDD
CLK
GND
VDDA
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDO
Q2
GND
Q3
VDDO
MR
FB_IN
PLL_SEL
ICS86004-02
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
MR Pulldown
F_SEL Pulldown
LOSS Reference Detect
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization
and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT ™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
1
ICS86004AG-02 REV A NOVEMBER 3, 2006
ICS86004-02
62.5MHz TO 250MHz, 1-TO-4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
1, 3,
13, 15
2, 7, 14
Name
Q1, Q0,
Q3, Q2
GND
Type
Output
Clock outputs. 7Ω typical output impedance. LVCMOS/LVTTL interface levels.
Power
4
F_SEL
Input
5
VDD
Power
Power supply ground.
Frequency range select input. When LOW, I/O frequency range is from
125MHz to 250Mz. When HIGH, I/O frequency range is from
62.5MHz to 125MHz. LVCMOS/LVTTL interface levels.
Core supply pin.
6
CLK
Input
Pulldown LVCMOS/LVTTL clock input.
8
VDDA
Power
9
PLL_SEL
Input
10
FB_IN
Input
11
MR
Input
Analog supply pin.
Selects between the PLL and reference clock as input to the dividers.
Pullup
When LOW, selects the reference clock (PLL Bypass). When HIGH,
selects PLL (PLL Enabled). LVCMOS/LVTTL interface levels.
Feedback input to phase detector for regenerating clocks with "zero delay".
Pulldown
Connect to one of the outputs. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
Pulldown causing the outputs to go low. When logic LOW, the internal dividers and the
outputs are enabled. LVCMOS/LVTTL interface levels.
12, 16
VDDO
Power
Pulldown
Description
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
CPD
Test Conditions
Power Dissipation Capacitance
(per output)
ROUT
Minimum
Typical
Maximum
Units
51
kΩ
VDD, VDDA, VDDO = 3.465V
TBD
pF
VDD, VDDA = 3.465V,
VDDO = 2.625V
TBD
pF
Output Impedance
3.3V ± 5%
5
7
12
Ω
TABLE 3. CONTROL INPUT FUNCTION TABLE
Input
F_SEL
Input/Output
Frequency Range (MHz)
Minimum
Maximum
0
125
250
1
62.5
125
IDT ™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
2
ICS86004AG-02 REV A NOVEMBER 3, 2006
ICS86004-02
62.5MHz TO 250MHz, 1-TO-4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5 V
Outputs, VO
-0.5V to VDDO + 0.5V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause per manent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, θJA 89°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = -0°C TO 70°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
VDD – 0.13
3.3
VDD
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
85
IDDA
Analog Supply Current
13
mA
IDDO
Output Supply Current
4
mA
mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
VDDA
Analog Supply Voltage
3.135
3.3
3.465
V
VDD – 0.13
3.3
VDD
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
85
mA
IDDA
Analog Supply Current
13
mA
IDDO
Output Supply Current
4
mA
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, TA = 0°C TO 70°C
Symbol
Parameter
VIH
Input High Voltage
VDD = 3.3V
VIL
Input Low Voltage
VDD = 3.3V
IIH
IIL
VOH
Input High Current
Input Low Current
Test Conditions
CLK, MR,
FB_IN, F_SEL
PLL_SEL
Minimum Typical
Maximum
Units
2
VDD + 0.3
V
-0.3
0.8
V
VDD = VIN = 3.465V
150
µA
VDD = VIN = 3.465V
5
µA
CLK, MR,
FB_IN, F_SEL
VDD = 3.465V, VIN = 0V
-5
µA
PLL_SEL
VDD = 3.465V, VIN = 0V
-150
µA
VDDO = 3.465V
2. 6
V
VDDO = 2.625V
1.8
Output High Voltage; NOTE 1
V
Output Low Voltage; NOTE 1
VDDO = 3.465V or 2.625V
VOL
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information Section,
Output Load Test Circuit diagrams.
IDT ™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
3
0.5
V
ICS86004AG-02 REV A NOVEMBER 3, 2006
ICS86004-02
62.5MHz TO 250MHz, 1-TO-4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
PRELIMINARY
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
t(Ø)
tsk(o)
Static Phase Offset; NOTE 2, 4
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 4
tL
PLL Lock Time
tR / tF
Output Rise/Fall Time
Output Skew; NOTE 3, 4
Test Conditions
Minimum
Maximum
Units
F_SEL = 0
125
Typical
250
MHz
F_SEL = 1
PLL_SEL = 0V,
Bypass Mode
PLL_SEL = 3.3V
62.5
125
MHz
5.8
ns
330
ps
PLL_SEL = 0V
60
ps
F_SEL = 0
F_SEL = 1
40
35
ps
ps
1
20% to 80%
550
mS
ps
F_SEL = 0
50
odc
Output Duty Cycle
F_SEL = 1
50
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
%
%
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
t(Ø)
Static Phase Offset; NOTE 2, 4
tsk(o)
Output Skew; NOTE 3, 4
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 4
tL
PLL Lock Time
tR / tF
Output Rise/Fall Time
Test Conditions
Minimum
Maximum
Units
F_SEL = 0
12 5
Typical
250
MHz
F_SEL = 1
PLL_SEL = 0V,
Bypass Mode
PLL_SEL = 3.3V
62.5
125
MHz
6.2
ns
285
ps
PLL_SEL = 0V
45
ps
F_SEL = 0
F_SEL = 1
45
35
ps
ps
20% to 80%
500
1
F_SEL = 0
50
F_SEL = 1
50
NOTE 1: Measured from the differential input crossing point to the output at VDDO/2.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
odc
Output Duty Cycle
IDT ™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
4
mS
ps
%
%
ICS86004AG-02 REV A NOVEMBER 3, 2006
ICS86004-02
62.5MHz TO 250MHz, 1-TO-4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
2.05V±5%
1.65V±5%
1.25V±5%
1.65V±5%
2.05V±5%
SCOPE
VDD,
VDDO
SCOPE
VDD
VDDA
Qx
VDDO
LVCMOS
VDDA
Qx
LVCMOS
GND
GND
-1.65V±5%
-1.25V±5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
VDD
V
Q0:Q3
DDO
2
DDO
2
➤
VDD
V
V
DDO
2
tcycle n
➤
CLK
➤
2
tcycle n+1
➤
2
FB_IN
t jit(cc) = tcycle n –tcycle n+1
➤
➤ t (Ø)
1000 Cycles
t (Ø) mean = Static Phase Offset
(where t (Ø) is any random sample, and t (Ø) mean is the average
of the sampled cycles measured on controlled edges)
STATIC PHASE OFFSET
80%
CYCLE-TO-CYCLE JITTER
80%
CLK
Clock
Outputs
20%
20%
tR
VDD
2
2
VDDO
tF
VDDO
2
tpLH
Q0:Q3
OUTPUT RISE/FALL TIME
2
tpHL
PROPAGATION DELAY
V
DDO
Qx
VDD
Q0:Q3
2
VDDO
VDDO
VDDO
2
2
2
t PW
t PERIOD
V
DDO
Qy
2
t sk(o)
odc =
OUTPUT SKEW
IDT ™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
t PW
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
5
ICS86004AG-02 REV A NOVEMBER 3, 2006
ICS86004-02
62.5MHz TO 250MHz, 1-TO-4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS86004-02 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance, power
supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VDDA. The 10Ω resistor
cn also be replaced by a ferrite bead.
3.3V
VDD
.01µF
VDDA
.01µF
10µF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT ™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
10Ω
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. There should be
no trace attached.
6
ICS86004AG-02 REV A NOVEMBER 3, 2006
ICS86004-02
62.5MHz TO 250MHz, 1-TO-4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
PRELIMINARY
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
FOR
16 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
137.1°C/W
89.0°C/W
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS86004-02 is: 2782
IDT ™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
7
ICS86004AG-02 REV A NOVEMBER 3, 2006
ICS86004-02
62.5MHz TO 250MHz, 1-TO-4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
PRELIMINARY
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
N
Maximum
16
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
4.90
E
E1
5.10
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT ™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
8
ICS86004AG-02 REV A NOVEMBER 3, 2006
ICS86004-02
62.5MHz TO 250MHz, 1-TO-4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
PRELIMINARY
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
ICS86004AG-02
86004A02
16 Lead TSSOP
Tube
0°C to 70°C
ICS86004AG-02T
86004A02
16 Lead TSSOP
2500 Tape & Reel
0°C to 70°C
ICS86004AG-02LF
TB D
16 Lead "Lead-Free" TSSOP
Tube
0°C to 70°C
ICS86004AG-02LFT
TBD
16 Lead "Lead-Free" TSSOP
2500 Tape & Reel
0°C to 70°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
IDT ™ / ICS™ LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
9
ICS86004AG-02 REV A NOVEMBER 3, 2006
ICS86004-02
62.5MHz TO 250MHz, 1-TO-4 LVCMOS/LVTTL ZERO DELAY CLOCK BUFFER
PRELIMINARY
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Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
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England
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© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
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