PRELIMINARY Integrated Circuit Systems, Inc. ICS8430-111 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS8430-111 is a general purpose, dual outICS put high frequency synthesizer and a member of HiPerClockS™ the HiPerClockS™ family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels. The single ended TEST_CLK input accepts LVCMOS or LVTTL input levels and translates them to 3.3V LVPECL levels. The VCO operates at a frequency range of 200MHz to 700MHz. With the output configured to divide the VCO frequency by 2, output frequency steps as small as 2MHz can be achieved using a 16MHz differential or single ended reference clock. Output frequencies up to 700MHz can be programmed using the serial or parallel interfaces to the configuration logic. The low jitter and frequency range of the ICS8430-111 makes it an ideal clock generator for most clock tree applications. • Dual differential 3.3V LVPECL output • Selectable 14MHz to 27MHz differential CLK, nCLK or TEST_CLK input • CLK, nCLK accepts any differential input signal: LVPECL, LVHSTL, LVDS, SSTL, HCSL • TEST_CLK accepts the following input types: LVCMOS, LVTTL • Output frequency range up to 700MHz • VCO range: 200MHz to 700MHz • Parallel or serial interface for programming counter and output dividers • Cycle-to-cycle jitter: 25ps (maximum) • 3.3V supply voltage • 0°C to 70°C ambient operating temperature • Industrial termperature information available upon request BLOCK DIAGRAM PIN ASSIGNMENT nCLK nP_LOAD M0 M1 32 31 30 29 28 27 26 25 1 ÷ 16 PLL PHASE DETECTOR MR VCO ÷M 0 1 1 24 CLK M6 2 23 TEST_CLK M7 3 22 CLK_SEL M8 4 21 VCCA N0 5 20 S_LOAD N1 6 19 S_DATA N2 7 18 S_CLOCK VEE 8 17 MR ICS8430-111 9 10 11 12 13 14 15 16 VEE nFOUT0 FOUT0 VCCO nFOUT1 FOUT1 VCC CONFIGURATION INTERFACE LOGIC M5 TEST FOUT0 nFOUT0 FOUT1 nFOUT1 ÷N ÷2 S_LOAD S_DATA S_CLOCK nP_LOAD M2 0 M3 CLK nCLK M4 CLK_SEL TEST_CLK VCO_SEL VCO_SEL TEST 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View M0:M8 N0:N2 The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8430DY-111 www.icst.com/products/hiperclocks.html 1 REV. F JUNE 1, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430-111 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION the parallel input mode. The relationship between the VCO frequency, the input frequency and the M divider is defined as follows: fVCO = fIN x M The ICS8430-111 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A differential clock input is used as the input to the on-chip oscillator. The output of the oscillator is divided by 16 prior to the phase detector. A16MHz clock input provides a 1MHz reference frequency. The VCO of the PLL operates over a range of 200 to 700MHz. The output of the M divider is also applied to the phase detector. The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 16MHz reference are defined as 100 ≤ M ≤ 350. The frequency out is defined as follows: fOUT = fVCO = fIN x M N N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS8430-111 support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 through N2 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in T1 T0 TEST Output 0 0 LOW 0 1 S_Data, Shift Register Input 1 0 Output of M divider 1 1 CMOS Fout SERIAL LOADING S_CLOCK S_DATA t S_LOAD S t H nP_LOAD t S PARALLEL LOADING M, N M0:M8, N0:N1 nP_LOAD t S t H S_LOAD Time FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: 8430DY-111 The NULL timing slot must be observed. www.icst.com/products/hiperclocks.html 2 REV. F JUNE 1, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430-111 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number 1, 2, 3, 28, 29, 30 31, 32 4 Name M5, M6, M7, M0, M1, M2, M3, M4 M8 Input 5, 6 N0, N1 Input 7 8, 16 N2 VEE Input Power 9 TEST Output 10 VCC FOUT1, nFOUT1 VCCO FOUT0, nFOUT0 Power 11, 12 13 14, 15 Type Input Description Pulldown M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS/LVTTL interface levels. Pullup Pulldown Determines output divider value as defined in Table 3C Function Table. LVCMOS/LVTTL interface levels. Pullup Negative supply pins. Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS/LVTTL interface levels. Core supply pin. Output Differential output for the synthesizer. 3.3V LVPECL interface levels. Power Output supply pin. Output Differential output for the synthesizer. 3.3V LVPECL interface levels. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low and the inver ted 17 MR Input Pulldown outputs nFOUTx to go high. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not affect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register 18 S_CLOCK Input Pulldown on the rising edge of S_CLOCK. LVCMOS/LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of 19 S_DATA Input Pulldown S_CLOCK. LVCMOS/LVTTL interface levels. Controls transition of data from shift register into the dividers. 20 S_LOAD Input Pulldown LVCMOS/LVTTL interface levels. Power Analog supply pin. 21 VCCA Selects between differential clock or test inputs as the PLL reference source. Selects CLK, nCLK inputs when HIGH. Selects TEST_CLK 22 Input Pullup CLK_SEL when LOW. LVCMOS/LVTTL interface levels. Pulldown Test clock input. LVCMOS/LVTTL interface levels. 23 TEST_CLK Input 24 CLK Input Pulldown Non-inver ting differential clock input. nCLK Input Pullup Inver ting differential clock input. 25 Parallel load input. Determines when data present at M8:M0 is 26 nP_LOAD Input Pulldown loaded into the M divider, and when data present at N2:N0 sets the N output divider value. LVCMOS/LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. 27 VCO_SEL Input Pullup LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLUP RPULLDOWN 8430DY-111 Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 51 51 www.icst.com/products/hiperclocks.html 3 Maximum 4 Units pF kΩ kΩ REV. F JUNE 1, 2005 PRELIMINARY Integrated Circuit Systems, Inc. TABLE 3A. PARALLEL AND ICS8430-111 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER SERIAL MODE FUNCTION TABLE Inputs Conditions MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X Reset. Forces outputs LOW. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L ↑ Data Data L X X L H X X L ↑ Data L H X X ↑ L Data L H X X ↓ L Data L H X X L X X H ↑ Data L H X X NOTE: L = LOW H = HIGH X = Don't care ↑ = Rising edge transition ↓ = Falling edge transition Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. M divider and N output divider values are latched. Parallel or serial input do not affect shift registers. S_DATA passed directly to M divider as it is clocked. TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1) 100 256 M8 0 128 M7 0 64 M6 1 32 M5 1 16 M4 0 8 M3 0 4 M2 1 2 M1 0 1 M0 0 101 102 103 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 0 1 • • 0 0 1 • • 0 1 0 VCO Frequency (MHz) M Divide 200 202 204 206 • • • • • • • • • • • • • • • • • • 696 34 8 1 0 1 0 1 1 1 698 349 1 0 1 0 1 1 1 700 35 0 1 0 1 0 1 1 1 NOTE 1: These M divide values and the resulting frequencies correspond to an input frequency of 16MHz. TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE 8430DY-111 N2 0 Input N1 0 N0 0 0 0 1 4 50 175 0 1 0 8 25 87.5 N Divider Value 2 Output Frequency (MHz) Minimum Maximum 100 350 0 1 1 16 12.5 43.75 1 0 0 1 200 700 350 1 0 1 2 100 1 1 0 4 50 175 1 1 1 8 25 87.5 www.icst.com/products/hiperclocks.html 4 REV. F JUNE 1, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430-111 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, VO -0.5V to VCCO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Core Supply 3.135 3.3 3.465 V VCCA Analog Voltage 3.135 3.3 3.465 V VCCO Ouput Voltage 3.135 3.3 3.465 V IEE Power Supply Current 120 mA ICCA Analog Supply Current 10 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage M0-M7, N0, N1, MR, S_CLOCK, S_DATA, S_LOAD, Input High Current TEST_CLK, nP_LOAD M8, N2, CLK_SEL, VCO_SEL M0-M7, N0, N1, MR, S_CLOCK, S_DATA, S_LOAD, Input TEST_CLK, nP_LOAD Low Current M8, N2, CLK_SEL, VCO_SEL IIH IIL Maximum Units 2 VCC + 0.3 V -0.3 0.8 V VCC = VIN = 3.465V 150 µA VCC = VIN = 3.465V 5 µA VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V Output TEST; NOTE 1 High Voltage Output VOL TEST; NOTE 1 Low Voltage NOTE 1: Outputs terminated with 50Ω to VCCO/2. VOH 8430DY-111 Minimum Typical -5 µA -150 µA 2.6 V 0.5 www.icst.com/products/hiperclocks.html 5 V REV. F JUNE 1, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430-111 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current Minimum Typical Maximum Units nCLK VIN = VCC = 3.465V 5 µA CLK VIN = VCC = 3.465V 150 µA nCLK VIN = 0V, VCC = 3.465V -150 CLK VIN = 0V, VCC = 3.465V -5 µA µA VPP Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VEE + 0.5 VCMR NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 1.3 V VCC - 0.85 V Maximum Units TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical VOH Output High Voltage; NOTE 1 VCCO - 1.4 VCCO - 0.9 V VOL Output Low Voltage; NOTE 1 VCCO - 2.0 VCCO - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. See 3.3V Output Load Test Circuit figure in the Parameter Measurement Information section. TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fIN Input Frequency Maximum Units TEST_CLK; NOTE 1 Test Conditions Minimum 14 Typical 27 MHz CLK, nCLK; NOTE 1 14 27 MHz S_CLOCK 50 MHz NOTE1: For the differential input and reference frequency range, the M value must be set for the VCO to operate within the 200MHz to 700MHz range. Using the minimum input frequency of 14MHz, valid values of M are 115 ≤ M ≤ 400. Using the maximum frequency of 27MHz, valid values of M are 60 ≤ M ≤ 208. 8430DY-111 www.icst.com/products/hiperclocks.html 6 REV. F JUNE 1, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430-111 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter FMAX Output Frequency Test Conditions Minimum Typical fOUT > 87.5MHz Maximum Units 700 MHz 25 ps tjit(cc) Cycle-to-Cycle Jitter ; NOTE 1 40 ps tjit(per) Period Jitter, RMS 9.5 ps tsk(o) Output Skew; NOTE 1, 2 15 ps tR / tF Output Rise/Fall Time 700 ps fOUT < 87.5MHz 20% to 80% M, N to nP_LOAD tS tH Setup Time Hold Time 5 S_DATA to S_CLOCK 5 ns 5 ns M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns 5 Output Duty Cycle 48 52 % N=1 45 55 % 1 ms www.icst.com/products/hiperclocks.html 7 ns N≠1 PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1:This parameter is defined in accordance with JEDEC Standard 65. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. 8430DY-111 ns S_CLOCK to S_LOAD S_CLOCK to S_LOAD odc 200 REV. F JUNE 1, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430-111 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION VCC, VCCA , VCCO = 2V VCC Qx SCOPE nCLK V LVPECL V Cross Points PP CMR CLK nQx VEE VEE = -1.3V ± 0.165V 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nFOUTx 80% 80% FOUTx VSW I N G Clock Outputs nFOUTy 20% 20% tF tR FOUTy tsk(o) OUTPUT RISE/FALL TIME OUTPUT SKEW VOH nFOUTx VREF FOUTx ➤ tcycle ➤ n tcycle n+1 VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements ➤ ➤ t jit(cc) = tcycle n –tcycle n+1 Reference Point 1000 Cycles (Trigger Edge) Histogram Mean Period (First edge after trigger) PERIOD JITTER CYCLE-TO-CYCLE JITTER nFOUTx FOUTx t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 8430DY-111 www.icst.com/products/hiperclocks.html 8 REV. F JUNE 1, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430-111 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8430-111 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. TERMINATION FOR 3.3V VCC .01μF 10Ω V CCA .01μF 10 μF FIGURE 2. POWER SUPPLY FILTERING LVPECL OUTPUTS drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. There are a few simple termination schemes. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω 1 RTT = Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V VCC - 2V RTT 84Ω FIGURE 3A. LVPECL OUTPUT TERMINATION 8430DY-111 125Ω 84Ω FIGURE 3B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 9 REV. F JUNE 1, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430-111 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VCC = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. Figure 4 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VCC/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio VCC R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 4. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8430DY-111 www.icst.com/products/hiperclocks.html 10 REV. F JUNE 1, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430-111 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 5A to 5E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 5A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 5A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 5B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 5C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 5D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 5E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE 8430DY-111 BY www.icst.com/products/hiperclocks.html 11 REV. F JUNE 1, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430-111 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8430-111. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8430-111 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 120mA = 415.8mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.465V, with all outputs switching) = 415.8mW + 60mW = 475.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.476W * 42.1°C/W = 90°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8430DY-111 www.icst.com/products/hiperclocks.html 12 REV. F JUNE 1, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430-111 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX =V OL_MAX CCO_MAX -V OL_MAX CCO_MAX – 0.9V ) = 0.9V For logic low, VOUT = V (V =V CCO_MAX – 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX ))/R ] * (V -V OH_MAX CCO_MAX L -V )= OH_MAX [(2V - 0.9V)/50Ω) * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω) * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 8430DY-111 www.icst.com/products/hiperclocks.html 13 REV. F JUNE 1, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430-111 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8430-111 is: 3960 8430DY-111 www.icst.com/products/hiperclocks.html 14 REV. F JUNE 1, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX FOR ICS8430-111 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 32 LEAD LQFP TABLE 9. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N 1.60 A A1 0.05 A2 1.35 1.40 0.15 1.45 b 0.30 0.37 0.45 c 0.09 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 E 9.00 BASIC E1 7.00 BASIC E2 5.60 0.80 BASIC e L 0.45 q 0° 0.60 0.75 7° 0.10 ccc Reference Document: JEDEC Publication 95, MS-026 8430DY-111 www.icst.com/products/hiperclocks.html 15 REV. F JUNE 1, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8430-111 700MHZ, LOW JITTER DIFFERENTIAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8430DY-111 ICS8430DY-111 32 Lead LQFP tray 0°C to 70°C ICS8430DY-111T ICS8430DY-111 32 Lead LQFP 1000 tape & reel 0°C to 70°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8430DY-111 www.icst.com/products/hiperclocks.html 16 REV. F JUNE 1, 2005