Integrated Circuit Systems, Inc. ICS9147-03 Frequency Generator & Integrated Buffers for 686 Series CPUs General Description Features The ICS9147-03 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro, AMD or Cyrix processors. Four bidirectional I/O pins (FS0, FS1, FS2, BSEL) are latched at power-on to the functionality table. The Six BUS clocks can be selected as either synchronous at 1/2 CPU speed or asynchronous at 32MHz selected by BSEL latched input.The inputs provide for tristate and test mode conditions to aid in system level testing.These multiplying factors can be customized for specific applications. Glitch-free stop clock controls provided for SDRAM(5:8) and SDRAM (9:12) banks (STP2#, STP3#). • High drive BUS and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30 pF loads. CPU outputs typically provide better than 1V/ns slew rate into 20pF loads while maintaining 50±5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. Seperate buffer supply pin VDDL allows for nominal 3.3V voltage or reduced voltage swing (from 2.9 to 2.5V) for CPUL (1:2) and IOAPIC outputs. • Block Diagram • • • • • • Total of 15 CPU speed clocks: - Two copies of CPU clock with VDDL (2.5 to 3.3V) - Twelve (12) SDRAM (3.3v) plus one CPUH/AGP (3.3V) clocks Six copies of BUS clocks (synchronous with CPU clock/2 or asynchronous 32 MHz) 250ps output skew window for CPU andSDRAM clocks and 500ps window BUS clocks. CPU clocks to BUS clocks skew 1-4ns (CPU early) Two copies of Ref. clock @14.31818 MHz (One driven by VDDL as IOAPIC) One 48 MHz (3.3 V TTL) for USB support and single 24 MHz. Separate VDDL for CPUL (1:2) clock buffers and IOAPIC to allow 2.5V output (or Std. Vdd) 3.0V – 3.7V supply range w/2.5V compatible outputs 48-pin SSOP package Pin Configuration 48-Pin SSOP Pentium is a trademark of Intel Corporation 9147-03 Rev A 04/25/01 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9147-03 Functionality with (14.31818 MHz input) Addre s s Se le ct CPUL (1:2) CPUH SDRAM (1:12) (MHz) BUS (1:6) (M Hz) BSEL=1 BSEL=0 24M 48M (M Hz) (M Hz) (MHz) (MHz) FS2 FS1 FS0 0 0 0 60 30 32 24 48 0 0 1 66.8 33.4 32 24 48 0 1 0 50 25 32 24 48 0 1 1 55 27.5 32 24 48 1 0 0 75 37.5 32 24 48 1 0 1 68.5 34.3 32 24 48 1 1 0 Test/2** Test/4** Test/3** 1 1 1 Tristate Tristate Tristate SDRAM Clock Enable DIMM DIMM DIMM STP2# STP3# BANK1 BANK2 BANK3 SDRAM SDRAM SDRAM (1:4) (5:8) (9:12) Stopped Stopped 0 0 ON Low Low Stopped 0 1 ON ON Low Stopped 1 0 ON ON Low 1 1 ON ON ON Test/4** Test/2** Tristate Tristate **Test: is the frequency applied to the X1 input. Can be crystal or tester generated clock overriding crystal at X1 pin. Pin Descriptions PI N N U M B E R 2 3, 9, 16, 22, 27, 33, 39, 45 4 5 41 8, 10, 11, 12, 14, 15 23, 24 PI N N A M E Reference clock output* Logic input frequency select Bit1*. Input latched at P oweron. GN D P WR Ground. X1 X2 VDDL BUS (1:5) BUS6 FS0 IN O UT P WR O UT O UT IN S TP # (2:3) IN C rystal input. N ominally 14.318 MHz. Has internal load cap C rystal output. Has internal load cap and feedack resistor to X1 2.5 or 3.3V buffer power for C P UL and IO AP IC output buffers. BUS clock outputs. see select table for frequency BUS clock output. S ee select table for frequency.* Logic input frequency select Bit0.*. Input latched at P oweron. Bank enable solutions for S DRAM clocks see table above, C locks are enabled in groups of 4. (S TP 2# stops DIMM bank2, S TP 3# stops DIMM bank 3 when low). 24MHz fixed clock.* Logic input* for selecting synchronous or asynchronous BUS frequencysee table above. Input latched at P oweron.* O UT BS EL IN VDD3 P WR 3.3 volt core logic and buffer power S DRAM (1:12) O UT S DRAM clocks at C P U speed. S ee select table for frequency. C P U clock operates at S DRAM VDD level (3.3V nom), for AGP etc. C P U clock output clocks .S ee select table for frequency. O perates at down to 2.5V controlled by VDDL pin. P ins not internally connected. 48 MHz fixed clock output*. Logic input frequency select Bit 2*. Input latched at P oweron. Reference clock (14.318MHz) powered by VDDL, operating 2.5 to 3.3V. 1, 6, 13, 19, 30, 36, 48 17, 18, 20, 21, 28, 29, 31, 32, 34, 35, 37, 38 40 C P UH/AGP O UT 42, 43 CPUL (1:2) O UT N /C 48M FS2 — O UT IN IO AP IC O UT 7, 25, 26 46 44 D E S C R I PT I O N O UT IN 24M 47 TYPE R EF FS1 * Bidirectional input/output pins, input logic level determined at internal power-on-reset are latched. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low. 2 ICS9147-03 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 3.3V VDD = 3.0 – 3.7 V, TA = 0 – 70° C unless otherwise stated DC Characte ris tics MIN TYP MAX UNITS Input Low Voltage PARAMETER VIL STP# and latched inputs - - 0.2VDD V Input High Voltage VIH STP# and latched inputs 0.7VDD - - V Input Low Current IIL VIN=0V (STP# inputs) - 28.0 - 10 . 5 - A Input High Current IIH VIN=VDD (STP# inputs) - 5.0 - 5.0 A IOL1 VOL=0.8V; for IOAPIC, CPUH, SDRAM, BUS & REF (and CPUL at VDDL = 3.0 to 3.7V) 19 30.0 - mA IOH1 VOH=2.0V; for IOAPIC, CPUH, SDRAM, BUS & REF (and CPUL at VDDL = 3.0 to 3.7V) - - 26.0 - 16 mA Output Low Current IOL2 VOL=0.8V; for fixed 24, 48 CLKs 16 25.0 - mA Output High Current IOH2 VOH=2.0V; for fixed 24, 48 CLKs - - 22.0 - 14 mA Output Low Current IOL3 VOL=0.8V; for CPUL at VDDL = 2.5V 19 30.0 - mA Output High Current IOH3 VOH = 1.7V; for CPUL at VDDL = 2.5V - - 12.5 - 9.5 mA Output Low Voltage VOL1 IOL = 10mA; - 10mA for IOAPIC, CPUH, SDRAM, BUS & REF (and CPUL at VDDL = 3.0 to 3.7V) - 0.22 0.4 V Output High Voltage VOH1 IOH = - 10mA; for CPUH, SDRAM, BUS & REF (and CPUL at VDDL = 3.0 to 3.7V) 2.4 2.8 - V Output Low Voltage VOL2 IOL = 8mA; for fixed CLKs - 0.25 0.4 V Output High Voltage VOH2 IOH = - 8mA; for fixed CLKs 2.4 2.6 - V Output Low Voltage VOL3 IOL = 8mA; for CPUL at VDDL = 2.5V - 0.25 0.4 V Output High Voltage VOH3 IOH = - 8mA; for CPUL at VDDL = 2.5V 1.95 2.1 - V - 90 18 0 mA Output Low Current Output High Current Supply Current SYMBOL IDD TEST CONDITIONS @66.6 MHz; all outputs unloaded Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 3 ICS9147-03 Electrical Characteristics at 3.3V VDD = 3.0 – 3.7 V, TA = 0 – 70° C unless otherwise stated AC Characte ris tics PARAMETER SYMBO L TEST CO NDITIO NS Rise Time1 Tr1 Fall Time1 Tf1 Rise Time1 Tr2 Fall Time1 Tf2 Rise Time1 Tr3 Fall Time1 Tf3 Rise Time1 Tr4 Fall Time1 Tf4 20pF load, 0.8 to 2.0V CPU, SDRAM, BUS & REF 20pF load, 2.0 to 0.8V CPU, SDRAM, BUS & REF 20pF load, 20% to 80% CPU, SDRAM, BUS & REF 20pF load, 80% to 20% CPU, SDRAM, BUS & REF 20pF load, 0.8 to 2.0V fixed 24 & 48 clocks 20pF load, 2.0 to 0.8V fixed 24 & 48 clocks 20pF load, 0.4 to 2.0V , CPUL with VDDL = 2.5V 20pF load, 2.0 to 0.4V, CPUL with VDDL = 2.5V Duty Cycle1 Dt 20pF load @ VO UT=1.4V Jitter, O ne Sigma1 Tjis1 Jitter, Absolute1 Tjab1 Jitter, O ne Sigma1 Tjis2 Jitter, Absolute1 Tjab2 Input Frequency1 MIN TYP MAX UNITS - 0.9 1.5 ns - 0.8 1.4 ns - 1.5 2.5 ns - 1.4 2.4 ns - 1.7 2.5 ns - 1.2 2.0 ns - 2.0 3.0 ns - 1.5 2.5 ns 45 50 55 % - 50 15 0 ps - 250 - 250 ps - 1 3 % -5 2 5 % 12.0 14.318 16.0 MHz CPU & BUS Clocks; Load=20pF, SDRAM; Load = 30pF 25 MHz, BSEL=1 CPU & BUS Clocks; Load=20pF, SDRAM; Load = 30pF FO UT=25 MHz, BSEL=1 Fixed CLK ; Load=20pF Fixed CLK ; Load=20pF Fi Logic Input Capacitance1 CIN Logic input pins - 5 - pF Crystal O scillator Capacitance1 CINX X1, X2 pins - 18 - pF - 2.5 4.5 ms - 150 250 ps - 300 500 ps 1 2.6 4 ns 250 400 ps Power- on Time1 ton Clock Skew1 Tsk1 Clock Skew1 Tsk2 Clock Skew1 Tsk3 Clock Skew1 TSR4 From VDD=1.6V to 1st crossing of 66.6 MHz VDD supply ramp < 40ms CPU to CPU; Load=20pF; @1.4V (Same VDD) BUS to BUS; Load=20pF; @1.4V CPU to BUS; Load=20pF; @1.4V (CPU is early) SDCPU (@3.3V) to CPU (@2.5V) (2.5V CPU is late) Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 4 ICS9147-03 Shared Pin Operation Input/Output Pins Test Mode Operation The ICS9147-03 includes a production test verification mode of operation. This requires that the FS2 and FS1 pins be programmed to a logic high and the FS0 pin be programmed to a logic low(see Shared Pin Operation section). In this mode the device will output the following frequencies. Pins 2, 15, 46 and 47 on the ICS9147-03 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 4-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm(10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. BUS BUS Pin REF, IOAPIC 48MHz 24MHz CPU, SDRAM BSEL=1 BSEL=0 Fre que ncy REF REF/2 REF/4 REF2 REF/4 REF/3 Note: REF is the frequency of either the crystal connected between the devices X1and X2, or, in the case of a device being driven by an external reference clock, the frequency of the reference (or test) clock on the device’s X1 pin. Figs. 1 and 2 show the recommended means of implementing this function. In Fig. 1 either one of the resistors is loaded onto the board (selective stuffing) to configure the device’s internal logic. Figs. 2a and b provide a single resistor loading option where either solder spot tabs or a physical jumper header may be used. These figures illustrate the optimal PCB physical layout options. These configuration resistors are of such a large ohmic value that they do not effect the low impedance clock signals. The layouts have been optimized to provide as little impedance transition to the clock signal as possible, as it passes through the programming resistor pad(s). Fig. 1 5 ICS9147-03 Fig. 2a Fig. 2b 6 ICS9147-03 Recommended PCB Layout for ICS9147-03 NOTE: This PCB Layout is based on a 4 layer board with an internal Ground (common) and Vcc plane. Placement of components will depend on routing of signal trace. The 0.1uf Capacitors should be placed as close as possible to the Power pins. Placement on the backside of the board is also possible. The Ferrite Beads can be replaced with 10-15ohm Resistors. For best results, use a Fixed Voltage Regulator between the main (board) Vcc and the different Vdd planes. 7 ICS9147-03 c N SYMBOL L E1 INDEX AREA A A1 b c D E E1 e h L N α E 1 2 a h x 45° D A In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° A1 -Ce SEATING PLANE N .10 (.004) C 48 b VARIATIONS D mm. MIN MAX 15.75 16.00 D (inch) MIN .620 MAX .630 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 300 mil SSOP Package Ordering Information ICS9147F-03 Example: ICS XXXX F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS = Standard Device 8 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.