ICS9158-03 Integrated Circuit Systems, Inc. Frequency Generator and Integrated Buffer General Description Features The ICS9158-03 is a low-cost frequency generator designed specifically for desktop and notebook PC applications. Eight copies of the CPU clock are available. Each high drive (40mA) output is capable for driving a 30pF load and has a typical duty cycle of 50/50. The clock outputs are skew-controlled to within ±250ps. The ICS9158-03 makes a gradual transition between frequencies, so that it meets the Intel cycle-to-cycle timing specification for 486 and Pentium systems. 8 skew-free, high drive CPU/BUS clocks Up to 100 MHz output ±250ps skew between all outputs Outputs can drive up to 30pF load and 40mA 50±10% duty cycle Compatible with 486 and Pentium CPUs On-chip loop filter components 4.5V - 5.5V supply range 24-pin SOIC package Applications Ideal for RISC or CISC systems such as 486, Pentium, PowerPC, etc. requiring multiple CPU and BUS clocks. Block Diagram 9158-03 Rev D 7/28/98 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9158-03 Pin Configuration 24-Pin SOIC Functionality (Assuming 14.318 MHz input.) VDD=5V±10% or 3.3V±10%, TEMP=0-70°C FS2 FS1 FS0 CLK2A (MHz) CLK12(A-C) (MHZ) CLK1(A-D) (MHz) 0 0 0 32 16 16 0 0 1 32 32 16 0 1 0 32 16 16 0 1 1 32 32 16 1 0 0 50 25 25 1 0 1 50 50 25 1 1 0 66.67 33.33 33.33 1 1 1 60 60 30 Peripheral Clocks OE CLK2A CLK12(A-C) CLK12(A-D) 40MHz (Pin 6) 24MHz (Pin 7) REF (Pin 18) 1 Runs Runs Runs 39.92 23.95 14.31818 0 Tristate Tristate Tristate Tristate Tristate Tristate 2 ICS9158-03 Pin Descriptions for ICS9158-03 PIN NUM BER PIN NAM E TYPE DESCRIPTION 1 CLK1A OUT CLK1A clock output 2 X2 OUT Crystal connection 3 X1 IN Crystal connection 4 VDD PW R Digital POW ER SUPPLY (+5V) 5 GND PW R Digital GROUND 6 40 M Hz OUT 40 M Hz clock output 7 24 M Hz OUT 24 M Hz floppy disk/com bination I/O clock output 8 CLK1B OUT CLK1B clock output 9 AGND PW R ANALOG GROUND 10 OE 11 CLK12B OUT 12 GND PW R Digital GROUND 13 CLK1C OUT CLK1C clock output 14 CLK1D OUT CLK1D clock output 15 FS2 16 AVDD PW R 17 CLK12A OUT CLK12A clock output 18 REF OUT 14.31818 M Hz clock output Digital GROUND IN IN OUTPUT ENABLE. Tristates all outputs when low. CLK12B clock output CPU clock frequency select 2 ANALOG power supply (+5V) 19 GND PW R 20 VDD PW R Digital POW ER SUPPLY (+5V) 21 CLK12C OUT 2X CPU clock output 22 CLK2A OUT CPU clock output 23 FS1 IN CPU clock frequency select 1 24 FS0 IN CPU clock frequency select 0 3 ICS9158-03 Absolute Maximum Ratings AVDD, VDD referenced to GND . . . . . . . . . . . . . . . . 7V Operating temperature under bias. . . . . . . . . . . . . . . . 0°C to +70°C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +150°C Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 5V VDD = +5V±10%, TA=0°C to 70°C unless otherwise stated DC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 0.8 V Input Low Voltage VIL Input High Voltage VIH 2.0 V Input Low Current IIL VIN=0V (Pull-up) -20 µA Input High Current IIH VIN=VDD -5 Output Low Voltage VOL IOL=20.0mA Output High Voltage1 VOH IOH=-30mA 2.4 Output Low Current1 IOL VOL=0.8V 45 Output High Current1 IOH VOH=2.0V -55 -35 mA Supply Current IDD No load, 66 MHz 67 100 mA Output Frequency Change over Supply and Temperature1 FD With respect to typical frequency 0.002 0.01 % Short circuit current1 ISC Each output clock Pull-up resistor value1 RPU Input pin 1 Ci Except X1, X2 Load Capacitance1 CL Pins X1, X2 Input Capacitance 5 0.25 25 0.4 3.5 V V 65 mA 56 mA 680 kΩ 8 20 Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 4 µA pf pf ICS9158-03 Electrical Characteristics (continued) VDD = +5V±10%, TA=0°C to 70°C unless otherwise stated AC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Output Rise time, 0.8 to 2.0V (Note 1) tr 30pf load - 1 2.0 ns Rise time, 20% to 80% VDD (Note 1) tr 30pf load - 2.5 3 ns Output Fall time, 2.0 to 0.8V1 tf 30pf load - 0.5 2.0 ns Fall time, 80% to 20% VDD1 tf 30pf load - 1.5 3.0 ns Duty cycle1 dt 30pf load 45/55 48/52 55/45 % 0.5 2.0 % 2 5 % 250 ps Jitter, one sigma1 tj1s Jitter, absolute tjab Jitter, absolute tjab Input Frequency As compared with clock period 25-66MHz clocks -5 -250 fi Clock skew between CLK2A, CLK1(A-D) and CLK12(A-C) outputs Tsk Frequency Transition Time1 tft 14.318 -250 From 4 to 50 MHz 100 250 ps 13 20 ms Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 5 MHz ICS9158-03 Electrical Characteristics at 3.3V VDD = +3.3V±10%, TA=0°C to 70°C unless otherwise stated PARAM ETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Voltage Output High Voltage 1 Output Low Current1 Output High Current 1 Supply Current Output Frequency Change over Supply and Temperature 1 Short Circuit Current1 Pull-up Resistor Value 1 Input Capacitance 1 Load Capacitance 1 SYM BOL V IL V IH I IL I IH V OL V OH I OL I OH I DD DC Characteristics TEST CONDITIONS V IN =0V(Pull-up) V IN =V DD I OL =10mA I OH =-5mA V OL =0.2V DD V OH =0.7V DD No load, 66 M Hz FD With respect to typical frequency I SC R PU Ci CL Each output clock Input pin Except X1, X2 Pins X1, X2 M IN TYP M AX 0.2 VDD 30 -15 43 -10 70 UNITS V V µA µA V V mA mA mA 0.002 0.01 % 0.7 VDD -10 -5 0.1V DD 0.85V DD 20 25 56 900 mA kW pF pF 8 20 AC C h aracteristics PA R A M E T E R O utput R ise tim e, 0.8 to 2.0V 1 R ise tim e, 20% to 80% V D D 1 O utput Fall tim e, 2.0 to 0.8V 1 Fall tim e, 80% to 20% V D D 1 D uty cycle 1 Jitter, one sigm a 1 Jitter, absolute 1 Jitter, absolute 1 Input Frequency C lock skew w indow betw een C L K 2A , C L K 1(A -D ) C PU and C L K 12(A -C ) outputs 1 F requency Transition tim e 1 SY M B O L tr tr tf tf dt t j1s t jab t jab fi T E ST C O N D IT IO N S 30pF load 30pF 30pF 30pF 30pF load load load load A s com pared w ith clock period TYP M AX U N IT S - 1 2.5 ns 40/50 2.5 0.5 1.5 44/46 0.5 2 4.0 2.5 4.0 50/40 2.0 5 300 ns ns ns % % % ps MHz 100 250 ps 13 20 ms 25-66 M H z clocks 14.318 T sk t ft M IN From 4 to 50 M H z Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 6 ICS9158-03 LEAD COUNT DIMENSION L 24L 0.604 24 Lead SOIC Ordering Information ICS9158-03CW24 Example: ICS XXXX-PPP W Package Type W=(SOIC) 300mil Pattern Number (2 or 3 digit number for parts with ROM code patterns) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV=Standard Device; GSP=Genlock Device 7 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.