ICS ICS9177

Integrated
Circuit
Systems, Inc.
ICS9177
High Frequency System Clock Generator
General Description
Features
The ICS9177 is a multiple output clock generator ideal for
high speed processor system applications. A single highspeed internal VCO is utilized to derive up to four simultaneous
clock output frequencies. This enables output clock skew
matching and the minimization of clock jitter. The internal
VCO operates up to 350 MHz providing edge skew matched
output clocks.
•
•
One differential PECL (Positive ECL) output pair provides a
high speed processor clock. 12 TTL clock outputs are also
provided for other system functions, such as bus clocks. Input
selection pins are used to select the TTL output clock
frequencies.
•
•
•
•
•
•
Provides output frequencies up to 175 Mhz
Internal VCO is divided into four skew-matched output
frequencies (Out A, B, C, D)
External clock feedback provides input to output skew
matching
Differential PECL clock output pair provided for high
speed output (Out A)
12 TTL clock outputs (for Out B, C, D)
Single 5 volt power supply voltage
Internal loop filters
52-pin QFP package
For information about ICS9177 customization optics, please
contact ICS.
Block Diagram
Pin Configuration
52-Pin QFP
ICS9177RevB060297P
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
ICS9177
Pin Description
PIN
PIN
NUMNAME
BER
1
GND
2
REFCLK
TYPE
INPUT
3
FBCLK
INPUT
4
DSEL1#
INPUT
5
DSEL0#
INPUT
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
TESTEN
TSTCLK
NC
VCC
GND
PCOUT1
PCOUT0
GND
VCC
PBOUT1
PBOUT0
VCC
GND
PAOUT1
PAOUT0
VCC
GND
RESETL
BOUT1
BOUT0
VCC
GND
INPUT
INPUT
DESCRIPTION
from external oscillator
external PLL Feedback path
from one of the OutC
outputs
PLL divider mode control
(Contains internal pull-up
resistors)
Test mode ENABLE pin
External Test Clk
OUTPUT TTL - Group 2
OUTPUT Programmable clock outputs
PIN
NUMBER
28
COUT2
OUTPUT
29
30
31
32
COUT1
VCC
GND
COUT0
OUTPUT
33
DOUT0
34
35
GND
NC
36
AOUT1
37
AOUT0
38
39
NC
GND
ECL+5V
(same as
VCC)
NC
40
41
42
OUTPUT TTL - Group 1
OUTPUT Programmable clock outputs
*Internal pull-up resistor
2
DESCRIPTION
TTL - 25 MHz output clock
TTL - 25 MHz output clock
TTL - 12.5 MHz output
clock
OUTPUT ECL - 100 MHz, 75 MHz or
50 MHz based on DSEL(1:0)
OUTPUT pins
45
46
PCSEL1
INPUT
47
PCSEL0
INPUT
48
PBSEL1
INPUT
49
PBSEL0
INPUT
50
PASEL1
INPUT
51
52
PASEL0
VC
INPUT
44
INPUT Low true divider reset pin
OUTPUT
TTL - 50 MHz output clock
OUTPUT
TYPE
NC
ANALOG +5V
ANALOG +5V
AGND
43
OUTPUT TTL - Group 0
OUTPUT Programmable clock outputs
PIN
NAME
Programmable clock Group
C select
Programmable clock Group
B select
Programmable clock Group
A select
ICS9177
Typical System Usage
Example of System Block Diagram - Clocking
Function Tables
Table 1: Primary Function Table Typical System Usage
REF IN
(MHx)
DSEL1# DSEL0#
RSTL
TEST
f1
OUT
OUT
OUT
OUT
A
B
C
D
DESCRIPTION
25
0
0
1
0
200 MHz
f/4
f/4
f/8
f/16
Mode 0 - 1/1
25
0
1
1
0
f/4
f/6
f/12
f/24
Mode 1 - 3/2
33
1
0
1
0
300 Mhz
200/264
MHz
f/2
f/4
f/8
f/16
Mode 2 - 2/1
25
-
1
X
0
1
X
0
1
0
1
0
X
1
X
X
TCLK
1
0
f/2
1
0
f/2
1
0
f/4
1
0
f/8
Mode 3 - A ll 1
Reset Mode
Test Mode 0
-
0
1
1
1
0
1
1
1
1
1
1
1
TCLK
TCLK
TCLK
f/2
f/3
f/6
f/12
f/1
f/2
f/4
f/8
f/2
f/2
f/2
f/2
Test Mode 1
Test Mode 2
Test Mode 3
Table 2: CLOCK SELECT Blocks Function Table
PxSEL
1
PxSEL
0
0
0
Both outputs at the same frequency as Out B .
0
1
Both outputs at the same frequency as Out C .
1
0
Both outputs at the same frequency as Out D .
1
1
Both outputs disabled in the high state.
Function of CLOCK SELECT Blocks
Note: x=A, B, or C. (See Figure 1.)
3
ICS9177
Clock Output Timing Diagrams
1:1 frequency ratio - Mode 0
3:2 frequency ratio - Mode 1
2:1 frequency ratio - Mode 2
Note: The arrow indicates the point where the clock sequence starts to repeat.
4
ICS9177
Absolute Maximum Ratings
Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -.05V to VDD +.05V
Ambient operating temperature . . . . . . . . . . . . . . . . 0°C to +70°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Power Supply Specifications (Total Power consumption: approximately 750 mw)
Table 3: DC Specifications
Supply
VDD
I(typ)
150 mA
I(max)
200 mA
V(min)
4.75V
V(typ)
5V
V(max)
5.25V
AC/DC Input Specification
Table 4: AC Specification of Inputs
Pin Type
Vih(min)
Vil(max)
tr
tf
All
2V
0.8V
3
3
Note: tr and tf are typical values for input
AC/DC Characteristics
Table 5: AC Specification type Out A.pecl Pins (CPUCLK)
PARAMETER
Output High Voltage 1
Output Low Voltage 1
Output High Current
Output Low Current
Rise Time 10-90%
Fall Time 10-90%
Duty cycle at 100 MHz 2, 3
SYMBOL
Voh
Vol
Ioh
TEST CONDITIONS
Iol
tr
tf
dcyc
MIN
3.87
2.63
38.7
26.3
45
TYP
MAX
4.67
3.19
46.7
UNITS
volts
volts
ma
31.9
1
1
55
ma
ns
ns
%
Test Load Conditions: 100Ω, 15 pF.
Note 1: The pecl levels are standard 10 kHz positive ECL values as shown in the table above.
Note 2: Pin skew and Duty cycle are measured at the signal swing mid-point.
Note 3: The skew and duty cycle numbers reflect the recommended clock distribution method shown in Figure 2
5
ICS9177
Table 6: AC Specification type Out B.ttl Pins (50 MHz)
PARAMETER
Output High Voltage
SYMBOL
Voh
Output Low Voltage
Output High Current
Output Low Current
Rise Time 10-90%
Fall Time 10-90%
Pin skew to other OutB.ttl
signals 1
Duty cycle at 1.5V
Delay from OutA.pecl signals
Skew associated with above
delay 3
TEST CONDITIONS
Vol
Ioh
Iol
tr
tf
MIN
2.4
TYP
3.2
MAX
5
UNITS
volts
0
16
0.3
0.8
2
2
24
3
3
volts
mA
mA
ns
ns
250
500
ps
55
%
.5
ns
±0.5
ns
1
1
tsk
dcyc
2
45
tdly
.2
tdlyskw
Test Load Conditions: 500Ω, 15 pF.
Note 1: Pin skew is measured from the earliest rising edge of the group to the latest rising edge of the group.
Note 2: Delay is the intrinsic delay between the TTL drivers switching and the PECL driver switching. This is measured from
the OutA.pecl signal at the signal swing mid-point to max output of the OutB.ttl signal’s rising edge
Table 7: AC Specification type Out C.ttl Pins (25 MHz)
PARAMETER
Output High Voltage
SYMBOL
Voh
Output Low Voltage
Output High Current
Output Low Current
Rise Time 10-90%
Fall Time 10-90%
Pin skew to other OutC.ttl
signals 1
Duty cycle at 1.5V
Spread to OutB.ttl signals 2
TEST CONDITIONS
Vol
Ioh
Iol
tr
tf
MIN
2.4
TYP
3.2
MAX
5
UNITS
volts
0
16
0.3
0.8
1
1
2
2
24
3
3
volts
mA
mA
ns
ns
250
500
ps
55
500
%
ps
tsk
dcyc
tspb
45
Test Load Conditions: 500Ω, 15 pF.
Note 1: Pin skew is measured from the earliest rising edge of the group to the latest rising edge of the group.
Note 2: Spread is the absolute difference between the rising edge of any OutC.ttl signal and the rising edge of any OutB.ttl
signal
6
ICS9177
Table 8: AC Specification type Out D.ttl Pins (12.5 MHz)
PARAMETER
High Voltage
Low Voltage
High Current
Low Current
SYMBOL
Voh
Vol
Ioh
Iol
Rise Time 10-90%
Fall Time 10-90%
Pin skew to other OutD.ttl
signals
Duty cycle at 1.5V
Delay from OutA.pecl signals
Skew associated with above
delay 2
tr
tf
Output
Output
Output
Output
TEST CONDITIONS
MIN
2.4
0
16
MAX
3.2
0.3
UNITS
volts
volts
mA
mA
3
3
2
2
ns
ns
500
250
ps
24
1
1
tsk
dcyc
tdly
1
TYP
5
0.8
45
tdlyskw
55
.5
%
ns
±1.3
ns
Test Load Conditions: 500W, 15 pF.
Note 1: Delay is the intrinsic delay between the TTL drivers switching and the PECL driver switching. This is measured from
the OutA.pecl signal at the signal swing mid-point to max output of the OutD.ttl signal’s rising edge
7
ICS9177
52-Pin QFP Package
LEAD COUNT
BODY THICKNESS
FOOTPRINT (BODY+)
DIMENSIONS TOLERANCE
A
MAX.
A1
D
D1
E
E1
MAX.
±0.25
±0.10
±0.25
±0.10
L
e
b
ccc
±0.15/-0.10
BASIC
+0.05
MAX
44L
52L
64L
2.0
80L
100L
64L
80L
2.70
100L
3.20
2.45
3.40
0.25
13.20
10.0
13.20
10.0
17.20
14.00
17.20
14.00
0.70
0.80
0.88
1.00
0.25
17.20
14.00
23.20
20.00
0.88
1.00
0.80
0.65
0.30
0.35
1.00
0.80
0.35
0.65
0.30
0.10
0° - 7°
∝
Ordering Information
ICS9177-01CF52
Example:
ICS XXXX-PPP M X#W
Lead Count & Package Width
Lead Count=1, 2 or 3 digits
W=.3” SOIC or .6” DIP; None=Standard Width
Package Type
F=QFP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV=Standard Device; GSP=Genlock
8
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.