ICS ICS9178Y-03

ICS9178-03
Integrated
Circuit
Systems, Inc.
245 MHz Clock Generator and Integrated Buffer for PowerPC™
General Description
Features
The ICS9178-03 generates all clocks required for high speed
PowerPC RISC microprocessor systems. Generating clocks
in phase with an external reference frequency allows the
ICS9178-03 to be used as a multiplying zero delay buffer.
Three different multiplying factors are externally selectable.
These factors can be customized for specific applications. An
external frequency can be directly applied to aid system
testing. With 2X processor clock speeds up to 245 MHz,
PECL outputs are provided. User selectable frequency ratios
are available for PCLK/BCLK and PCLK/XCLK. Each pair of
clocks outputs have separate supply pins to minimize output
jitter and allow them to operate at 5V, 3.3V or custom voltage
levels.
•
•
•
•
•
•
•
•
•
•
Generates 2 PECL 2x processor, 2 TTL/CMOS 1x
processor and 10 selectable bus clocks
2XPCLK ranges from 75 MHz to 245 MHz (5V or
5V/3.3V mixed supply) or 60 to 170 MHz (3.3V only)
Asymmetric duty cycle bus clock for PowerPC
Bus to processor clock skews less than ±250ps
2XPCLK to PCLK skew controlled at 300 ±300ps
Selectable reference multiplying factors
Selectable PCLK/BCLK and PCLK/XCLK ratios
Separate supplies allow 5V and 3.3V output mix
3.0V - 5.5V supply range
44-pin PQFP package
Applications
•
Ideal for high-speed systems based on PowerPC
Block Diagram
PowerPC is a trademark of Motorola Corporation.
ICS9178-03 Rev C 02/12/98P
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
ICS9178-03
Pin Configuration
X_S1
X_S0
XCLK_(0,1)
0
0
PCLK
0
1
BCLK
1
0
DCLK
1
1
Tristate
_=A,B,C
44-Pin PQFP
Functionality
FS1
FS0
RST
TEN
*VCO
2XPCLK
PCLK
ABCLK (H/L%)
BCLK
DCLK
0
0
1
0
6x REF
VCO
VCO/2
VCO/6 (66/33)
VCO/6
VCO/4
0
1
1
0
8x REF
VCO
VCO/2
VCO/8 (75/25)
VCO/8
VCO/4
1
0
1
0
4x REF
VCO
VCO/2
VCO/12 (50/50)
VCO/4
VCO/4
1
1
1
0
X
1
1
1
1
1
X
X
0
X
X
0
0
0
0
0
0
0
1
1
TCLK
TCLK
TCLK/2
TCLK/6 (66/33)
TCLK/6
TCLK/4
0
1
1
1
TCLK
TCLK
TCLK/2
TCLK/8 (75/25)
TCLK/8
TCLK/4
1
0
1
1
TCLK
TCLK
TCLK/2
TCLK/12 ( 66/33)
TCLK/12
TCLK/4
1
1
1
1
TCLK
TCLK
TCLK/2
TCLK/2
TCLK/2
TCLK/4
*VCO range is limited from 75- 245 MHz at 5V ±5% and 60 - 170 MHz at 3.3V ±5%. Divide ratios assume BCLK is externally
fed back to FBCLK.
The 2XPCLK series or Thevinen trace terminations must be optimized for the specific operating frequency and board
layout. The rising edge of ABCLK is coincident with the rising edges of 2XPCLK, PCLK and other BCLKs.
2
ICS9178-03
Pin Description
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
32
XAS0
Input
LSB Programmable Group A frequency selector.
31
XAS1
Input
MSB Programmable Group A frequency selector.
6
XCLKA0
Output
TTL/CMOS group A programmable clock output.
5
XCLKA1
Output
TTL/CMOS group A programmable clock output.
30
XBS0
Input
LSB Programmable Group B frequency selector.
29
XBS1
Input
MSB Programmable Group B frequency selector.
3
XCLKB0
Output
TTL/CMOS Group B programmable clock output.
2
XCLKB1
Output
1
VDDXBA
—
Power for programmable Group A and B buffers (Pins 2, 3, 5, 6).
TTL/CMOS Group B programmable clock output.
4
GNDXBA
—
Ground for programmable Group A and B buffers (Pins 2, 3, 5, 6).
44
GNDXC
—
Ground for the programmable Group C buffers (Pins 42 and 43).
43
XCLKC0
Output
42
XCLKC1
Output
41
VDDXC
—
28
XCS0
27
XCS1
11
PCLK0
Output
TTL/CMOS 1X Processor clock output.
10
PCLK1
Output
TTL/CMOS 1X Processor clock output.
8
GNDP
—
Ground for PCLK output buffers (Pins 11 and 10).
7
VDDP
—
Power for PCLK output buffers (Pins 11 and 10).
22
2XPCLK0
Output
21
2XPCLK1
Output
24
EVDD
—
Power for PECL buffers (Pins 21 and 22).
23
EGND
—
Ground for PECL buffers (Pins 21 and 22).
20
EGND
—
Ground for PECL buffers (Pins 21 and 22).
38*
FS0
Input
37*
FS1
Input
MSB frequency select PLL (divider mode control).
36
FBCLK
Input
External PLL feedback path from one of the BCLK outputs.
35
REFCLK
Input
External reference clock input.
TTL/CMOS Group C programmable clock output.
TTL/CMOS Group C programmable clock output.
Power for the XC signal output buffers (Pins 42 and 43).
Input
LSB Programmable Group C frequency selector.
Input
MSB Programmable Group C frequency selector.
PECL 2X Processor clock output.
PECL 2X Processor clock output.
LSB frequency select PLL (divider mode control).
25
AVDD
—
Power for the analog PLL circuitry.
26
AGND
—
Ground for the analog PLL circuitry.
19
DCLK
Output
16
VDDD
—
Power for D output buffers (Pin 19).
17
GNDD
—
Ground for D output buffer (Pin 19).
15
BCLK0
Output
14
BCLK1
Output
13
GNDBAB
—
Ground for output buffers AB and B clocks (Pins 14, 15 & 18).
12
VDDBAB
—
Power for output buffers AB and B clocks (Pins 14, 15 & 18).
Output
TTL/CMOS D clock output.
TTL/CMOS B (Bus) clock output.
TTL/CMOS B (Bus) clock output.
18
ABCLK
40
TCLK
Input
TTL/CMOS AB Bus clock (has Asymmetric duty cycle).
39
TEN#
Input
Test enable (tie low).
9
RESET#
Input
Sync register reset (active low).
33
VDD
—
Digital power supply for 5.0 or 3.3V.
34
GND
—
Digital ground supply.
External test clock input.
*=Pin is pulled-up to VDD internally by the device.
3
ICS9178-03
Absolute Maximum Ratings
VDD referenced to GND . . . . . . . . . . . . . . . . . . . . . . 7V
Operating temperature under bias. . . . . . . . . . . . . . . . 0°C to +70°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Voltage on I/O pins referenced to GND. . . . . . . . . . . GND -0.5V to VDD +0.5V
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 Watts
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Electrical Characteristics
Device Specifications
Maximum Ratings
DESCRIPTION
Supply voltage relative to GND
Input voltage with respect to GND
SYMBOL
MIN
MAX
UNITS
VDD
-0.5
7.0
V
VIN
-0.5
VDD +0.5
V
Operating temperature
TOPER
0
+70
°C
Storage temperature
TSTOR
-65
+150
°C
Max soldering temperature (10 sec)
TSOL
+260
°C
Junction temperature
Tj
Package power dissipation
PDISS
+135
°C
900
mWatts
800
DC Characteristics
VDD =+5V ±5%, 0°C ≥ TAMBIENT ≥ +70°C unless otherwise stated
PARAMETER
SYMBOL
TEST CONDITIONS
High level input voltage
VIH
Low level input voltage
VIL
High level CMOS output voltage
VOH
IOH=-25mA
Low level CMOS output voltage
VOL
IOL=25mA
High level PECL output voltage
(2XPCLK) (Note 1)
VOHP
110 ohm load to ground
Low level PECL output voltage
(2XPCLK) (Note 1)
VOLP
110 ohm load to ground
MIN
TYP
MAX
2.0
V
0.8
2.4
V
V
0.4
1.9
UNITS
2.2
0.3
V
V
0.5
V
Input high current
IIH
VIH=VDD
Input low current (MSX pins, pull-up)
IIL1
VIL=0V
Input low current (other inputs)
IIL2
VIL=0V
-10
10
µA
Output leakage current (XCLKs)
IOZ
(tristate)
-10
10
µA
Power supply current
IDD
@240 MHz on
2XPCLK
145
185
mA
@75 MHz on 2XPCLK
80
100
mA
8
pF
Power supply current (typical) (Note 1)
Input capacitance (Note 1)
IDD-TYP
-10
CIN
Note 1: Parameter is guaranteed by design and characterization. Not tested 100% in production.
4
10
µA
-150
µA
ICS9178-03
AC Characteristics
VDD =+5V ±5%, 0°C ≥ TAMBIENT ≥ +70°C unless otherwise stated
PARAMETER
MIN
TYP
MAX
UNITS
fi
8
40.0
50.0
MHz
Input Clock Rise time (Note 1)
ICLKr
-
-
3
ns
Input Clock Fall time (Note 1)
ICLKf
-
-
3
ns
245
MHz
Input Frequency (Note 1)
SYMBOL
TEST CONDITIONS
Output Frequency (2XPCLK)
fo2XPCLK 6X mode, 8X mode
Output Rise time, 0.8 to 2.0V 20%
to 80% (Note 1)
tr2XPCLK
15pF load
Fall time 2.0 to 0.8 80% to 20%
(Note 1)
tf2XPCLK
15pF load
75
4X mode
240
-
-
t(TTL)r
15pF load
Output Fall time 80% to 20%
(Note 1)
t(TTL)f
15pF load
Duty cycle 2XPCLK (Note 1)
dt1
1.0
20% to 80%
-
-
1.5
2.0 to 0.8V
-
-
1.0
80% to 20%
Output Rise time 80% to 20%
(Note 1)
Pulse Width, High, 2XPCLK
(Note 1, 2)
Pulse Width, Low, 2XPCLK
(Note 1, 2)
75
0.8 to 2.0V
ns
ns
1.5
-
-
3.0
ns
-
-
2.0
ns
200 to 240 MHz @ 1.4V 110
ohm, 15pF load
42.5
50
57.5
%
Tpwr
@ 1.8V, 110ΩLoad 2
1.2
-
-
ns
Tpwr
@ 0.6V, 110ΩLoad 2
1.0
-
-
ns
70
75
80
%
%
Duty cycle ABCLK (Note 1)
dt3
15pF load @ 1.4V (8X mode)
Duty cycle ABCLK (Note 1)
dt4
15pF load @ 1.4V 6X mode
61
66
71
15pF load @ 1.4V 4X mode
45
50
55
15pF load @ 1.4V
45
50
55
%
Duty cycle TTL (other clocks)
(Note 1)
dt5
Jitter 1 Sigma 2XPCLK (10,000
samples) (Note 1)
Tj1s1
for 200 to 240 MHz on
2XPCLK
-
40
-
ps
Jitter 1 Sigma 1XPCLK B & D
(10,000 samples) (Note 1)
Tj1s2
for 200 to 240 MHz on
2XPCLK
-
50
-
ps
Jitter 1 Sigma AB clock (10,000
samples) (Note 1)
Tj1s3
for 200 to 240 MHz on
2XPCLK
-
60
-
ps
Jitter Absolute 2XPCLK (Note 1)
Tjabs1
for 200 to 240 MHz on
2XPCLK
-150
80
+150
ps
Jitter Absolute 1XPCLK, B, D
clocks (Note 1)
Tjabs2
for 200 to 240 MHz on
2XPCLK
-200
110
+200
ps
Jitter Absolute AB clock (Note 1)
Tjabs3
for 200 to 240 MHz on
2XPCLK
-250
120
+250
ps
Note 1: Parameter is guaranteed by design and characterization. Not tested 100% in production.
Note 2: For 70Ω Load, 2XPCLK level may be pulled-up with a 390Ω resistor to meet minimum pulse width requirements
at both 1.8V and 0.6V at 240 MHz.
5
ICS9178-03
AC Characteristics (continued)
VDD =+5V ±5%, 0°C ≥ TAMBIENT ≥ +70°C unless otherwise stated
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-125
80
+125
ps
Jitter Absolute 2XPCLK (Note 1)
Tjabs4
for 200 to 240 MHz on
2XPCLK at VDD 4.9 to
5.2V
Jitter Absolute 1XPCLK, B, D clocks
(Note 1)
Tjabs5
for 200 to 240 MHz on
2XPCLK at VDD 4.9 to
5.2V
-160
110
+160
ps
Jitter Absolute 2XPCLK (Note 1)
Tjabs6
for < 200 MHz on 2XPCLK
-200
-
+200
ps
Jitter Absolute 1XPCLK (Note 1)
Tjabs7
for < 200 MHz on 2XPCLK
-250
-
+250
ps
Jitter Absolute AB clock (Note 1)
Tjabs8
for < 200 MHz on 2XPCLK
-300
-
+300
ps
Skew, output to output (P, B, D , AB abd
XCLKs) (Note 1)
Tskew1
@ 1.4V
-250
-
+250
ps
Skew, 2XPCLK to PCLK (2XPCLK is
earlier than PCLK) (Note 1)
Tskew2
@ 1.4V
-600
-300
0
ps
Skew, 2XPCLK to REFCLK (2XPCLK is
earlier) (Note 1)
Tskew3
for 240 MHz on 2XPCLK
@ 1.4V
-600
-300
0
ps
Skew, 2XPCLK to DCLK (Notes 1,3)
Tskew4
@ 1.4V
-600
-100
100
ps
Note 1: Parameter is guaranteed by design and characterization. Not tested 100% in production.
Note 2: For 70Ω Load, 2XPCLK level may be pulled-up with a 390Ω resistor to meet minimum pulse width requirements
at both 1.8Vand 0.6Vat 240 Mhz.
Note 3: 2XPCLK is normally earlier than DCLK by up to 600ps and can be later by up to
6
ICS9178-03
Applications
Frequency Combinations
PwrPC 601/601+Processor Modules
(XCLK pairs selectable)
SYS
BUS
9178
MODE
2XPCLK
(2XCPU)
PCLK(0,1)
(CPU)
XCLK(0,5)
(BUS)
BCLK(0,1)
ABCLK
F
x4
4F
2F
2F, 1F
1F
F
x6
6F
3F
3F, 1.5F, 1F
1.5F
F
8F
8F
4F
4F, 2F, 1F
2F
Frequency Combinations
PwrPC 601\601+ System Clock Diagram
(selectable SCLK)
PwrPC 603/604 System Clock Diagram
OSC
9178
MODE
2XPCLK
(2XCPU)
PCLK
(CPU)
XCLK
(BUS)
F
x4
4F
2F
2F, 1F
1F
F
x6
6F
3F
3F, 1.5F, 1F
1.5F
Q (PCI)
F
8F
8F
4F
4F, 2F, 1F
2F
33
x4
132
66
66, 33
33
33
x6
196
99
99, 48, 33
33
33
x8
264
132
132, 66, 33
33
30
x4
120
60
60, 30
30
30
x6
180
90
90, 45, 30
30
30
x8
240
120
120, 60, 30
30
25
x4
100
50
50, 25
25
25
x6
150
75
75, 37, 25
25
25
x8
200
100
100, 50, 25
25
Frequency Combinations
(9178 x4 mode)
OSC
7
PwrPC
MODE
PCLK,
DCLK
(CPU)
PwrPC
INTERNAL
CLOCK
PCLK(0,1)
XCLK(0,3)
(BUS)
ABCLK,
BCLK(0,1)
XCLK(4,5)
F
-
2F, 1F
-
2F, 1F
F
33
x1, x2
66, 33
66
66, 33
33 PCI)
40
x1, x2
80, 40
80
80, 40
40 (VL)
33
x3
-, 33
100
66, 33
33 (PCI)
30
x2, x4
60, 30
120
60, 30
30 (PCI)
40
x3
-, 40
120
80, 40
40 (VL)
33
x2, x4
66, 33
132
66, 33
33 (PCI)
ICS9178-03
PQFP Package
LEAD COUNT
44L
BODY THICKNESS
2.0
FOOTPRINT (BODY+)
3.20
DIMENSIONS
TOLERANCE
A
MAX.
2.45
A1
MAX.
0.25
A2
±0.10
2.00
D
±0.25
13.20
D1
±0.10
10.0
E
±0.25
13.20
E1
±0.10
10.0
L
±0.15/-0.10
0.70
e
BASIC
0.80
b
+0.05
0.35
ccc
MAX.
0.10
∝
0° - 7°
Ordering Information
ICS9178Y-03
Example:
ICS XXXX- M PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
Y=QFP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS,AV=Standard
8
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.