Integrated Circuit Systems, Inc. ICS9159-12 Frequency Generator and Buffers for Mobile Pentium Systems General Description The ICS9159-12 generates all clocks required for mobile microprocessor systems based on Pentium/Mobile Triton chip sets. Three different reference frequency multiplying factors are externally selectable with smooth frequency transitions. These multiplying factors can be customized for specific plications. A test mode is provided to drive all clocks directly. High drive BCLK outputs provide greater than 1V/ns slew rate into 30pF loads. PCLK outputs provide better than 1V/ ns slew rate into 20pF loads while maintaining ±5% duty cycle. Block Diagram Features Generates 14 clocks including processor, disk and reference Meets all Pentium/Mobile Triton 82430MX requirments Independent buffers provide 4 and 6 clock copies Buffered clocks skew matched to ±250ps Buffer inputs are 5V tolerant Test clock mode eases system design Selectable multiplying and processor/bus ratios Custom configurations available 3.0V- 5.5V supply range 28pin, .209" SSOP package Pin Configuration Functionality FS1 FS0 *VCO X1, REF (MHz) CPU (MHz) 0 0 118/17*X1 14.318 50 (49.69) 0 1 65/7*X1 14.318 66.6 (66.47) 1 0 92/11*X1 14.318 60 (59.87) 1 1 Test mode TCLK TCLK/2 28-Pin SSOP *VCO range is limited form 60 - 200 MHz. CPU 24M VCO/2 24 MHz TCLK/2 TCLK/4 9159-12 Rev B 071797 Pentium is a trademark of Intel Corporation. ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9159-12 Pin Descriptions PIN NUMBER 8, 25 PIN NAME VDD TYPE PWR DESCRIPTION Power for logic, CPU and fixed frequency output buffers. XTAL or external reference frequency input. This input includes XTAL load capacitance and feedback bias for a 10 - 30 MHz XTAL. 1 X1 IN 2 X2 OUT 3 OEN IN OEN tristates all outputs when low. This input has an internal pull-up device. 4 BPIN IN Input to BPIN(0:5) buffers. 5 BHIN IN Input to BHIN(0:3) buffers. 11, 23 GND PWR 6, 7, 9, 10 BH(0:3) OUT 13, 12 FS(0:1) IN 14, 20 VDD PWR BP(0:5) OUT 24 CPU OUT 26 24M OUT The 24M clock is fixed at 24 MHz. REF(0:1) OUT REF is a buffered copy of the crystal oscillator or reference input clock, nominally 14.31818 MHz. 15, 16, 18 19, 21, 22 28, 27 XTAL output which includes XTAL load capacitance. Ground for logic, CPU and fixed frequency output buffers. Buffered copies of the BHIN input, typically used to drive the PCI device clock inputs at one half the CPU frequency. Frequency multiplier select pins. See table below. These inputs have internal pull-up devices. Power for BCLK output buffers. Buffered copies of the BPIN input, typically used to drive the host device clock inputs at the CPU frequency. 17 VSS PWR Ground for BCLK output buffers. The CPU output, which is a multiple of the input reference frequency as shown in the table above. Duty cycle is 50/50±5% with a maximum frequency of 100 MHz. Note: BCLK buffers cannot be supplied with 5 volts (Pins 14 and 20) if CPU and fixed frequencies (Pins 1, 8 and 26) are being supplied with 3 volts. 2 ICS9159-12 Absolute Maximum Ratings Supply Voltage .......................................................................................................... 7.0 V Logic Inputs ....................................................................... GND 0.5 V to VDD +0.5 V Ambient Operating Temperature ............................................................. 0°C to +70°C Storage Temperature ........................................................................... 65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 3.3V VDD = 3.0 3.7 V DC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Low Voltage VIL - - 0.2VDD V Input High Voltage VIH 0.7VDD - - V Input Low Current IIL VIN=0V - 10.5 28.0 µA Input High Current IIH VIN=VDD -5.0 - 5.0 µA Output Low Current IOL VOL=0.8V; for PCLKS & BCLKS 30.0 47.0 - mA Output High Current IOH VOL=2.0V; for PCLKS & BCLKS - -66.0 -42.0 mA Output Low Current IOL VOL=0.8V; for fixed CLKs 25.0 38.0 - mA Output High Current IOH VOL=2.0V; for fixed CLKs - -47.0 -30.0 mA Output Low Voltage VOL IOL=15mA; for PCLKS & BCLKS - 0.3 0.4 V Output High Voltage VOH IOH=-30mA; for PCLKS & BCLKS 2.4 2.8 - V Output Low Voltage VOL IOL=12.5mA; for fixed CLKs - 0.3 0.4 V Output High Voltage VOH IOH=-20mA; for fixed CLKs 2.4 2.8 - V Supply Current ICC @66.66 MHz; all outputs unloaded - 55 110 mA 3 ICS9159-12 Electrical Characteristics at 3.3V VDD = 3.0 3.7 V AC Characteristics PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Rise Time 0.8 to 2.0V Tr 20pF load - 1.5 3 ns Fall Time 2.0 to 0.8V Tf 20pF load - 0.9 2 ns Rise Time 20% to 80% Tr 20pF load - 2 4.5 ns Fall Time 80% to 20% Tf 20pF load - 1.8 4.25 ns Duty Cycle [CPU] Dt 20pF load 45 50 55 % Duty Cycle, [REF(0:1)] Dt 20pF load 40 - 60 % Jitter, One Sigma Tj1s CPU Clock; Load=20pF, FOUT>25 MHz - 50 150 ps Jitter, Absolute Tjab CPU Clock; Load=20pF, FOUT>25 MHz -250 - 250 ps Jitter, One Sigma Tj1s Fixed CLK; Load=20pF; Comp. to the period - 1 3 % Jitter, Absolute Tjab Fixed CLK; Load=20pF; Comp. to the period - 2 5 % Input Frequency Fi - 14.318 - MHz Clock Skew Window Tsk BH to BH; Load=20pF; @1.4V - 50 250 ps Clock Skew Window Tsk BP to BP; Load=20pF; @1.4V - 50 250 ps Clock Skew Window Tsk BH to BP; Load=20pF; @1.4V - 100 500 ps 4 ICS9159-12 COMMON DIMENSIONS SYMBOL MIN. NOM. MAX. A A1 A2 B C D E e H L N 0.068 0.002 0.066 0.010 0.005 0.078 0.008 0.070 0.015 0.008 ∝ 0° 0.073 0.005 0.068 0.012 0.006 See Variations 0.209 0.0256 BSC 0.307 0.030 See Variations 4° 0.205 0.301 0.022 D VARIATIONS 14 16 20 24 28 30 34 36 44 48 56 0.212 0.311 0.037 MIN. NOM. MAX. 0.239 0.239 0.278 0.318 0.397 0.397 0.701 0.602 0.701 0.620 0.720 0.244 0.244 0.284 0.323 0.402 0.402 0.706 0.607 0.706 0.625 0.725 0.249 0.249 0.289 0.328 0.407 0.407 0.711 0.612 0.711 0.630 0.730 8° SSOP Package Ordering Information ICS9159F-12 Example: ICS XXXX F-PPP Pattern Number(2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Device Type (consists of 3 or 4 digit numbers) Prefix ICS=Standard Device 5 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.