ICS ICS9342

Integrated
Circuit
Systems, Inc.
ICS9342
133MHz Clock Generator and Integrated Buffer for PowerPC™
Recommended Application:
Power PC System Clock
Output Features:
•
12- CPUs @ 3.3V, up to 146MHz
•
1- PCIREF @ 3.3V, up to 73MHz
•
1 - OUT 3.3V, 64MHz
•
1 - OUT/2 3.3V, OUT/2MHz
•
2 - REF @ 3.3V, 14.318MHz
Pin Configuration
Features:
•
Up to 146MHz frequency support
•
Support power management: CPU, PCI stop and power
down mode.
•
Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
•
Uses external 14.318MHz crystal
•
FS pins for frequency select
•
Support for industrial temperature range (-40C° to 85C°)
Functionality
PLL2
OUT
XTAL
OSC
2
CPU
DIVDER
Stop
12
REF (1:0)
PCI
DIVDER
Stop
Logic
FS (2:0)
PD#
PDFP#
TEST#
BOOST#
PCI
MHz
REF
MHz
1
133.33
33.33
14.318
0
100.00
33.33
14.318
83.33
33.33
14.318
66.66
33.33
14.318
133.33
66.66
14.318
100.00
66.66
14.318
83.33
66.66
14.318
66.66
66.66
14.318
FS2
FS1
FS0
1
1
1
1
1
1
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
0
1
0
0
1
1
0
0
0
CPUCLK (11:0)
OUTSEL (1:0)
Control
CPU
MHz
TEST
OUT/DIV2
/2
SS_EN#
OUTSEL1*
VDDCPU
GNDCPU
CPU0
CPU1
CPU2
VDDCPU
GNDCPU
CPU3
CPU4
CPU5
VDDCPU
GNDCPU
CPU6
CPU7
CPU8
VDDCPU
GNDCPU
CPU9
CPU10
CPU11
VDDCPU
GNDCPU
OUTSEL0*
* Internal pull-up resistor of 120K to VDD
on indicated inputs.
Block Diagram
PLL1
Spread
Spectrum
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48-Pin 300mil SSOP
Key Specifications:
•
CPU Output Skew: <200ps
•
CPU - PCI Output Skew: <500ps
•
CPU Output Jitter: <150ps
•
PCI Output Jitter: <500ps
X1
X2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS9342
VDDREF
REF1
REF0
GNDREF
X1
X2
*PD#
*CPU-STOP#
VDD
GND
*PCI_STOP#
*SS_EN#
VDDPCI
PCIREF
GNDPCI
*FS0
*FS1
*FS2
VDDFP
GNDFP
*TEST#/OUT
*BOOST#/OUT_DIV2
*PDFP#
VDDA
PCIREF
Config.
Reg.
9342 Rev E 9/06/00
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9342
General Description
The ICS9342 generates all clocks required for high speed PowerPC RISC microprocessor systems. With a zero delay buffer
chip such as the ICS9112-17 multiple PCI clock outputs can be generated in phase with PCIREF.
Spread Spectrum may be enabled by driving the SS_EN# pin low. Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9342
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Pin Configuration
PIN NUMBER
1
2,3
4
5
6
7
8
9
10
11
PIN NAME
VDDREF
REF[1:0]
GNDREF
X1
X2
PD#
CPU_STOP#
VDD
GND
PCI_STO P#
TYPE
PWR
OU T
PWR
IN
OU T
IN
IN
PWR
PWR
IN
12
SS_EN#
IN
13
14
15
18, 17, 16
19
20
VDDPCI
PCIREF
GNDPCI
FS (2:0)
VDDFP
GNDFP
O UT
PWR
OU T
PWR
IN
PWR
PER
OU T
TEST#
IN
22
OUT_D IV2
BOOST#
OU T
IN
23
PDFP#
IN
24
48, 25
26, 31, 36, 41, 46
27, 32, 37, 42, 47
VDDA
OUTSEL(1:0)
GNDCPU
VDDCPU
PWR
IN
PWR
PWR
21
Third party brands and names are the property of their respective owners.
DESCRIPTION
Ref(1:0), XTAL power supply, nominal 3.3V
14.318 M Hz reference clocks
Ground pin for the REF outputs
Crystal input,nominally 14.318M Hz.
Crystal output, nominally 14.318M Hz.
Pow ers down chip, active low .
Stops all CPUCLKs [11:0] at logic 0 level, w hen input low
3.3V power for the digital core.
Ground pin for the digital core.
Drives PCIREF to logic 0 level, when input low
Spread spectrum is turned on by driving this input low and turned off by
driving it high.
Pow er supply for PCIREF, nominal 3.3V.
Reference clock for PCI Zero Delay Buffer.
Ground pin for PCIREF.
Frequency select pins.
3.3V power for the Fixed PLL core.
Ground pin for the Fixed PLL core.
3.3V O UT reference clock.
Logic input to select over clocking or under clocking frequencies.
(latched input)
3.3V 1/2 frequency OUT reference clock.
Logic input to select normal or test mode frequencies. (latched input)
Pow ers down Fixed PLL. When driven to low, OUT and OUT_DIV2 clocks
will be stopped
3.3V power for the PLL core
Frequency select pins for OUT and OUT_DIV2 clocks.
Ground pin for CPU clocks.
3.3V power supply for CPU clocks.
2
ICS9342
Frequency Selection
BOOST#
TEST#
FS2
FS1
FS0
CPU
MHz
PCI
MHz
REF
MHz
SS TYPE/VALUE
If SS enabled
X
1
1
1
1
133.33
33.33
14.318 0 to -0.5% Down Spread
X
1
1
1
0
100.00
33.33
14.318 0 to -0.5% Down Spread
X
1
1
0
1
83.33
33.33
14.318 0 to -0.5% Down Spread
X
1
1
0
0
66.66
33.33
14.318 0 to -0.5% Down Spread
X
1
0
1
1
133.33
66.66
14.318 0 to -0.5% Down Spread
X
1
0
1
0
100.00
66.66
14.318 0 to -0.5% Down Spread
X
1
0
0
1
83.33
66.66
14.318 0 to -.5% Down Spread
X
1
0
0
0
66.66
66.66
14.318 0 to -0.5% Down Spread
1
0
1
1
1
146.62
36.6
14.318 + 0.25% Center Spread
1
0
1
1
0
109.99
36.6
14.318 + 0.25% Center Spread
1
0
1
0
1
91.58
36.6
14.318 + 0.25% Center Spread
1
0
1
0
0
73.31
36.6
14.318 + 0.25% Center Spread
1
0
0
1
1
146.62
73.3
14.318 + 0.25% Center Spread
1
0
0
1
0
109.99
73.3
14.318 + 0.25% Center Spread
1
0
0
0
1
91.58
73.3
14.318 + 0.25% Center Spread
1
0
0
0
0
73.31
73.3
14.318 + 0.25% Center Spread
0
0
1
1
1
119.98
30.00
14.318 + 0.25% Center Spread
0
0
1
1
0
90.00
30.00
14.318 + 0.25% Center Spread
0
0
1
0
1
74.93
30.00
14.318 + 0.25% Center Spread
0
0
1
0
0
0
0
0
1
1
119.98
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
Test Mode, CPU=Ref/4, PCI=Ref/8
60.00
14.318 + 0.25% Center Spread
90.00
60.00
14.318 + 0.25% Center Spread
74.93
60.00
14.318 + 0.25% Center Spread
Tristate, all outputs
OUT_SEL1
OUT_SEL0
OUT
(MHz)
OUT_DIV2
(MHz)
REF
(MHz)
1
1
48
24
14.318
1
0
40
20
14.318
0
1
64
32
14.318
0
0
48
48#
14.318
Third party brands and names are the property of their respective owners.
3
ICS9342
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T A = 0 - 70º C; Supply Voltage VD D = 3.3 V +/-5% (unles s otherwis e s tated)
PARAM ETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
Supply Current
Power Down
Supply Current
Input frequency
ID D 3 .3 P D
Input Capacitance 1
Transition Time
1
Settling Time 1
Clk Stabilization
Skew1
SYM BOL
VIH
VIL
IIH
IIL1
IIL2
IDD3.3 OP6 6
IDD3.3 OP8 3
IDD3 .3OP1 0 0
IDD3 .3OP1 3 3
1
CONDITIONS
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
Select @ 66M Hz; M ax discrete cap loads
Select @ 83M Hz; M ax discrete cap loads
Select @ 100M Hz; M ax discrete cap loads
Select @ 133M Hz; M ax discrete cap loads
-5
-200
VDD = 3.3 V
Logic Inputs
X1 & X2 pins
T Tran s
To 1st crossing of target Freq.
TS
From 1st crossing to 1% target Freq.
T STAB
From VDD = 3.3 V to 1% target Freq.
VT = 1.5 V
Third party brands and names are the property of their respective owners.
4
TYP
0.1
2.0
-100
134
165
198
254
M AX UNITS
VDD+0.3
V
0.8
V
µA
5
µA
µA
175
200
mA
225
300
313
400
µA
12
14.318
13.5
18
16
5
22.5
M Hz
pF
pF
3
ms
PD# = 0
Fi
C IN
C INX
t CP U -P CI
M IN
2
VSS -0.3
1
190
ms
3
500
ms
ps
ICS9342
Electrical Characteristics - CPU
T A = 0 - 70º C; V DD = 3.3 V +/-5%; C L = 20 pF (unless otherwise stated)
PARAM ETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
SYM BOL
RD SP 2 B
1
RD SN 2 B
VOH2 B
VOL2 B
IOH2 B
IOL2B
1
1
Rise Time
t r2 B
Fall Time
t f2 B 1
Duty Cycle
d t2 B 1
Skew
t sk 2 B 1
Jitter, Cycle-to-cycle
tj cy c-cyc2 B 1
1
CONDITIONS
M IN
TYP
M AX
UNITS
VO = VD D *(0.5)
13.5
20
45
Ω
VO = VD D *(0.5)
IOH = -8.0 mA
IOL = 12 mA
VOH =1.7 V
VOL = 0.7 V
13.5
2
29
2.4
0.32
-37
26
45
Ω
V
V
mA
mA
19
0.4
-16
VOL = 0.4 V, VOH = 2.4 V
1.13
2
ns
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V; [email protected] 66M , 83M , 100M
VT = 1.5 V; [email protected] & 146.6M
VT = 1.5 V
VT = 1.5 V; Normal
VT = 1.5 V; Spread, CPU = 91.58M Hz
VT = 1.5 V; Spread, CPU remaining freq.
1.27
52
56
187
95
143
143
2
56
60
200
150
200
175
ns
45
51
%
ps
ps
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCI
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL =30 pF
PARAMETER
SYMBOL
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
1
RDSN1
VOH1
VOL1
IOH1
IOL1
CONDITIONS
MIN
TYP
MAX UNITS
VO = VDD*(0.5)
12
21
55
Ω
VO = VDD*(0.5)
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
12
2.4
21.2
55
Ω
0.4
-22
25
0.17
-60
47
V
mA
mA
1
tr1
VOL = 0.4 V, VOH = 2.4 V
0.5
1
2
ns
Fall Time1
tf1
VOH = 2.4 V, VOL = 0.4 V
0.5
0.9
2
ns
Duty Cycle1
Jitter, Cycle-to-cycle1
dt1
tjcyc-cyc1
VT = 1.5 V
VT = 1.5 V
45
50
170
55
500
%
ps
Rise Time
1
RDSP1
1
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
5
ICS9342
Electrical Characteristics - REF, OUT , OUT /2
T A = 0 - 70º C; V DD = 3.3 V +/-5%; C L = 20 pF (unless otherwise stated)
SYM BOL
PA RA M ETER
Ris e Time
1
1
Duty Cycle
Ris e Time
OUT
Fall Time
1
Ris e Time
Fall Time
1
1
1
Duty Cycle
Jitter, Cycle-to-cycle1
Jitter, Cycle-to-cycle 1
1
1
1
Duty Cycle
OUT/2
VO = VD D *(0.5)
20
34
60
Ω
VO = VD D *(0.5)
IO H = -12 mA
IO L = 10 mA
VO H = 2.0 V
VO L = 0.8 V
20
2.4
60
16
31
2.9
0.33
-30
23
Ω
V
V
mA
mA
t r5
VO L = 0.4 V, VO H = 2.4 V; OUT
1.5
1.8
4
ns
t f5
VO H = 2.4 V, VO L = 0.4 V; OUT
1.5
2
4
ns
d t5
VT = 1.5 V; OUT
45
52
55
%
t r5
VO L = 0.4 V, VO H = 2.4 V; OUT/2
1.5
2.2
4
ns
t f5
VO H = 2.4 V, VO L = 0.4 V; OUT/2
1.5
2.1
4
ns
d t5
VT = 1.5 V; OUT/2
45
50
55
%
t r5
VO L = 0.4 V, VO H = 2.4 V; REF
1.5
2.7
4
ns
t f5
VO H = 2.4 V, VO L = 0.4 V; REF
1.5
2.8
4
ns
VT = 1.5 V; REF
VT = 1.5 V; OUT, OUT/2
VT = 1.5 V; REF
45
50
280
55
500
%
ps
450
1000
ps
RD SN 5
VO H 5
VO L 5
IO H 5
IO L 5
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Fall Time
TYP
RD SP 5
Output Impedance
REF
M IN
1
1
1
d t5
t jcy c-cy c5
t jcy c-cy c5
CONDITIONS
Guaranteed by des ign, not 100% tes ted in production.
Third party brands and names are the property of their respective owners.
6
M A X UNITS
0.4
-20
ICS9342
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
The I/O pins designated by (input/output) on the ICS9342
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid
CMOS programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K Via to Gnd
Device
Pad
8.2K Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
7
ICS9342
Power Management
PD#
PDFP#
OUT1, OUT_DIV2
CPU, PCI, REF
1
1
RUNNING
RUNNING
1
0
STOPPED
RUNNING
0
1
STOPPED
STOPPED
0
0
STOPPED
STOPPED
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the
clock synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to
a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power
down latency should be as short as possible but conforming to the sequence requirements shown below. The REF and OUT
clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and
holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPU
PCIREF
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPU (defined as inside the ICS9342 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
Third party brands and names are the property of their respective owners.
8
ICS9342
CPU_STOP# Timing Diagram
CPU_STOP# is an asynchronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is asserted asynchronously by the external clock control logic with the rising edge of free running PCI clock
(and hence CPU clock) and must be internally synchronized to the external output. All other clocks will continue to run while
the CPU clocks are disabled. The CPU clocks must always be stopped in a low state and started in such a manner as to
guarantee that the high pulse width is a full pulse.
CPUCLK
(internal)
PCICLK
(internal)
CPU_STOP#
PCI_STOP#
PD#
CPUCLK
(externall)
Notes:
1. All timing is referenced to the internal CPUCLK.
2. The internal label means inside the chip and is a reference only. This in fact may not be the way that the control is designed.
3. PD# and PCI_STOP# are shown in a high state.
PCI_STOP# Timing Diagram
PCI_STOP# is an input to the clock synthesizer. It is used to turn off the PCIREF clock for low power operation. PCIREF clock
is required to be stopped in a low state and started such that a full high pulse width is guaranteed.
CPUCLK
(internal)
PCICLK
(internal)
CPU_STOP#
PCI_STOP#
PD#
PCIREF
(externall)
Notes:
1. All timing is referenced to CPUCLK.
2. Internal means inside the chip.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high state.
Third party brands and names are the property of their respective owners.
9
ICS9342
SYMBOL
In Millimeters
COMMON DIMENSIONS
MIN
MAX
In Inches
COMMON DIMENSIONS
MIN
MAX
A
2.413
2.794
.095
A1
0.203
0.406
.008
.016
b
0.203
0.343
.008
.0135
c
D
0.127
0.254
SEE VARIATIONS
.005
.010
SEE VARIATIONS
E
10.033
10.668
.395
.420
E1
7.391
7.595
.291
.299
e
0.635 BASIC
h
0.381
L
0.508
1.016
SEE VARIATIONS
N
α
0.635
0°
.110
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
8°
0°
8°
MIN
MAX
MIN
MAX
28
9.398
9.652
.370
.380
34
11.303
11.557
.445
.455
48
15.748
16.002
.620
.630
56
18.288
18.542
.720
.730
64
20.828
21.082
.820
.830
VARIATIONS
D mm.
N
D (inch)
Ordering Information
ICS9342yF-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
10
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.