Integrated Circuit Systems, Inc. ICS9248-114 AMD - K7™ System Clock Chip Pin Configuration VDD1 REF0/CPU_STOP#* GND X1 X2 VDD2 *MODE/PCICLK_F *FS3/PCICLK0 GND *SEL24_48#/PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDD2 BUFFER IN GND SDRAM11 SDRAM10 VDD3 SDRAM9 SDRAM8 GND SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 ICS9248-114 Recommended Application: VIA K7 style chipset Output Features: • 1 - Differential pair open drain CPU clocks • 1 - Single-ended open drain CPU clock • 13 - SDRAM @ 3.3V • 6 - PCI @3.3V, • 1 - 48MHz, @3.3V fixed. • 1 - 24/48MHz @ 3.3V • 2 - REF @3.3V, 14.318MHz. Features: • Up to 155MHz frequency support • Support power management: CPU stop and Power down Mode from I2C programming. • Spread spectrum for EMI control (0 to -0.5% down spread, ± 0.25% center spread). • Uses external 14.318MHz crystal Skew Specifications: • CPUT – CPUC: <200ps • PCI – PCI: <500ps • CPU – PCI: <500ps 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF1/FS2* GND CPUCLKT1 GND CPUCLKC0 CPUCLKT0 VDDL PD#* SDRAM_OUT GND SDRAM0 SDRAM1 VDD3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDD3 SDRAM6 SDRAM7 VDD4 48MHz/FS0* 24/48MHz/FS1* 48-Pin 300mil SSOP * Internal Pull-up Resistor of 120K to VDD Functionality Block Diagram PLL2 48MHz 24_48MHz /2 X1 X2 XTAL OSC PLL1 Spread Spectrum REF (1:0) CPU DIVDER Stop CPUCLKC0 CPUCLKT (1:0) SEL24_48# Control SDATA SCLK Logic FS (3:0) Config. PD# CPU_STOP# Reg. PCI DIVDER PCICLK (4:0) PCICLK_F SDRAM DRIVER BUFFER IN 9248-114 Rev C 01/24/01 Third party brands and names are the property of their respective owners. SDRAM (11:0) SDRAM_OUT FS3 FS2 FS1 FS0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 124.00 75.00 83.30 66.80 103.00 112.00 133.30 100.00 120.00 115.00 110.00 105.00 140.00 150.00 124.00 133.30 PCICLK (MHz) 41.33 37.50 41.65 33.40 34.33 37.33 44.43 33.33 40.00 38.33 36.67 35.00 35.00 37.50 31.00 33.33 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-114 Pin Descriptions PIN NUMBER 1 P I N NA M E VDD1 REF0 TYPE PWR OUT 2 CPU_STOP#1, 2 3,9,16,22, 33,39,45, 47 GND IN PWR 4 X1 IN 5 X2 OUT VDD2 PWR PCICLK_F OUT 6,14 7 MODE1, 2 8 10 13, 12, 11 15 17, 18, 20, 21, 28, 29, 31, 32, 34, 35,37,38 19,30,36 23 24 25 26 IN DESCRIPTION REF, XTAL power supply, nominal 3.3V 14.318 Mhz reference clock.This REF output is the STRONGER buffer for ISA BUS loads This asynchronous input halts CPUCLKT, CPUCLKC & SDRAM at logic "0" level when driven low. Ground Crystal input, has internal load cap (36pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (36pF) Supply for PCICLK_F and PCICLK, nominal 3.3V Free running PCI clock not affected by PCI_STOP# for power management. Pin 2 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. Frequency select pin. Latched Input. Internal Pull-down to GND PCI clock output Logic input to select 24 or 48MHz for pin 25 output PCI clock output. PCI clock outputs. Input to Fanout Buffers for SDRAM outputs. FS31, 2 PCICLK0 SEL24_48#1, 2 PCICLK1 PCICLK (4:2) BUFFER IN IN OUT IN OUT OUT IN SDRAM (11:0) OUT SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset). VDD3 SDATA SCLK PWR IN IN Supply for SDRAM nominal 3.3V. Data input for I2C serial input, 5V tolerant input Clock input of I2C input, 5V tolerant input 24_48MHz OUT 24MHz/48MHz clock output FS11, 2 IN 48MHz OUT FS0 1, 2 IN Frequency select pin. Latched Input. 48MHz output clock Frequency select pin. Latched Input 27 VDD4 PWR Power for 24 & 48MHz output buffers and fixed PLL core. 40 SDRAM_OUT OUT Reference clock for SDRAM zero delay buffer 41 PD#1, 2 IN 42 VDD PWR CPUCLKT (1:0) OUT 44 CPUCLKC0 OUT 48 REF1 FS21, 2 OUT IN 46, 43 Powers down chip, active low Supply for core 3.3V "True" clocks of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. "Complementory" clocks of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. 14.318 MHz reference clock. Frequency select pin. Latched Input Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low. Third party brands and names are the property of their respective owners. 2 ICS9248-114 General Description The ICS9248-114 is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all clocks required for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-114 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection. Mode Pin - Power Management Input Control MODE, Pin 7 (Latched Input) Pin 2 0 CPU_STOP# (Input) REF0 (Output) 1 Third party brands and names are the property of their respective owners. 3 ICS9248-114 Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = 0) Bit Bit 2, Bit 7:4 Bit 3 Bit 1 Bit 0 Description CPUCLK PCICLK Bit (2, 7, 6, 5, 4) (MHz) (MHz) 0 0 0 0 0 124.00 41.33 0 0 0 0 1 75.00 37.50 0 0 0 1 0 83.30 41.65 0 0 0 1 1 66.80 33.40 0 0 1 0 0 103.00 34.33 0 0 1 0 1 112.00 37.33 0 0 1 1 0 133.30 44.43 0 0 1 1 1 100.00 33.33 0 1 0 0 0 120.00 40.00 0 1 0 0 1 115.00 38.33 0 1 0 1 0 110.00 36.67 0 1 0 1 1 105.00 35.00 0 1 1 0 0 140.00 35.00 0 1 1 0 1 150.00 37.50 0 1 1 1 0 124.00 31.00 0 1 1 1 1 133.30 33.33 1 0 0 0 0 90.00 30.00 1 0 0 0 1 92.50 30.83 1 0 0 1 0 95.00 31.67 1 0 0 1 1 97.50 32.50 1 0 1 0 0 101.50 33.83 1 0 1 0 1 127.00 42.33 1 0 1 1 0 136.50 34.13 1 0 1 1 1 100.00 33.33 1 1 0 0 0 120.00 40.00 1 1 0 0 1 117.50 39.17 1 1 0 1 0 122.00 40.67 1 1 0 1 1 107.50 35.83 1 1 1 0 0 145.00 36.25 1 1 1 0 1 155.00 38.75 1 1 1 1 0 130.00 32.50 1 1 1 1 1 133.30 33.32 0 - Frequency is selected by hardware select, Latched Inputs 1 - Frequency is selected by Bit 2, 7:4 0 - Normal 1 - Spread Spectrum Enabled 0 - Running 1- Tristate all outputs PWD Spread Precentage ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread -0.5% Down Spread -0.5% Down Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread ±0.25% Center Spread -0.5% Down Spread Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. The I2C readback of the power up default could indicate the manufacture ID in bits 2, 7:4 as shown. Third party brands and names are the property of their respective owners. 4 00100 Note1 0 1 0 ICS9248-114 Byte 1: CPU, Active/Inactive Register (1= enable, 0 = disable) Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable) BIT PIN# PWD Bit 7 - X FS2# DESCRIPTION Bit 6 - 1 (Reserved) Bit 5 Bit 5 - 1 (Reserved) Bit 4 - X FS3# Bit 3 40 1 SDRAM_OUT Bit 2 - X Bit 1 43,44 1 Bit 0 46 1 BIT (SEL24_48#)# CPUCLK0 enable (both differential pair. "True" and Complimentary") CPUCLKT enable Byte 3: SDRAM, Active/Inactive Register (1= enable, 0 = disable) BIT PIN# PWD PIN# PWD DESCRIPTION Bit 7 - X FS0# Bit 6 7 1 PCICLK_F - 1 (Reserved) Bit 4 13 1 PCICLK4 Bit 3 12 1 PCICLK3 Bit 2 11 1 PCICLK2 Bit 1 10 1 PCICLK1 Bit 0 8 1 PCICLK0 Byte 4: SDRAM , Active/Inactive Register (1= enable, 0 = disable) BIT DESCRIPTION PIN# PWD DESCRIPTION Bit 7 - 1 (Reserved) Bit 7 28 1 SDRAM 7 Bit 6 - 1 (Reserved) Bit 6 29 1 SDRAM 6 31 1 SDRAM 5 Bit 5 26 1 48MHz Bit 5 Bit 4 25 1 24_48MHz Bit 4 32 1 SDRAM 4 Bit 3 17 1 SDRAM 11 Bit 3 34 1 SDRAM 3 Bit 2 18 1 SDRAM 10 Bit 2 35 1 SDRAM 2 Bit 1 20 1 SDRAM 9 Bit 1 37 1 SDRAM 1 Bit 0 21 1 SDRAM 8 Bit 0 38 1 SDRAM 0 Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable) BIT PIN# PWD Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable) BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DESCRIPTION Bit 7 - 1 (Reserved) Bit 6 - 1 (Reserved) Bit 5 - 1 (Reserved) Bit 4 - X MODE# Bit 3 - X FS1# Bit 2 - 1 (Reserved) Bit 1 48 1 REF1 Bit 0 2 1 REF0 PIN# - PWD 0 0 0 0 0 1 1 0 DESCRIPTION R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) Note: Don’t write into this register, writing into this register can cause malfunction Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions. Third party brands and names are the property of their respective owners. 5 ICS9248-114 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN = VDD VIN = 0V; Inputs with no pull-up resistors Input Low Current IIL1 VIN = 0V; Inputs with pull-up resistors Input Low Current IIL2 CL = 0 pF; Select @ 66 MHz IDD3.3OP66 Operating Supply CL = 0 pF; Select @ 100 MHz IDD3.3OP100 Current CL = 0 pF; Select @ 133 MHz IDD3.3OP133 CL = 0 pF; Input address to VDD or GND Powerdown Current IDD3.3PD Input Frequency Input Capacitance1 1 Clk Stabilization Skew1 Fi CIN CINX VDD = 3.3 V Logic Inputs X1 & X2 pins MIN 2 VSS-0.3 TYP MAX VDD+0.3 0.8 5 180 180 180 600 UNITS V V µA µA µA mA mA mA µA 16 5 45 MHz pF pF -5 -200 12 14.318 27 TSTAB TCPU-PCI TCPU-PCI From VDD = 3.3 V to 1% target frequency CPU VT = VX, PCI VT = 1.5V, CPU=66MHz -100 CPU VT = VX, PCI VT = 1.5V, CPU=100MHz -100 -5509 -2946 3 100 100 ms ps ps TCPU-PCI CPU VT = VX, PCI VT = 1.5V, CPU=133MHz -100 -1637 100 ps 1 Guaranteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 6 ICS9248-114 Electrical Characteristics - CPUCLK (Open Drain) T A = 0 - 70º C; VDD = 3.3 V +/-5%; C L = 20 pF (unless otherwise stated). PARAM ETER SYMBOL Output Impedance Z O1 Output High Voltage Output Low Voltage Output Low Current Rise Time Fall Time Duty Cycle Differential Voltage-AC Differential Voltage-DC Differential Crossover Voltage Skew VOH2B VOL2B IOL2 B Jitter, Cycle-to-cycle CONDITIONS MIN MAX UNITS 60 Ω 1.2 0.4 V V 45 1.93 0.81 49.3 2.6 2.6 55 mA ns ns % 1.18 Vpull-up (external) + 0.6 V Vpull-up (external) + 0.6 V 958 1100 mV 94 158 200 250 ps ps t r2 B1 t f2 B1 d t2B 1 Termination to Vpu ll-u p (external) Termination to Vpu ll-u p (external) VOL = 0.3 V VOL = 0.3 V, VOH = 1.2 V VOH = 1.2 V, VOL = 0.3 V VT = VX VDIF1 Note 2 0.4 VDIF1 Note 2 0.2 VX1 Note 3 550 t sk2B1 t jcyc-cyc2B TYP VO = VX 1 VT = 1.5 V VT = VX 1 18 Notes: 1 - Guaranteed by design, not 100% tested in production. 2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true" input level and VCP is the "complement" input level. 3 - Vpull-up(external) = 1.5V, Min = (Vpull-up(ex ternal)/2) - 150mV; M ax = (Vp ull-up(extern al)/2) + 150mV Electrical Characteristics - SDRAM TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH3 IOH = -28 mA Output Low Voltage VOL3 IOL = 20 mA IOH3 VOH = 2.0 V Output High Current IOL3 VOL = 0.8 V Output Low Current 1 Rise Time 1 Fall Time 1 Duty Cycle Skew window1 Propagation Time1 (Buffer In to Output) MIN 2.4 41 TYP 3 0.18 -110 86 MAX 0.4 -40 UNITS V V mA mA tr3 VOL = 0.4 V, VOH = 2.4 V 1.42 2 ns tf3 dt3 VOH = 2.4 V, VOL = 0.4 V 1.78 2 ns 56.7 55 % tsk3 VT = 1.5 V 225 250 ps Tprop VT = 1.5 V 3.41 VT = 1.5 V 45 1 Guaranteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 7 ns ICS9248-114 Electrical Characteristics - PCICLK TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS IOH = -11 mA Output High Voltage VOH1 Output Low Voltage VOL1 IOL = 9.4 mA IOH1 VOH = 2.0 V Output High Current IOL1 VOL = 0.8 V Output Low Current 1 Rise Time MIN 2.4 41 TYP 3.15 0.13 -97 69 MAX 0.4 -40 UNITS V V mA mA tr1 VOL = 0.4 V, VOH = 2.4 V 1.69 2.0 ns tf1 dt1 VOH = 2.4 V, VOL = 0.4 V 1.75 2.0 ns 51.7 55 % Skew window tsk1 VT = 1.5 V 400 500 ps Jitter,Cycle-to-Cycle1 tjcyc-cyc1 VT = 1.5 V -500 135 500 ps MIN 2.4 TYP 3.15 0.13 -97 69 MAX UNITS V V mA mA 1 Fall Time Duty Cycle 1 1 VT = 1.5 V 45 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - PCICLK_F TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS IOH = -11 mA Output High Voltage VOH1 Output Low Voltage VOL1 IOL = 9.4 mA IOH1 VOH = 2.0 V Output High Current IOL1 VOL = 0.8 V Output Low Current 1 Rise Time 41 0.4 -40 tr1 VOL = 0.4 V, VOH = 2.4 V 1.90 2.0 ns tf1 dt1 VOH = 2.4 V, VOL = 0.4 V 1.79 2.0 ns 49.9 55 % Skew window1 tsk1 VT = 1.5 V 400 500 ps Jitter,Cycle-to-Cycle1 tjcyc-cyc1 VT = 1.5 V 110 500 ps 1 Fall Time Duty Cycle 1 VT = 1.5 V 45 -500 1 Guaranteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 8 ICS9248-114 Electrical Characteristics - REF, 48MHz, 24MHz TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Output High Voltage VOH5 IOH = -16 mA IOL = 9 mA Output Low Voltage VOL5 IOH5 VOH = 2.0 V Output High Current IOL5 VOL = 0.8 V Output Low Current 1 Rise Time 1 Fall Time 1 Duty Cycle Jitter, Jitter, 1 Cycle-to-Cycle 1 Cycle-to-Cycle MIN 2.4 16 TYP 3.03 0.23 -50 40 MAX 0.4 -22 UNITS V V mA mA tr5 VOL = 0.4 V, VOH = 2.4 V 1.47 4.0 ns tf5 dt5 VOH = 2.4 V, VOL = 0.4 V 1.98 4.0 ns 54.4 55 % 552 1000 ps 421 500 ps VT = 1.5 V tjcyc-cyc5, Ref VT = 1.5 V tjcyc-cyc5, Fixed VT = 1.5 V 45 -1 1 Guaranteed by design, not 100% tested in production. Third party brands and names are the property of their respective owners. 9 ICS9248-114 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: • • • • • • • • • • • • • • • • Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 • ICS clock will acknowledge each byte one at a time. • Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ICS (Slave/Receiver) ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. Third party brands and names are the property of their respective owners. 10 ICS9248-114 Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) on the ICS9248114 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K Via to Gnd Device Pad 8.2K Clock trace to load Series Term. Res. Fig. 1 Third party brands and names are the property of their respective owners. 11 ICS9248-114 CPU_STOP# Timing Diagram CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-114. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks. INTERNAL CPUCLK PCICLK CPU_STOP# PD# (High) CPUCLKT (1:0) CPUCLKC0 Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9248-114. 3. All other clocks continue to run undisturbed. Third party brands and names are the property of their respective owners. 12 ICS9248-114 PD# Timing Diagram The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. PD# CPUCLKT CPUCLKC PCICLK VCO Crystal Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-114 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz. Third party brands and names are the property of their respective owners. 13 ICS9248-114 SYMBOL In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A 2.413 2.794 .095 .110 A1 0.203 0.406 .008 .016 b 0.203 0.343 .008 .0135 c D 0.127 0.254 SEE VARIATIONS .005 .010 SEE VARIATIONS E 10.033 10.668 .395 .420 E1 7.391 7.595 .291 .299 e 0.635 BASIC h 0.381 L 0.508 1.016 SEE VARIATIONS N α 0.025 BASIC 0.635 0° .015 .025 .020 .040 SEE VARIATIONS 8° 0° 8° MIN MAX MIN MAX 15.748 16.002 .620 .630 JEDEC MO-118 DOC# 10-0034 6/1/00 REV B VARIATIONS D mm. N 48 D (inch) Ordering Information ICS9248yF-114-T Example: ICS XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device Third party brands and names are the property of their respective owners. 14 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.