ICS ICS94215YF-T

ICS94215
Integrated
Circuit
Systems, Inc.
Programmable System Clock Chip for AMD - K7™ Processor
Recommended Application:
VIA KX/KT133 style chipset
Output Features:
•
1 - Differential pair open drain CPU clocks
•
1 - CPU clock @ 3.3V
•
13 - SDRAM @ 3.3V
•
6 - PCI @3.3V,
•
1 - 48MHz, @3.3V fixed.
•
1 - 24/48MHz @ 3.3V
•
2 - REF @3.3V, 14.318MHz.
Features:
•
Programmable ouput frequency.
•
Programmable ouput rise/fall time.
•
Programmable PCI_F and PCICLK skew.
•
Spread spectrum for EMI control typically
by 7dB to 8dB,
with programmable spread percentage.
•
Watchdog timer technology to reset system
if over-clocking causes malfunction.
•
Uses external 14.318MHz crystal.
•
FS pins for frequency select
PLL2
48MHz
24_48MHz
/2
XTAL
OSC
REF (1:0)
CPUCLK
PLL1
Spread
Spectrum
CPU
DIVDER
Stop
CPUCLKC0
CPUCLKT0
SEL24_48#
Control
SDATA
SCLK
Logic
FS (3:0)
Config.
PD#
CPU_STOP#
BUFFER IN
0442C—07/03/02
Reg.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF1/FS2*
GND
CPUCLK
GND
CPUCLKC0
CPUCLKT0
VDDCPU
PD#*
SDRAM_OUT
GND
SDRAM0
SDRAM1
VDD3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD3
SDRAM6
SDRAM7
VDD4
48MHz/FS0*
24/48MHz/FS1*
48-Pin 300mil SSOP
*
Internal Pull-up Resistor of 120K to VDD
Functionality
Block Diagram
X1
X2
VDD1
REF0/CPU_STOP#*
GND
X1
X2
VDD2
*MODE/PCICLK_F
*FS3/PCICLK0
GND
*SEL24_48#/PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDD2
BUFFER IN
GND
SDRAM11
SDRAM10
VDD3
SDRAM9
SDRAM8
GND
SDATA
SCLK
ICS94215
Pin Configuration
PCI
DIVDER
PCICLK (4:0)
PCICLK_F
SDRAM
DRIVER
SDRAM (11:0)
SDRAM_OUT
FS3
FS2
FS1
FS0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
(MHz)
90.00
95.00
101.00
102.00
100.90
103.00
105.00
100.00
107.00
109.00
110.00
111.00
113.00
115.00
117.00
133.30
PCICLK
(MHz)
30.00
31.67
33.67
34.00
33.57
34.33
35.00
33.33
35.67
36.33
36.67
37.00
37.67
38.33
39.00
33.33
ICS94215
Pin Descriptions
PIN NUMBER
1
PIN NAME
VDD1
REF0
2
CPU_STOP#1, 2
3,9,16,22,
33,39,45, 47
GND
TYPE
DESCRIPTION
P W R Ref (0:2), XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.This REF output is the
OUT
STRONGER buffer for ISA BUS loads
This asynchronous input halts CPUCLKT, CPUCLKC & at logic
IN
"0" level when driven low.
PWR
4
X1
IN
5
X2
OUT
VDD2
PWR
PCICLK_F
OUT
6,14
7
MODE1, 2
1, 2
8
10
11, 12, 13
15
17, 18, 20, 21,
28, 29, 31, 32,
34, 35,37,38
19,30,36
23
24
25
26
27
IN
Ground
Cr ystal input, has inter nal load cap (36pF) and feedback
resistor from X2
Cr ystal output, nominally 14.318MHz. Has inter nal load
cap (36pF)
Supply for PCICLK_F and PCICLK (0:4), nominal 3.3V
Free running PCI clock not affected by PCI_STOP# for power
management.
Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile
Mode. Latched Input.
Frequency select pin. Latched Input. Internal Pull-down to GND
PCI clock output
Logic input to select 24 or 48MHz for pin 25 output
PCI clock output.
PCI clock outputs.
Input to Fanout Buffers for SDRAM outputs.
FS3
PCICLK0
SEL24_48#1, 2
PCICLK1
PCICLK(2:4)
BUFFER IN
IN
OUT
IN
OUT
OUT
IN
SDRAM (11:0)
OUT
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN
pin (controlled by chipset).
VDD3
SDATA
SCLK
PWR
IN
IN
Supply for SDRAM (0:12) nominal 3.3V.
Data input for I2C serial input, 5V tolerant input
Clock input of I2C input, 5V tolerant input
24_48MHz
OUT
24MHz/48MHz clock output
FS1
1, 2
48MHz
FS0
1, 2
IN
OUT
IN
Frequency select pin. Latched Input.
48MHz output clock
Frequency select pin. Latched Input
VDD4
PWR
Power for 24 & 48MHz output buffers and fixed PLL core.
40
SDRAM_OUT
OUT
Reference clock for SDRAM zero delay buffer
41
PD#1, 2
42
VDDCPU
PWR
43
CPUCLKT0
OUT
44
CPUCLKC0
OUT
46
CPUCLK
REF1
FS21, 2
OUT
OUT
IN
48
IN
Powers down chip, active low
Supply for CPU clock 3.3V
"True" clocks of differential pair CPU outputs. These open drain
outputs need an external 1.5V pull-up.
"Complementory" clocks of differential pair CPU outputs. These
open drain outputs need an external 1.5V pull-up.
3.3V CPU clock output powered by pin 42
14.318 MHz reference clock.
Frequency select pin. Latched Input
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
0442C—07/03/02
2
ICS94215
General Description
The ICS94215 is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all
clocks required for such a system.
The ICS94215 belongs to ICS new generation of programmable system clock generators. It employs serial
programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output
strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/
enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the
frequency to a safe setting if the system become unstable from over clocking.
Mode Pin - Power Management Input Control
MODE, Pin 7
(Latched Input)
0
1
Pin 2
CPU_STOP#
(Input)
REF0
(Output)
0442C—07/03/02
3
ICS94215
General I2C serial interface information for the ICS94215
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending Byte 0 through Byte 20
(see Note)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends Byte 0 through byte 8 (default)
ICS clock sends Byte 0 through byte X (if X(H) was
written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
How to Read:
How to Write:
Controller (Host)
Start Bit
Address D2(H)
Controlle r (Host)
Start Bit
Address D3 (H )
ICS (Slave/Receiver)
ICS (Sla ve /Re ce ive r)
A CK
Byte Count
ACK
Dummy Command Code
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
If 7H has been written to B8
ACK
Byte 0
Dummy Byte Count
Byte 1
Byte 0
Byte 2
Byte 1
Byte 3
Byte 2
Byte 4
Byte 3
Byte 5
Byte 4
Byte 6
Byte 5
Byte 6
ACK
Byte 7
Byte 18
ACK
If 12H has been written to B8
ACK
If 13H has been written to B8
ACK
If 14H has been written to B8
ACK
Stop Bit
Byte 19
ACK
Byte 20
ACK
Stop Bit
*See notes on the following page.
0442C—07/03/02
4
Byte18
Byte 19
Byte 20
ICS94215
Brief I2C registers description for ICS94215
Programmable System Frequency Generator
Register Name
Functionality &
Frequency Select
Register
Output Control
Registers
Byte
Description
0
1-6
Output frequency, hardware / I C
frequency select, spread spectrum &
output enable control register.
See individual
byte
description
Active / inactive output control
registers/latch inputs read back.
See individual
byte
description
See individual
byte
description
Vendor ID & Revision
ID Registers
7
Byte 11 bit[7:4] is ICS vendor id 1001. Other bits in this register
designate device revision ID of this
part.
Byte Count
Read Back Register
8
Writing to this register will configure
byte count and how many byte will
be read back. Do not write 00 H to
this byte.
08H
Watchdog Timer
Count Register
9
Writing to this register will configure
the number of seconds for the
watchdog timer to reset.
10H
10 Bit [6:0]
Watchdog enable, watchdog status
and programmable 'safe' frequency'
can be configured in this register.
000,0000
Watchdog Control
Registers
VCO Control Selection
Bit
10 Bit [7]
This bit select whether the output
frequency is control by
hardware/byte 0 configurations or
byte 11&12 programming.
VCO Frequency
Control Registers
11-12
These registers control the dividers
ratio into the phase detector and
thus control the VCO output
frequency.
Spread Spectrum
Control Registers
13-14
These registers control the spread
percentage amount.
Group Skews Control
Registers
15-16
Increment or decrement the group
skew amount as compared to the
initial skew.
Output Rise/Fall Time
Select Registers
17-20
These registers will control the
output rise and fall time.
Notes:
1.
2.
3.
4.
5.
6.
7.
PWD Default
2
0
Depended on
hardware/byte
0 configuration
Depended on
hardware/byte
0 configuration
See individual
byte
description
See individual
byte
description
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches
for verification. Readback will support standard SMBUS controller protocol. The number of bytes to
readback is defined by writing to byte 8.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte
14 is written but not 15, neither byte 14 or 15 will load into the receiver.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the
controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to
stop after any complete byte has been transferred. The Command code and Byte count shown above must
be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
0442C—07/03/02
5
ICS94215
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
PWD
Description
Bit7 Bit6 Bit5 Bit4 VCO/REF VCO CPUCLK PCICLK
Mz
MHz
MHz
FS3 FS2 FS1 FS0 Divider
0
0
0
0
0
440/35
180.00
90.00
30.00
0
0
0
0
1
491/37
190.01
95.00
31.67
0
0
0
1
0
395/28 201.99
101.00
33.67
0
0
0
1
1
513/36 204.03
102.00
34.00
0
0
1
0
0
451/32 201.80
100.90
33.57
0
0
1
0
1
446/31 206.00
103.00
34.33
0
0
1
1
0
484/33 210.00
105.00
35.00
0
0
1
1
1
447/32
200.01 100.00
33.33
0
1
0
0
0
284/19 214.02
107.00
35.67
0
1
0
0
1
472/31 218.01 109.00
36.33
0
1
0
1
0
507/33 219.98
110.00
36.67
0
1
0
1
1
496/32 221.93
111.00
37.00
0
1
1
0
0
363/23 225.98
113.00
37.67
0
1
1
0
1
514/32 229.99
115.00
38.33
Bit
0
1
1
1
0
474/29 234.03
117.00
39.00
(2,7:4)
0
1
1
1
1
391/21 266.59
133.30
33.33
1
0
0
0
0
352/21 240.00
120.00
40.00
1
0
0
0
1
454/26 250.02
125.00
31.25
1
0
0
1
0
345/19 259.99
130.00
32.50
1
0
0
1
1
467/25 267.46
133.73
33.43
1
0
1
0
0
396/21 270.00
135.00
33.75
1
0
1
0
1
421/22 274.00
137.00
34.25
1
0
1
1
0
466/24
278.01 139.00
34.75
1
0
1
1
1
376/27
199.39
100.00
33.33
1
1
0
0
0
352/18 280.00
140.00
35.00
1
1
0
0
1
519/26
285.81 143.00
35.75
1
1
0
1
0
486/24 289.94
145.00
36.25
1
1
0
1
1
496/24
295.91 148.00
37.00
1
1
1
0
0
440/21 300.00
150.00
37.50
1
1
1
0
1
433/20 309.99
155.00
38.75
1
1
1
1
0
419/18 333.30
166.66
41.67
1
1
1
1
1
427/23
265.82
133.33
33.33
0-Frequency is selected by hardware select, latched inputs
Bit 3 1- Frequency is selected by Bit 2,7:4
Bit 1 0- Normal
1- Spread spectrum enable ± 0.35% Center Spread
0
Running
Bit 0 1-- T
ristate all outputs
Bit2
Note 1
0
1
0
Note: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
0442C—07/03/02
6
ICS94215
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT
PIN#
PWD
Bit 7
-
X
FS2#
Bit 6
46
1
CPUCLK
DESCRIPTION
Bit 5
-
1
(Reserved)
Bit 4
-
X
FS3#
Bit 3
40
1
SDRAM_OUT
Bit 2
-
X
Bit 1
43,44
1
Bit 0
-
1
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT
(SEL24_48#)#
CPUCLK0 enable (both
differential pair. "True" and
Complimentary")
(Reserved)*
PIN#
PWD
DESCRIPTION
Bit 7
-
X
FS0#
Bit 6
7
1
PCICLK_F
Bit 5
-
1
(Reserved)
Bit 4
13
1
PCICLK4
Bit 3
12
1
PCICLK3
Bit 2
11
1
PCICLK2
Bit 1
10
1
PCICLK1
Bit 0
8
1
PCICLK0
Note:
* It is recommended to drive this bit to 0.
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
BIT
DESCRIPTION
PIN# PWD
DESCRIPTION
BIT
PIN#
PWD
Bit 7
-
1
(Reserved)
Bit 7
28
1
SDRAM 7
Bit 6
-
1
(Reserved)
Bit 6
29
1
SDRAM 6
Bit 5
26
1
48MHz
Bit 5
31
1
SDRAM 5
Bit 4
25
1
24_48MHz
Bit 4
32
1
SDRAM 4
Bit 3
17
1
SDRAM 11
Bit 3
34
1
SDRAM 3
Bit 2
18
1
SDRAM 10
Bit 2
35
1
SDRAM 2
Bit 1
20
1
SDRAM 9
Bit 1
37
1
SDRAM 1
Bit 0
21
1
SDRAM 8
Bit 0
38
1
SDRAM 0
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
PIN# PWD
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DESCRIPTION
Bit 7
-
1
(Reserved)
Bit 6
-
1
(Reserved)
Bit 5
-
1
(Reserved)
Bit 4
-
X
MODE#
Bit 3
-
X
FS1#
Bit 2
-
1
(Reserved)
Bit 1
48
1
REF1
Bit 0
2
1
REF0
PIN#
-
PWD
0
0
0
0
0
1
1
0
DESCRIPTION
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
R e s e r ve d ( N o t e )
Note: Don’t write into this register, writing into this
register can cause malfunction
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
0442C—07/03/02
7
ICS94215
Byte 7: Vendor ID and Revision ID Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
0
0
1
X
X
X
X
X
Byte 8: Byte Count and Read Back Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
Vendor ID
Vendor ID
Vendor ID
Revision ID
Revision ID
Revision ID
Revision ID
Revision ID
PWD
0
0
0
0
0
0
0
0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
The decimal representation of these
8 bits correspond to 290ms or 1ms
the watchdog timer will wait before
it goes to alarm mode and reset the
frequency to the safe setting. Default
at power up is 290ms.
PWD
X
X
X
X
X
X
X
X
PWD
0
0
0
1
0
0
0
0
Description
0=Hw/B0 freq / 1=B11 & 12 freq
WD Enable 0=disable / 1=enable
WD Status 0=normal / 1=alarm
WD Safe Frequency, Byte 0 bit 2
WD Safe Frequency, FS3
WD Safe Frequency, FS2
WD Safe Frequency, FS1
WD Safe Frequency, FS0
Note: FS values in bit [0:4] will correspond to Byte 0 FS
values. Default safe frequency is same as 00000
entry in byte0.
Byte 12: VCO Frequency Control Register
Byte 11: VCO Frequency Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 10: VCO Control Selection Bit
&
Watchdog Timer Control Register
Byte 9: Watchdog Timer Count Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
0
0
0
0
1
0
0
0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
VCO Divider Bit0
REF Divider Bit6
REF Divider Bit5
REF Divider Bit4
REF Divider Bit3
REF Divider Bit2
REF Divider Bit1
REF Divider Bit0
PWD
X
X
X
X
X
X
X
X
Description
VCO Divider Bit8
VCO Divider Bit7
VCO Divider Bit6
VCO Divider Bit5
VCO Divider Bit4
VCO Divider Bit3
VCO Divider Bit2
VCO Divider Bit1
Note: The decimal representation of these 9 bits (Byte
12 bit [7:0] & Byte 11 bit [7] ) + 8 is equal to the VCO
divider value. For example if VCO divider value of 36
is desired, user need to program 36 - 8 = 28, namely, 0,
00011100 into byte 12 bit & byte 11 bit 7.
Note: The decimal representation of these 7 bits (Byte 11
[6:0]) + 2 is equal to the REF divider value .
Notes:
1. PWD = Power on Default
0442C—07/03/02
8
ICS94215
Byte 13: Spread Sectrum Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
X
X
X
X
X
X
X
X
Byte 14:
Description
Spread Spectrum Bit7
Spread Spectrum Bit6
Spread Spectrum Bit5
Spread Spectrum Bit4
Spread Spectrum Bit3
Spread Spectrum Bit2
Spread Spectrum Bit1
Spread Spectrum Bit0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Spread Sectrum Control Register
PWD
X
X
X
X
X
X
X
X
Description
Reserved
Reserved
Reserved
Spread Spectrum Bit12
Spread Spectrum Bit11
Spread Spectrum Bit10
Spread Spectrum Bi 9
Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread
spectrum. Incorrect spread percentage may cause
system failure.
Byte 15: Output Skew Control
Byte 16: Output Skew Control
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
Description
0
0
PCI_F Skew Control
0
0
0
0
PCICLK [0:4] Skew Control
0
0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
1
1
X
0
1
0
1
0
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 18: Output Rise/Fall Time Select Register
Byte 17: Output Rise/Fall Time Select Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
X
X
X
X
X
X
X
X
Description
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPUCLKT0
CPUCLKC0
Reserved
CPUCLK
SDRAM_OUT: Slew Rate Control
SDRAM [0:11] Slew Rate Control
PWD
1
0
1
0
1
0
1
0
Description
PCI [0:4]: Slew Rate Control
PCI_F Slew Rate Control
48MHz: Slew Rate Control
24MHz: Slew Rate Control
Notes:
1. PWD = Power on Default
2. The power on default for byte 13-20 depends on the harware (latch inputs FS[0:4]) or I2C (Byte 0 bit [1:7]) setting.
Be sure to read back and re-write the values of these 8 registers when VCO frequency change is desired for the first
pass.
3. If Byte 8 bit 7 is driven to "1" meaning programming is intended, Byte 21-24 will lose their default power up value.
0442C—07/03/02
9
ICS94215
Byte 19: Reserved Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
X
X
X
X
X
X
X
X
Byte 20: Reserved Register
Description
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PWD
X
X
X
X
X
X
X
X
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note: Byte 19 and 20 are reserved registers, these
VCO Programming Constrains
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
Useful Formula
VCO Frequency = 14.31818 x VCO/REF divider value
Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5
are unused registers writing to these registers
will not affect device performance or
functinality.
To program the VCO frequency for over-clocking.
0. Before trying to program our clock manually, consider using ICS provided software utilities for easy
programming.
1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by
writing to byte 0, or using initial hardware power up frequency.
2. Write 0001, 1001 (19H) to byte 8 for readback of 21 bytes (byte 0-20).
3. Read back byte 11-20 and copy values in these registers.
4. Re-initialize the write sequence.
5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values.
6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew
rate.
7. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be
changed again, user only needs to write to byte 11 and 12 unless the system is to reboot.
Note:
1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group skew
relation programmed into bytes 13-16 could be unstable. Step 3 & 7 assure the correct spread and skew relationship.
2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly.
3. Follow min and max VCO frequency range provided. Internal PLL could be unstable if VCO frequency is too fast or
too slow. Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz).
4. ICS recommends users, to utilize the software utility provided by ICS Application Engineering to program the VCO
frequency.
5. Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spreadamount
desired. See Application note for software support.
0442C—07/03/02
10
ICS94215
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Volt age VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
Input High Voltage
VIH
2
VDD+0.3
Input Low Voltage
VIL
VSS-0.3
0.8
V
Input High Current
IIH
5
A
Input Low Current
IIL1
IIL2
Input Low Current
VIN = VDD
VIN =0 V; Inputs with no pull-
up resistors
VIN =0 V; Inputs with pull-up
resistors
-5
mA
-200
IDD3.3OP66
CL =0 pF; Select@ 66MHz
87
IDD3.3OP100
CL =0 pF; Select@ 100MHz
91
IDD3.3OP133
CL =0 pF; Select@ 133MHz
104
180
mA
Supply Current
Power Down
PD
Input frequency
Fi
VDD = 3.3 V
CIN
1
Input Capacitance
3.25
5
mA
14.32
16
MHz
Logic Inputs
5
pF
CIN
Logic Inputs
5
pF
CINX
X1 & X2 pins
45
pF
3
ms
4
ns
TSTAB
12
27
From VDD= 3.3 V to 1% target
Freq.
tCPU-PCI
VT = 50% to 1.5V
1 Guaranteed by design, not 100% tested in production.
0442C—07/03/02
11
1
2.85
ICS94215
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
VO = VX
Output Impedance
Z0
Output High Voltage
V OH2B
Termination to Vpull-up(external)
Output Low Voltage
VOL2B
Output Low Current
I OL2B
V OL = 0.3 V
1
tr2B
VOL = 0.3 V, VOH = 1.2 V
Rise Time
1
1
1
Jitter, Cycle-to-cycle
1
Jitter, Absolute
UNITS
1.2
0.4
0.9
V
V
mA
ns
0.9
ns
Vpu
+0.6
V
51
1100
55
mV
%
1
18
1
VDIF
Note 2
0.4
1
VDIF
Note 2
0.2
VX
dt2B
Note 3
VT = 50%
550
45
tsk2B
VT = 50%
163
200
ps
tjcyc-cyc2B
VT = VX
201
250
ps
tjabs2B
VT = 50%
250
ps
Differential voltage-DC
Differential Crossover
Skew
MAX
VOH = 1.2 V, VOL = 0.3 V
Differential voltage-AC
Duty Cycle
TYP
tf2B
Fall Time
1
MIN
-250
V
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true"
input level and VCP is the "complement" input level.
3 - Vpullup(external) = 1.5V, Min = Vpullup(external)/2-150mV; Max=(Vpullup(external)/2)+150mV
Electrical Characteristics - CPU (Push-Pull)
TA = 0 - 70°C; VDDL = 2.5 V +/-5%; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX
RDSP2B
V O = V DD*(0.5)
10
20
Output Impedance1
1
R
V
=
V
*(0.5)
10
20
Output Impedance
DSN2B
O
DD
Output High Voltage
V OH2B
IOH = -12.0 mA
2
Output Low Voltage
VOL2B
IOL = 12 mA
0.4
Output High Current
IOH2B
V OH = 1.7 V
-19
Output Low Current
IOL2B
V OL = 0.7 V
19
tr2B
VOL = 0.4 V, VOH = 2.0 V
0.4
1.2
1.6
Rise Time1
1
tf2B
VOH = 2.0 V, VOL = 0.4 V
0.4
1.1
1.6
Fall Time
Duty Cycle1
dt2B
V T = 1.25 V
0:1
tsk2B
0:2
tsk2B
tjcyc-cyc
Skew window
Skew window
1
Jitter, Cycle-to-cycle
46.9
55
%
V T = 1.25 V
43
175
ps
V T = 1.25 V
142
375
ps
V T = 1.25 V, CPU=66 MHz
177
250
ps
1
Guaranteed by design, not 100% tested in production.
0442C—07/03/02
12
45
UNITS
W
W
V
V
mA
mA
ns
ns
ICS94215
Electrical Characteristics - USB, REF(0:1)
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
Output High Voltage
V OH5
IOH = -12 mA
2.4
IOL = 9 mA
Output Low Voltage
V OL5
Output High Current
I OH5
VOH = 2.0 V
VOL = 0.8 V
16
Output Low Current
IOL5
1
tr5
VOL = 0.4 V, VOH = 2.4 V
Rise Time
1
tf5
VOH = 2.4 V, VOL = 0.4 V
Fall Time
dt5
VT = 1.5V
45
Duty Cycle1
Jitter, Cycle-totjcyc-cyc2B
VT = 1.5V
1
cycle
1Guaranteed by design, not 100% tested in production.
TYP
MAX
1.2
1.5
55.1
4
4
57
UNITS
V
V
mA
mA
ns
ns
%
1007
1100
ps
MAX
2.3
UNITS
V
V
mA
mA
ns
2.3
ns
0.4
-22
Electrical Characteristics - PCICLK_F, PCICLK(0:4)
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Output High Voltage
V OH5
IOH = -11 mA
2.6
IOL = 9.4 mA
Output Low Voltage
V OL5
Output High Current
IOH5
VOH = 2.0 V
Output Low Current
IOL5
VOL = 0.8 V
19
1
t
V
=
0.4
V,
VOH
=
2.4
V
1.8
Rise Time
r5
OL
1
Fall Time
1
Duty Cycle
1
Skew
Jitter, Cycle-tocycle1
1
tf5
VOH = 2.4 V, VOL = 0.4 V
2
45
0.4
-16
dt5
VT = 1.5V
51.7
55
%
tsk2B
VT = 1.5V
108
500
ps
tjcyc-cyc2B
VT = 1.5V
223
500
ps
Guaranteed by design, not 100% tested in production.
0442C—07/03/02
13
ICS94215
Electrical Characteristics - 24MHz,48MHz
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
IOH = -16 mA
Output High Voltage
VOH5
IOL = 9 mA
Output Low Voltage
V OL5
Output High Current
I OH5
VOH = 2.0 V
V OL = 0.8 V
Output Low Current
IOL5
1
tr5
VOL = 0.4 V, VOH = 2.4 V
Rise Time
1
tf5
VOH = 2.4 V, VOL = 0.4 V
Fall Time
dt5
VT = 1.5V
Duty Cycle1
1
tj1s5
VT = 1.5V
Jitter, One Sigma
VT = 1.5V
Jitter, Cycle to cycle
tjcyc_cyc2B
1Guaranteed by design, not 100% tested in production.
MIN
2.4
TYP
MAX
4
4
55
0.5
500
UNITS
V
V
mA
mA
ns
ns
%
ns
ps
otherwise specified)
MIN
TYP MAX
10
24
UNITS
W
0.4
-22
16
45
1.1
1.28
52
177
Electrical Characteristics - SDRAM
TA = 0 - 70°C; VDD = 3.3 V +/-5%;VDDL = 2.5 V +/-5%; CL = 20-30 pF (unless
PARAMETER
SYMBOL
CONDITIONS
Output Impedance
V O = V DD*(0.5)
RDSN3B1
IOH = -18 mA
Output High Voltage
VOH3
Output Low Voltage
V OL3
IOL = 9.4 mA
Output High Current
I OH3
V OH = 2.0 V
Output Low Current
I OL3
V OL = 0.8V
tr3
VOL = 0.4 V, VOH = 2.4 V
Rise Time1
tf3
VOH = 2.4 V, VOL = 0.4 V
Fall Time1
1
d
VT = 1.5 V
Duty Cycle
t3
1(0:11)
tsk3
VT = 1.5 V
Skew window
1( 0:12)
tsk3
VT = 1.5 V
Skew window
V
=
1.5
V,
CPU=66,100,133
T
tjcyc-cyc3
Jitter, Cycle-to-cycle1
MHz
1Guaranteed by design, not 100% tested in production.
0442C—07/03/02
14
2.4
0.8
0.8
48.5
192
290
1.6
1.6
55
250
500
V
V
mA
mA
ns
ns
%
ps
ps
173
250
ps
0.4
-46
45
ICS94215
Shared Pin Operation Input/Output Pins
both the solid CMOS programming voltage needed during
the power-up programming period and to provide an
insignificant load on the output clock during the subsequent
operating period.
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the
series termination resistor to minimize the current loop
area. It is more important to locate the series termination
resistor close to the driver than the programming resistor.
The I/O pins designated by (input/output) on the ICS94215
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and
stored into a 5-bit internal data latch. At the end of PowerOn reset, (see AC characteristics for timing values), the
device changes the mode of operations for these pins to
an output function. In this mode the pins produce the
specified buffered clocks to external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD
(logic 1) power supply or the GND (logic 0) voltage
potential. A 10 Kilohm (10K) resistor is used to provide
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0442C—07/03/02
15
ICS94215
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering
down the clock synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven
to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS.
The power down latency should be as short as possible but conforming to the sequence requirements shown below.
CPU_STOP# is considered to be a don't care during the power down operations. The REF and 48MHz clocks are
expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding
the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94215 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
0442C—07/03/02
16
ICS94215
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power
operation. CPU_STOP# is synchronized by the ICS94215. The minimum that the CPU clock is enabled (CPU_STOP#
high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks
will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse.
CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is
synchronized to the CPU clocks inside the ICS94215.
3. All other clocks continue to run undisturbed.
0442C—07/03/02
17
ICS94215
SY MBOL
c
N
L
E1
INDEX
AREA
E
In Millimeters
COMMON DIMENSIONS
MIN
MA X
A
2.413
2.794
.095
A1
0.203
0.406
.008
.016
b
0.203
0.343
.008
.0135
c
0.127
0.254
SEE V A RIA TIONS
D
1 2
.110
.005
.010
SEE V A RIA TIONS
E
10.033
10.668
.395
.420
E1
7.391
7.595
.291
.299
e
α
h x 45°
D
In Inches
COMMON DIMENSIONS
MIN
MA X
0.635 BA SIC
h
0.381
L
0.508
1.016
SEE V A RIA TIONS
N
α
0.635
0°
0.025 BA SIC
.015
.025
.020
.040
SEE V A RIA TIONS
8°
0°
MIN
MA X
MIN
15.748
16.002
8°
A
V A RIA TIONS
A1
N
-Ce
48
SEATING
PLANE
b
D mm.
D (inc h)
.620
.630
J EDEC M O- 118
6/ 1/ 00
DOC# 10- 0034
REV B
.10 (.004) C
Ordering Information
ICS94215yF-T
Example:
ICS XXXX y F - T
Designation for tape and reel packaging
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
0442C—07/03/02
18
MA X