ICS950201 Integrated Circuit Systems, Inc. Programmable Timing Control Hub™ for P4™ Recommended Application: CK-408 clock for Intel® 845 chipset with P4 processor. Output Features: • 3 Differential CPU Clock Pairs @ 3.3V • 7 PCI (3.3V) @ 33.3MHz • 3 PCI_F (3.3V) @ 33.3MHz • 1 USB (3.3V) @ 48MHz • 1 DOT (3.3V) @ 48MHz • 1 REF (3.3V) @ 14.318MHz • 5 3V66 (3.3V) @ 66.6MHz • 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz Features: • Supports spread spectrum modulation, down spread 0 to -0.5%. • Efficient power management scheme through PD#, CPU_STOP# and PCI_STOP#. • Uses external 14.318MHz crystal • Stop clocks and functional control available through I2C interface. Key Specifications: • CPU Output Jitter <150ps • 3V66 Output Jitter <250ps • CPU Output Skew <100ps, programmable over 800 ps with groups CPU0,1 and CPU2. Block Diagram Pin Configuration 56-Pin SSOP & TSSOP * These inputs have 150K internal pull-up resistor to VDD. Frequency Table FS2 FS1 FS0 0460G—08/31/04 CPU (MHz) 3V66 (MHz) 66Buff[2:0] 3V66[4:2] (MHz) PCI_F PCI (MHz) 0 0 0 66.66 66.66 66.66 33.33 0 0 1 100.00 66.66 66.66 33.33 0 1 0 200.00 66.66 66.66 33.33 0 1 1 133.33 66.66 66.66 33.33 Mid 0 0 Tristate Tristate Tristate Tristate Mid 0 1 TCLK/2 TCLK/4 TCLK/4 TCLK/8 Mid 1 0 Reserved Reserved Reserved Reserved Mid 1 1 Reserved Reserved Reserved Reserved ICS950201 Integrated Circuit Systems, Inc. Pin Description PIN NUMBER PIN NAME TYPE 1, 8, 14, 19, 26, 32, 37, 46, 50 DESCRIPTION VDD PWR 2 X1 X2 Cr ystal 14.318MHz Cr ystal input Input 3 X2 X1 Cr ystal 14.318MHz Cr ystal output Output 7, 6, 5 PCICLK_F (2:0) OUT Free running PCI clock not affected by PCI_STOP# for power management. 4, 9, 15, 20, 27, 31, 36, 41, 47 GND PWR Ground pins for 3.3V supply 18, 17, 16, 13, 12,11, 10 PCICLK (6:0) OUT PCI clock outputs 24,23, 22, 21 3V66 (5:2) OUT 66MHz reference clocks, from internal VCO 24 3V66_5 OUT 66MHz reference clock, from internal VCO 25 PD# IN Invokes power-down mode. Active Low. 3.3V power supply 28 Vtt_PWRGD# IN This 3.3V LVTTL input is a level sensitive strobe used to determine when FS(2:0) and MULTISEL0 inputs are valid and are ready to be sampled (active low) 29 SDATA I/O Data pin for I2C circuitry 5V tolerant 30 SCLK IN Clock pin of I2C circuitry 5V tolerant 33 3V66_0 OUT 34 PCI_STOP# IN 35 3V66_1/VCH_CLK OUT 3.3V output selectable through I2C to be 66MHz from internal VCO or 48MHz (non-SSC) 38 48MHz_DOT OUT 48MHz output clock for DOT 39 48MHz_USB OUT 48MHz output clock for USB 40 FS2 IN , 42 I REF OUT 43 MULTSEL0 IN 3.3V LVTTL input for selecting the current multiplier for CPU outputs 66MHz reference clocks, from internal VCO Halts PCICLK clocks at logic 0 level, when input low except PCICLK_F which are free running Special 3.3V input for Mode selection, cannot be logic 1 This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 44, 48, 51 CPUCLKC (2:0) OUT "Complementor y" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. 45, 49, 52 CPUCLKT (2:0) OUT "True" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. 53 CPU_STOP# IN Halts CPUCLK clocks at logic 0 level, when input low 55, 54 FS (1:0) IN Frequency select pins 56 REF OUT 14.318MHz reference clock. Power Groups (Analog) (Digital) VDDA = Analog Core PLL1 VDDREF = REF, Xtal VDD48 = 48MHz, PLL VDDPCI VDD3V66 VDDCPU 0460G—08/31/04 2 ICS950201 Integrated Circuit Systems, Inc. Truth Table CPU (MHz) 3V66 (5:0) (MHz) PCI_F PCI (MHz) REF0 (MHz) USB/DOT (MHz) 0 66.66 66.66 33.33 14.318 48.00 1 100.00 66.66 33.33 14.318 48.00 0 200.00 66.66 33.33 14.318 48.00 FS2 FS1 FS0 0 0 0 0 0 1 0 1 1 133.33 66.66 33.33 14.318 48.00 Mid 0 0 Tristate Tristate Tristate Tristate Tristate TCLK/2 TCLK/4 Mid 0 1 TCLK/8 TCLK TCLK/2 Mid 1 0 Reserved Reserved Reserved Reserved Reserved Mid 1 1 Reserved Reserved Reserved Reserved Reserved Maximum Allowed Current Condition Max 3.3V supply consumption Max discrete cap loads, Vdd = 3.465V All static inputs = Vdd or GND Powerdown Mode (PWRDWN# = 0) 40mA Full Active 360mA Host Swing Select Functions MULTISEL0 Board Target Trace/Term Z Reference R, Iref = VDD/(3*Rr) Output Current Voh @ Z 1 50 ohms Rr = 475 1%, Iref = 2.32mA Ioh = 6* I REF 0.7V @ 50 0460G—08/31/04 3 ICS950201 Integrated Circuit Systems, Inc. Byte 0: Control Register Bit Pin# Name PWD2 Type1 Bit 0 54 FS0 X R Bit 1 55 FS1 X R Bit 2 40 FS2 X R X R 1 RW Bit 3 34 PCI_STOP# 3 Bit 4 53 CPU_STOP# X R Bi t 5 35 3V66_1/VCH 0 RW Bit 6 - Bit 7 - Description Reflects the value of FS0 pin sampled on power up Reflects the value of FS1 pin sampled on power up Reflects the value of FS2 pin sampled on power up Hardware mode: Reflects the value of PCI_STOP# pin sampled on PWD Software mode: 0=PCICLK stopped 1=PCICLK not stopped Reflects the current value of the external CPU_STOP# pin VCH Select 66MHz/48MHz 0=66MHz, 1=48MHz (Reser ved) 0 Spread Enabled 0 RW 0=Spread Off, 1=Spread On Byte 1: Control Register PWD2 Type1 1 RW 0=Disabled 1=Enabled 4 1 RW 0=Disabled 1=Enabled 4 45, 44 Name CPUCLKT0 CPUCLKC0 CPUCLKT1 CPUCLKC1 CPUCLKT2 CPUCLKC2 1 RW 0=Disabled 1=Enabled 4 Bit 3 52, 51 CPUCLKT0 CPUCLKC0 0 RW Bit 4 49, 48 CPUCLKT1 CPUCLKC1 0 RW Bit 5 45, 44 CPUCLKT2 CPUCLKC2 0 RW Bit 6 Bit 7 43 MULTSEL0 0 X R Bit Pin# Bit 0 52, 51 Bit 1 49, 48 Bit 2 Description Allow control of CPUCLKT0/C0 with asser tion of CPU_STOP# 0=Not free running 1=Free running Allow control of CPUCLKT1/C1 with asser tion of CPU_STOP# 0=Not free running 1=Free running Allow control of CPUCLKT2/C2 with asser tion of CPU_STOP# 0=Not free running 1=Free running (Reserved) Reflects the current value of MULTSEL0 Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default 3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP functionality via I2C Byte 0 Bit 3. In Hardware mode it is not allowed to write to the I2C Byte 0 Bit3. In Software mode it is not allowed to pull the external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix these modes. In Hardware mode the I2C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in PCI_STOP mode. Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I2C Byte 0 Bit 3 = 0)]. 4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC off, and external resistor termination will bring CPUCLKC low. 0460G—08/31/04 4 ICS950201 Integrated Circuit Systems, Inc. Byte 2: Control Register Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Pin# 10 11 12 13 16 17 18 - Name PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 - PWD 1 1 1 1 1 1 1 0 Type RW RW RW RW RW RW RW - Description 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled (Reserved) Description 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled Allow control of PCICLK_F0 with asser tion of PCI_STOP#. 0=Free Running, 1=Not free running Allow control of PCICLK_F1 with asser tion of PCI_STOP#. 0=Free Running, 1=Not free running Allow control of PCICLK_F2 with asser tion of PCI_STOP#. 0=Free Running, 1=Not free running 0=Disabled 1=Enabled 0=Disabled 1=Enabled Byte 3: Control Register Bit Bit 0 Bit 1 Bit 2 Pin# 5 6 7 Name PCICLK_F0 PCICLK_F1 PCICLK_F2 PWD 1 1 1 Type RW RW RW Bit 3 5 PCICLK_F0 0 RW Bit 4 6 PCICLK_F1 0 RW Bit 5 7 PCICLK_F2 0 RW Bit 6 Bit 7 39 38 48MHz_USB 48MHz_DOT 1 1 RW RW Byte 4: Control Register Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Pin# 21 22 23 24 35 33 - Name 3V66-2 3V66-3 3V66-4 3V66_5 3V66_1/VCH_CLK 3V66_0 - PWD 1 1 1 1 1 1 0 0 Type RW RW RW RW RW RW R R Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default 0460G—08/31/04 5 Description 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled (Reserved) (Reserved) ICS950201 Integrated Circuit Systems, Inc. Byte 5: Programming Edge Rate (1 = enable, 0 = disable) Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Pin# X X X X X X X X Name 48MHz_USB 48MHz_USB 48MHz_DOT 48MHz_DOT - PWD 0 0 0 0 0 0 0 0 Type RW RW RW RW - PWD 1 1 1 1 1 1 1 1 Type R R R R R R R R Description USB edge rate cntrol USB edge rate cntrol DOT edge rate control DOT edge rate control (Reserved) (Reserved) (Reserved) (Reserved) Byte 6: Vendor ID Register (1 = enable, 0 = disable) Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Pin# X X X X X X X X Name Vendor ID Bit0 Vendor ID Bit1 Vendor ID Bit2 Vendor ID Bit3 Revision ID Bit0 Revision ID Bit1 Revision ID Bit2 Revision ID Bit3 Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default 0460G—08/31/04 6 Description (Reserved) (Reserved) (Reserved) (Reserved) Revision ID values will be based on individual device's revision ICS950201 Integrated Circuit Systems, Inc. Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage V DD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL CONDITIONS MIN VIH 2 VIL VSS - 0.3 IIH VIN = VDD -5 IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 Input Low Current Powerdown Current Input Frequency Pin Inductance Input Capacitance1 1 Transition time Settling time1 Clk Stabilization1 1 Delay UNITS MAX V VDD + 0.3 V 0.8 5 µA µA VIN = 0 V; Inputs with pull-up resistors IIL2 Operating Supply Current TYP -200 IDD3.3OP CL = Full load; Select @ 100 MHz IDD3.3OP CL =Full load; Select @ 133 MHz IDD3.3OP CL = Full load; Select @ 200 MHz IDD3.3PD Fi Lpin CIN C OUT CINX Ttrans Ts IREF=2.32 mA VDD = 3.3 V 229 240 360 220 236 360 234 245 360 25 14.32 Logic Inputs Output pin capacitance X1 & X2 pins To 1st crossing of target frequency From 1st crossing to 1% target frequency From VDD = 3.3 V to 1% target frequency TSTAB tPZH,tPZL Output enable delay (all outputs) tPHZ,tPLZ Output disable delay (all outputs) 1 Guaranteed by design, not 100% tested in production. 0460G—08/31/04 7 27 1 1 7 5 6 45 3 3 3 10 10 mA mA mA mA MHz nH pF pF pF ms ms ms ns ns ICS950201 Integrated Circuit Systems, Inc. Electrical Characteristics - CPU 0.7V Current Mode Differential Pair TA = 0 - 70°C; V DD = 3.3 V +/-5%; CL =2pF 1 PARAMETER SYMBOL CONDITIONS MIN Current Source Output Impedance Zo1 VO = Vx 3000 Voltage High VHigh Statistical measurement on single ended signal using oscilloscope math function. 660 Voltage Low VLow Max Voltage Min Voltage Crossing Voltage (abs) Vovs Vuds Vcross(abs) Crossing Voltage (var) d-Vcross Long Accuracy ppm Average period Tperiod Absolute min period Tabsmin Rise Time Fall Time Rise Time Variation Fall Time Variation tr tf d-tr d-tf Duty Cycle dt3 Skew tsk3 Jitter, Cycle to cycle tjcyc-cyc Measurement on single ended signal using absolute value. Variation of crossing over all edges see Tperiod min-max values 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 200MHz nominal 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread VOL = 0.175V, V OH = 0.525V V OH = 0.525V VOL = 0.175V Measurement from differential wavefrom VT = 50% Measurement from differential wavefrom TYP 770 MAX UNITS NOTES Ω 1 850 1 mV -150 5 150 756 -7 350 1150 -300 250 550 mV 1 1 1 12 140 mV 1 300 5.0015 5.0266 6.0018 6.0320 7.5023 5.4000 10.0030 10.0533 1,2 2 2 2 2 2 2 2 2 1,2 1,2 1,2 1,2 1 1 1 1 -300 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 4.8735 5.8732 7.3728 9.8720 175 175 45 1 mV 332 344 30 30 700 700 125 125 ppm ns ns ns ns ns ns ns ns ns ns ns ns ps ps ps ps 49 55 % 1 8 100 ps 1 60 150 ps 1 Guaranteed by design, not 100% tested in production. 2 All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at 14.31818MHz 0460G—08/31/04 8 ICS950201 Integrated Circuit Systems, Inc. Electrical Characteristics - PCICLK TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Frequency SYMBOL FO1 Output Impedance RDSP11 1 Output High Voltage VOH Output Low Voltage Output High Current VOL1 Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter,cycle to cyc 1 IOH IOL1 tr11 tf11 d t11 tsk11 tjcyc-cyc1 CONDITIONS MIN TYP 33.33 MAX UNITS MHz VO = VDD*(0.5) 12 33 55 Ω IOH = -1 mA 2.4 IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V 0.5 VOH = 2.4 V, VOL = 0.4 V 0.5 VT = 1.5 V 45 V -33 0.55 -33 V mA 30 38 mA 1.29 2 ns 1.45 2 ns 51 55 % VT = 1.5 V 190 500 ps VT = 1.5 V 124 250 ps 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - 3V66 TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL Output Frequency FO1 Output Impedance Duty Cycle RDSP11 VOH1 VOL1 IOH1 IOL1 tr11 tf11 d t11 Skew tsk11 Jitter tjcyc-cyc1 Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time CONDITIONS MIN TYP MAX UNITS 66.67 VO = VDD*(0.5) 12 IOH = -1 mA 2.4 33 MHz 55 Ω V IOL = 1 mA 0.55 V -33 38 mA mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V -33 30 VOL = 0.4 V, VOH = 2.4 V 0.5 1.28 2 ns VOH = 2.4 V, VOL = 0.4 V 0.5 1.36 2 ns VT = 1.5 V 45 53.1 55 % VT = 1.5 V 90 250 ps VT = 1.5 V 3V66 128 250 ps 1 Guaranteed by design, not 100% tested in production. 0460G—08/31/04 9 ICS950201 Integrated Circuit Systems, Inc. Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Frequency SYMBOL FO1 Output Impedance RDSP11 Output High Voltage V OH1 Output Low Voltage Output High Current Output Low Current 48DOT Rise Time V OL1 IOH1 IOL1 tr11 tf11 tr11 tf11 dt11 IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, V OL @MAX = 0.4 V -29 29 VOL = 0.4 V, V OH = 2.4 V 0.5 VOH = 2.4 V, VOL = 0.4 V 48DOT Fall Time VCH 48 USB Rise Time VCH 48 USB Fall Time Duty Cycle Jitter tjcyc-cyc 1 CONDITIONS MIN TYP MAX UNITS 48.008 MHz VO = V DD*(0.5) 20 60 IOH = -1 mA 2.4 Ω V 0.4 -23 27 V mA mA 677 1 ns 0.5 952 1 ns VOL = 0.4 V, V OH = 2.4 V 1 1.11 2 ns VOH = 2.4 V, VOL = 0.4 V 1 1.28 2 ns 45 53 55 % 194 350 ps VT = 1.5 V VT = 1.5 V 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - REF TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Frequency SYMBOL FO1 Output Impedance RDSP11 Output High Voltage VOH1 Output Low Voltage Output High Current Duty Cycle VOL1 IOH1 IOL1 tr11 tf11 d t11 Jitter tjcyc-cyc1 Output Low Current Rise Time Fall Time CONDITIONS MIN TYP 14.318 MAX UNITS MHz VO = VDD*(0.5) 20 48 60 Ω IOH = -1 mA 2.4 IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -29 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 29 V 0.4 -23 V mA 27 mA VOL = 0.4 V, VOH = 2.4 V 1 1.25 2 ns VOH = 2.4 V, VOL = 0.4 V 1 1.21 2 ns 45 52.2 55 % 675 1000 ps VT = 1.5 V VT = 1.5 V 1 Guaranteed by design, not 100% tested in production. 0460G—08/31/04 10 ICS950201 Integrated Circuit Systems, Inc. General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: • • • • • • • • • • • • • • • • Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 • ICS clock will acknowledge each byte one at a time. • Controller (host) sends a Stop bit Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2 (H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ICS (Slave/Receiver) ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Byte 6 Byte 6 Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 0460G—08/31/04 11 ICS950201 Integrated Circuit Systems, Inc. Un-Buffered Mode 3V66 & PCI Phase Relationship All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci. 3V66 (1:0) 3V66 (4:2) 3V66_5 Tpci PCICLK_F (2:0) PCICLK (6:0) Group Skews at Common Transition Edges: (Un-Buffered Mode) GROUP 3V66 PCI 3V66 to PCI SYMBOL CONDITIONS 3V66 3V66 pin to pin skew PCI PCI_F and PCI pin to pin skew S3V66-PCI 3V66 leads 33MHz PCI MIN 0 0 1.5 TYP MAX UNITS 500 ps 500 ps 3.5 ns 1 Guaranteed by design, not 100% tested in production. PD# Functionality CPU_STOP# CPUT CPUC 3V66 66MHz_OUT PCICLK_F PCICLK PCICLK USB/DOT 48MHz 1 Normal Normal 66MHz 66MHz_IN 66MHz_IN 66MHz_IN 48MHz 0 iref * Mult Float Low Low Low Low Low 0460G—08/31/04 12 ICS950201 Integrated Circuit Systems, Inc. PCI_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge. Assertion of PCI_STOP# Waveforms PCI_STOP# PCI_F[2:0] 33MHz PCI[6:0] 33MHz tsu CPU_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven. Assertion of CPU_STOP# Waveforms CPU_STOP# CPUT CPUC CPU_STOP# Functionality CPU_STOP# CPUT CPUC 1 Normal Normal 0 iref * Mult Float 0460G—08/31/04 13 ICS950201 Integrated Circuit Systems, Inc. c N SYMBOL L E1 INDEX AREA A A1 b c D E E1 e h L N α E 1 2 a h x 45° D In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0° 8° In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0° 8° A A1 N -Ce SEATING PLANE b .10 (.004) C 56 VARIATIONS D mm. MIN MAX 18.31 18.55 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 300 mil SSOP Package Ordering Information ICS950201yFLF-T Example: ICS XXXX y F LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0460G—08/31/04 14 D (inch) MIN .720 MAX .730 ICS950201 Integrated Circuit Systems, Inc. c N In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS α 0° 8° 0° 8° aaa -0.10 -.004 L E1 INDEX AREA E 1 2 a D A A2 A1 -Ce VARIATIONS SEATING PLANE b N 56 aaa C D mm. MIN 13.90 D (inch) MAX 14.10 Reference Doc.: JEDEC Publication 95, MO-153 10-0039 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) Ordering Information ICS950201yGLF-T Example: ICS XXXX y G LF- T Designation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 0460G—08/31/04 15 MIN .547 MAX .555 ICS950201 Integrated Circuit Systems, Inc. Revision History Rev. G Issue Date Description 8/31/2004 Updated Lead Free information Page # 14-15 0460G—08/31/04 16