ICS ICSSSTVA16857

ICSSSTVA16857
Integrated
Circuit
Systems, Inc.
DDR 14-Bit Registered Buffer
Recommended Applications:
•
DDR Memory Modules
•
Provides complete DDR DIMM logic solution with
ICS93V857 or ICS95V857
•
SSTL_2 compatible data registers
•
DDR400 recommended (backward compatible to
DDR200/266/333)
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
Product Features:
•
Exceeds "SSTVN16857" performance
•
Differential clock signal
•
Meets SSTL_2 signal data
•
Supports SSTL_2 class I & II specifications
•
Low-voltage operation
- VDD = 2.3V to 2.7V
•
48 pin TSSOP package
Truth Table1
Inputs
RESET#
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICSSSTVA16857
Pin Configuration
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK#
CLK
VDD
GND
VREF
RESET#
D8
D9
D10
D11
D12
VDD
GND
D13
D14
Q Outputs
CLK#
D
48-Pin TSSOP
Q
6.10 mm. Body, 0.50 mm. pitch = TSSOP
L
X or
Floating
X or
Floating
X or
Floating
L
H
↑
↓
H
H
H
↑
↓
L
L
H
L or H
L or H
X
Q0(2)
Notes:
1.
2.
H = High Signal Level
L = Low Signal Level
↑ = Transition LOW-to-HIGH
↓ = Transition HIGH -to LOW
X = Irrelevant
Output level before the indicated
steady state input conditions were
established.
Block Diagram
CLK
CLK#
RESET#
D1
VREF
38
39
34
48
35
R
CLK
D1
To 13 Other Channels
0932A—05/12/04
1
Q1
ICSSSTVA16857
General Description
The 14-bit ICSSSTVA16857 is a universal bus driver designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O levels,
except for the LVCMOS RESET# input.
Data flow from D to Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive edge
of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#, an
LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTVA16857 supports low-power
standby operation. A logic level “Low” at RESET# assures that all internal registers and outputs (Q) are reset to the logic
“Low” state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that RESET# must always
be supported with LVCMOS levels at a valid logic state because VREF may not be stable during power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held at a logic
“Low” level during power up.
In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#.
Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state,
the register will be cleared and the outputs will be driven to a logic “Low” level quickly relative to the time to disable the
differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power
standby state, the register will become active quickly relative to the time to enable the differential input receivers. When
the data inputs are at a logic level “Low” and the clock is stable during the “Low”-to-”High” transition of RESET# until the
input receivers are fully enabled, the design ensures that the outputs will remain at a logic “Low” level.
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
24, 23, 20, 19, 18,
15, 14, 11, 10, 7,
6, 5, 2, 1
DESCRIPTION
Q (14:1)
OUTPUT
3, 8, 13, 22,
27, 36, 46
GND
PWR
Ground
Output supply voltage
Data output
4, 9, 12, 16, 21
VDDQ
PWR
25, 26, 29, 30, 31,
32, 33, 40, 41, 42,
43, 44, 47, 48
D (14:1)
INPUT
Data input
38
CLK
INPUT
Positive clock input
39
CLK#
INPUT
Negative clock input
28, 37, 45
VDD
PWR
34
RESET#
INPUT
Reset (active low)
Core supply voltage
35
VREF
INPUT
Input reference voltage
0932A—05/12/04
2
ICSSSTVA16857
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . .
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . .
Input Voltage 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage 1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Clamp Current . . . . . . . . . . . . . . . . . . . .
Output Clamp Current . . . . . . . . . . . . . . . . . . .
Continuous Output Current . . . . . . . . . . . . . . .
VDD, VDDQ or GND Current/Pin . . . . . . . . . . . .
–65°C to +150°C
-0.5 to 3.6V
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
±50 mA
±50 mA
±50 mA
±100 mA
Notes:
1. The input and output negative voltage
ratings may be excluded if the input
and output clamp ratings are observed.
2. This current will flow only when the
output is in the high state level
V0 >VDDQ.
3. The package thermal impedance is
calculated in accordance with
JESD 51.
Package Thermal Impedance 3 . . . . . . . . . . . . . . . . 55°C/W
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Recommended Operating Conditions - DDRI/DDR333 (PC1600, PC2100, PC2700)
PARAMETER
V DD
V DDQ
VREF
VTT
VI
VIH (DC)
VIH (AC)
VIL (DC)
VIL (DC)
VIH
VIL
VICR
VID
VIX
IOH
IOL
TA
DESCRIPTION
Supply Voltage
I/O Supply Voltage
Reference Voltage
Termination Voltage
Input Voltage
DC Input High Voltage
AC Input High Voltage
Data Inputs
DC Input Low Voltage
AC Input Low Voltage
Input High Voltage Level
RESET#
Input Low Voltage Level
Common mode Input Range
CLK, CLK#
Differential Input Voltage
Cross Point Voltage of Differential Clock
Pair
High-Level Output Current
Low-Level Output Current
Operating Free-Air Temperature
1
Guaranteed by design, not 100% tested in production.
0932A—05/12/04
3
MIN
2.3
2.3
1.15
VREF - 0.04
0
VREF + 0.15
VREF + 0.31
TYP
2.5
2.5
1.25
V REF
MAX
2.7
2.7
1.35
V REF + 0.04
V DDQ
UNITS
VREF - 0.15
VREF - 0.31
V
1.7
0.97
0.36
0.7
1.53
(V DDQ/2) - 0.2
(VDDQ/2) + 0.2
0
-16
16
70
mA
°C
ICSSSTVA16857
Recommended Operating Conditions - DDRI-400 (PC3200)
PARAMETER
V DD
V DDQ
VREF
VTT
VI
VIH (DC)
VIH (AC)
VIL (DC)
VIL (DC)
VIH
VIL
VICR
VID
VIX
IOH
IOL
TA
DESCRIPTION
Supply Voltage
I/O Supply Voltage
Reference Voltage
Termination Voltage
Input Voltage
DC Input High Voltage
AC Input High Voltage
Data Inputs
DC Input Low Voltage
AC Input Low Voltage
Input High Voltage Level
RESET#
Input Low Voltage Level
Common mode Input Range
CLK, CLK#
Differential Input Voltage
Cross Point Voltage of Differential Clock
Pair
High-Level Output Current
Low-Level Output Current
Operating Free-Air Temperature
1
Guaranteed by design, not 100% tested in production.
0932A—05/12/04
4
MIN
2.5
2.5
1.25
VREF - 0.04
0
VREF + 0.15
VREF + 0.31
TYP
2.6
2.6
1.3
V REF
MAX
2.7
2.7
1.35
V REF + 0.04
V DDQ
UNITS
VREF - 0.15
VREF - 0.31
V
1.7
0.97
0.36
0.7
1.53
(V DDQ/2) - 0.2
(VDDQ/2) + 0.2
0
-16
16
70
mA
°C
ICSSSTVA16857
DC Electrical Characteristics - DDRI/DDR333 (PC1600, PC2100, PC2700)
TA = 0 - 70°C; VDD = 2.5 +/-0.2V, V DDQ=2.5 +/-0.2V; (unless otherwise stated)
SYMBOL
I DD
I DDD
rOH
rOL
rO(D)
Ci
MIN
TYP
2.3V
I OH = -100µA
2.3V-2.7V
I OH = -8mA
I OL = 100µA
I OL = 8mA
All Inputs
V I = VDD or GND
Standby (Static)
RESET# = GND
V I = VIH(AC) or V IL(AC),
Operating (Static)
RESET# = VDD
RESET# = VDD,
Dynamic operating
V I = VIH(AC) or V IL(AC),
(clock only)
CLK and CLK# switching
50% duty cycle.
IO = 0
RESET# = VDD,
V I = VIH(AC) or V IL (AC),
Dynamic Operating CLK and CLK# switching
(per each data input) 50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
I OH = -16mA
Output High
Output Low
I OL = 16mA
[rOH - rOL] each
I O = 20mA, TA = 25° C
separate bit
Data Inputs
V I = VREF ±350mV
V ICR = 1.25V, V I(PP) = 360mV
CLK and CLK#
2.3V
2.3V-2.7V
2.3V
2.7V
VOH
II
VDDQ
I I = -18mA
VIK
VOL
CONDITIONS
PARAMETERS
Notes:
1 - Guaranteed by design, not 100% tested in production.
0932A—05/12/04
5
MAX
UNITS
-1.2
V DDQ 0.2
1.95
V
0.2
0.35
±5
0.01
µA
µA
25
mA
30
µ/clock
MHz
10
µA/ clock
MHz/data
2.7V
2.3V-2.7V
2.3V-2.7V
7
7
2.5V
2.5V
2.5
2.5
13.5
13
20
20
Ω
Ω
4
Ω
3.5
3.5
pF
ICSSSTVA16857
DC Electrical Characteristics - DDRI-400 (PC3200)
TA = 0 - 70°C; VDD = 2.5 +/-0.2V, V DDQ=2.5 +/-0.2V; (unless otherwise stated)
SYMBOL
I DD
I DDD
rOH
rOL
rO(D)
Ci
MIN
TYP
2.5V
I OH = -100µA
2.5V-2.7V
I OH = -8mA
I OL = 100µA
I OL = 8mA
All Inputs
V I = VDD or GND
Standby (Static)
RESET# = GND
V I = VIH(AC) or V IL(AC),
Operating (Static)
RESET# = VDD
RESET# = VDD,
Dynamic operating
V I = VIH(AC) or V IL(AC),
(clock only)
CLK and CLK# switching
50% duty cycle.
IO = 0
RESET# = VDD,
V I = VIH(AC) or V IL (AC),
Dynamic Operating CLK and CLK# switching
(per each data input) 50% duty cycle. One data
input switching at half
clock frequency, 50%
duty cycle
I OH = -16mA
Output High
Output Low
I OL = 16mA
[rOH - rOL] each
I O = 20mA, TA = 25° C
separate bit
Data Inputs
V I = VREF ±350mV
V ICR = 1.25V, V I(PP) = 360mV
CLK and CLK#
2.7V
2.5V-2.7V
2.5V
2.7V
VOH
II
VDDQ
I I = -18mA
VIK
VOL
CONDITIONS
PARAMETERS
Notes:
1 - Guaranteed by design, not 100% tested in production.
0932A—05/12/04
6
MAX
UNITS
-1.2
V DDQ 0.2
1.95
V
0.2
0.35
±5
0.01
µA
µA
25
mA
30
µ/clock
MHz
10
µA/ clock
MHz/data
2.7V
2.5V-2.7V
2.5V-2.7V
7
7
2.6V
2.6V
2.5
2.5
13.5
13
20
20
Ω
Ω
4
Ω
3.5
3.5
pF
ICSSSTVA16857
Timing Requirements1
(over recommended operating free-air temperature range, unless otherwise noted)
VDDQ = 2.5V ± 0.2V
PARAMETERS
SYMBOL
MIN
MAX
Clock frequency
270
fclock
Output slew rate
1
4
tSL
0.4
Setup time, fast slew rate 2 & 4
Data before CLK↑ , CLK#↓
tS
0.6
Setup time, slow slew rate 3 & 4
2&4
0.4
Hold time, fast slew rate
Th
Data after CLK↑ , CLK#↓
0.5
Hold time, slow slew rate 3 & 4
1 - Guaranteed by design, not 100% tested in production.
Notes:
2 - For data signal input slew rate of ≥ 1V/ns.
3 - For data signal input slew rate of ≥ 0.5V/ns and < 1V/ns.
4 - CLK, CLK# signals input slew rate of ≥ 1V/ns.
UNITS
Switching Characteristics - DDRI/DDR333 (PC1600, PC2100, PC2700)
(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)
VDD = 2.5V ±0.2V
From
To
SYMBOL
UNITS
(Input)
(Output)
MIN
TYP
MAX
210
MHz
f max
CLK, CLK# (TSSOP)
Q
1.6
2.1
2.6
ns
t PD
RESET#
Q
3.5
ns
t phl
Switching Characteristics - DDRI-400 (PC3200)
(over recommended operating free-air temperature range, unless otherwise noted) (see Figure 1)
From
To
VDD = 2.6V ±0.1V
UNITS
SYMBOL
(Input)
(Output)
MIN
TYP
MAX
f max
210
MHz
CLK, CLK# (TSSOP)
Q
1.1
1.6
1.89
ns
t PD
RESET#
Q
3.5
ns
t phl
0932A—05/12/04
7
MHz
V/ns
ns
ns
ns
ns
ICSSSTVA16857
VTT
RL=50Ω
From Output
Under Test
Test Point
CL = 30 pF
(see Note 1)
Load Circuit
LVCMOS
RESET#
Input
VDDQ
VDDQ/2
VDDQ/2
tinact
VI(pp)
0V
Timing
Input
tact
IDD
(see note 2)
tPHL
90% IDDH
10%
VICR
VICR
IDDL
tPHL
VTT
Voltage and Current Waveforms
Inputs Active and Inactive Times
VTT
VOH
VOL
Output
Voltage Waveforms - Propagation Delay Times
tw
VIH
VREF
Input
VREF
VIL
Voltage Waveforms - Pulse Duration
LVCMOS
RESET#
Input
VI(pp)
Timing
Input
VDD/2
VIL
VICR
tPHL
tS
Input
VIH
VREF
VOH
Output
th
VTT
VOL
VIH
VREF
Voltage Waveforms - Propagation Delay Times
VIL
Voltage Waveforms - Setup and Hold Times
Figure 1 - Parameter Measurement Information (VDDQ = 2.5V ±0.2V)
Notes:
1. CL incluces probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDDQ or GND, and IO = 0 mA.
3. All input pulses are supplied by generators having the following characteristics: PRR @10 MHz,
Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VTT = VREF = VDDQ/2
6. VIH = VREF + 310mV (AC voltage levels) for differential inputs. VIH = VDDQ for LVCMOS input.
7. VIL = VREF - 310mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. tPLH and tPHL are the same as tpd
0932A—05/12/04
8
ICSSSTVA16857
c
N
L
E1
INDEX
AREA
E
1 2
D
A
A2
A1
-Ce
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-1.20
-.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
SEE VARIATIONS
SEE VARIATIONS
D
8.10 BASIC
0.319 BASIC
E
E1
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
e
L
0.45
0.75
.018
.030
SEE VARIATIONS
SEE VARIATIONS
N
0°
8°
0°
8°
α
aaa
-0.10
-.004
VARIATIONS
SEATING
PLANE
b
N
aaa C
48
D mm.
MIN
MAX
12.40
12.60
Reference Doc.: JEDEC Publicat ion 95, M O-153
6.10 mm. Body, 0.50 mm. pitch TSSOP
(0.020 mil)
(240 mil)
10-0039
Ordering Information
ICSSSTVA16857yGLF-T
Example:
ICS XXXX y G LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0932A—05/12/04
9
D (inch)
MIN
.488
MAX
.496