ICSI IC62LV2568L

IC62LV2568L
IC62LV2568LL
IC62LV2568L
IC62LV2568LL
256K x 8 LOW POWER and LOW V++
CMOS STATIC RAM
FEATURES
• Access times of 55, 70, 100 ns
• Low active power: 126 mW (max, L, LL)
• Low standby power: 36 µW (max, L) and 7.2
µW (max, LL) CMOS standby
• Low data retention voltage: 1.5V (min.)
• Available in Low Power (-L) and Ultra-Low
Power (-LL)
• Output Enable (OE) and two Chip Enable
• TTL compatible inputs and outputs
• Single 2.7V-3.6V power supply
• Available in the 32-pin 8x20mm TSOP-1, 32-pin
8x13.4mm TSOP-1 and 48-pin 6*8mm TF-BGA
DESCRIPTION
The 1+51 IC62LV2568L and IC62LV2568LL are low power
and low VCC, 262,144-bit words by 8 bits CMOS static RAMs.
They are fabricated using 1+51's high-performance CMOS
technology. This highly reliable process coupled with innovative circuit design techniques, yields higher performance and
low power consumption devices.
When CE1 is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs, CE1 and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IC62LV2568L and IC62LV2568LL are available in 32-pin
8*20mm TSOP-1, 8*13.4mm TSOP-1 and 48-pin 6*8mm TFBGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A17
DECODER
2048 x 128 x 8
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VCC
GND
I/O0-I/O7
CE1
CE2
OE
CONTROL
CIRCUIT
WE
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
LPSR001-0A 05/01/2001
1
IC62LV2568L
IC62LV2568LL
PIN CONFIGURATIONS
32-Pin 8*20mm TSOP-1, 8*13.4mm STSOP-1
A11
A9
A8
A13
WE
CE2
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48-Pin 6*8mm TF-BGA
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
1
2
3
4
5
6
A
A0
A1
CE2
A3
A6
A8
B
I/O4
A2
WE
A4
A7
I/O0
NC
A5
C
I/O5
D
GND
Vcc
E
Vcc
GND
F
I/O6
G
I/O7
H
A9
I/O1
NC
A17
OE
CE1
A16
A15
I/O3
A10
A11
A12
A13
A14
I/O2
PIN DESCRIPTIONS
A0-A17
Address Inputs
CE1
Chip Enable 1 Input
CE2
Chip Enable 2 Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Data Input/Output
NC
No Connection
Vcc
Power
GND
Ground
OPERATING RANGE
Range
Commercial
Industrial
2
Ambient Temperature
0°C to +70°C
VCC
2.7V - 3.6V
–40°C to +85°C
2.7V - 3.6V
Integrated Circuit Solution Inc.
LPSR001-0A 05/01/2001
IC62LV2568L
IC62LV2568LL
TRUTH TABLE
Mode
WE
CE1
CE2
OE
I/O Operation
Vcc Current
X
X
H
H
L
H
X
L
L
L
X
L
H
H
H
X
X
H
L
X
High-Z
High-Z
High-Z
DOUT
DIN
ISB, ISB
ISB, ISB
ICC
ICC
ICC
Not Selected
(Power-down)
Output Disabled
Read
Write
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
VCC
TBIAS
TSTG
PT
Parameter
Terminal Voltage with Respect to GND
Vcc related to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
Value
–0.5 to Vcc + 0.5
–0.3 to +4.0
–40 to +85
–65 to +150
0.7
Unit
V
V
°C
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
CAPACITANCE(1)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
VOL
VIH
VIL(1)
ILI
ILO
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
Output Leakage
VCC = Min., IOH = –1.0 mA
VCC = Min., IOL = 2.1 mA
2.2
—
2.2
–0.3
–1
–1
—
0.4
VCC + 0.3
0.4
1
1
V
V
V
V
µA
µA
GND ≤ VIN ≤ VCC
GND ≤ VOUT ≤ VCC
Notes:
1. VIL = –2.0V for pulse width less than 10 ns.
Integrated Circuit Solution Inc.
LPSR001-0A 05/01/2001
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IC62LV2568L
IC62LV2568LL
IC62LV2568L POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-55
Min. Max.
-70
Min. Max.
-100
Min. Max.
Symbol Parameter
Test Conditions
Unit
ICC
Vcc Dynamic Operating
Supply Current
VCC = Max.,
IOUT = 0 mA, f = fMAX
Com.
Ind.
—
—
40
45
—
—
30
35
—
—
20
25
mA
ISB
TTL Standby Current
(TTL Inputs)
VCC = Max.,
Com.
VIN = VIH or VIL,
Ind.
CE1 ≥ VIH or CE2 ≤ VIL, f = 0
—
—
0.4
1.0
—
—
0.4
1.0
—
—
0.4
1.0
mA
ISB
CMOS Standby
Current (CMOS Inputs)
VCC = Max., f = 0
Com.
Ind.
CE1 ≥ VCC – 0.2V,
CE2 ≤ 0.2V,
or VIN ≥ VCC – 0.2V, VIN ≤ 0.2V
—
—
35
50
—
—
35
50
—
—
35
50
µA
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IC62LV2568LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-55
Min. Max.
-70
Min. Max.
-100
Min. Max.
Symbol Parameter
Test Conditions
Unit
ICC
Vcc Dynamic Operating
Supply Current
VCC = Max.,
IOUT = 0 mA, f = fMAX
Com.
Ind.
—
—
40
45
—
—
30
35
—
—
20
25
mA
ISB
TTL Standby Current
(TTL Inputs)
VCC = Max.,
Com.
VIN = VIH or VIL,
Ind.
CE1 ≥ VIH or CE2 ≤ VIL, f = 0
—
—
0.4
1.0
—
—
0.4
1.0
—
—
0.4
1.0
mA
ISB
CMOS Standby
Current (CMOS Inputs)
VCC = Max., f = 0
Com.
CE ≥ VCC – 0.2V,
Ind.
CE2 ≤ 0.2V,
or VIN ≥ VCC – 0.2V, VIN ≤ 0.2V
—
—
10
15
—
—
10
15
—
—
10
15
µA
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
4
Integrated Circuit Solution Inc.
LPSR001-0A 05/01/2001
IC62LV2568L
IC62LV2568LL
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
Parameter
Min.
-55
Max.
Min.
-70
Max.
-100
Min. Max.
Unit
tRC
Read Cycle Time
55
—
70
—
100
—
ns
tAA
Address Access Time
—
55
—
70
—
100
ns
tOHA
Output Hold Time
10
—
10
—
15
—
ns
tACE1
CE1 Access Time
—
55
—
70
—
100
ns
tACE2
CE2 Access Time
—
55
—
70
—
100
ns
tDOE
OE Access Time
—
30
—
35
—
50
ns
5
—
5
—
5
—
ns
tLZOE(2) OE to Low-Z Output
tHZOE
OE to High-Z Output
—
20
0
25
0
30
ns
tLZCE1(2) CE1 to Low-Z Output
10
—
10
—
10
—
ns
tLZCE2(2) CE2 to Low-Z Output
10
—
10
—
10
—
ns
tHZCE
0
20
0
25
0
30
ns
(2)
(2)
CE1 or CE2 to Low-Z Output
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels
of 0.4V to 2.2V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0.4V to 2.2V
5 ns
1.5V
See Figures 1 and 2
AC TEST LOADS
1 TTL
OUTPUT
OUTPUT
100 pF
Including
jig and
scope
Figure 1
Integrated Circuit Solution Inc.
LPSR001-0A 05/01/2001
1 TTL
5 pF
Including
jig and
scope
Figure 2
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IC62LV2568L
IC62LV2568LL
AC TEST LOADS
READ CYCLE NO.1(1,2)
tRC
ADDRESS
tAA
tOHA
tOHA
DOUT
DATA VALID
AC WAVEFORMS
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA
tOHA
OE
tHZOE
tDOE
CE1
tLZOE
tACE1/tACE2
CE2
DOUT
tLZCE1/
tLZCE2
HIGH-Z
tHZCE
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIL.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
6
Integrated Circuit Solution Inc.
LPSR001-0A 05/01/2001
IC62LV2568L
IC62LV2568LL
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range, Standard and Low Power)
Symbol
Parameter
Min.
-55
Max.
Min.
-70
Max.
-100
Min. Max
Unit
tWC
Write Cycle Time
55
—
70
—
100
—
ns
tSCE1
CE1 to Write End
45
—
65
—
80
—
ns
tSCE2
CE2 to Write End
45
—
65
—
80
—
ns
tAW
Address Setup Time to Write End
45
—
65
—
80
—
ns
tHA
Address Hold from Write End
0
—
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
0
—
ns
tPWE(4)
WE Pulse Width
50
—
55
—
70
—
ns
tSD
Data Setup to Write End
25
—
30
—
40
—
ns
tHD
Data Hold from Write End
0
—
0
—
0
—
ns
(3)
WE LOW to High-Z Output
—
25
—
25
—
30
ns
(3)
WE HIGH to Low-Z Output
5
—
5
—
5
—
ns
tHZWE
tLZWE
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to
2.2V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
tWC
ADDRESS
tHA
tSCE1
CE1
tSCE2
CE2
tAW
tPWE(4)
WE
tSA
DOUT
DATA UNDEFINED
tHZWE
tLZWE
HIGH-Z
tSD
DIN
Integrated Circuit Solution Inc.
LPSR001-0A 05/01/2001
tHD
DATA-IN VALID
7
IC62LV2568L
IC62LV2568LL
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)
tWC
ADDRESS
tSA
tHA
tSCE1
CE1
tSCE2
CE2
tAW
tPWE(4)
WE
tHZWE
DOUT
DATA UNDEFINED
tLZWE
HIGH-Z
tSD
DIN
tHD
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the Write.
2. I/O will assume the HIGH-z state if OE =VIH.
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Integrated Circuit Solution Inc.
LPSR001-0A 05/01/2001
IC62LV2568L
IC62LV2568LL
DATA RETENTION SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Condition
VDR
Vcc for Data Retention
See Data Retention Waveform
IDR
Data Retention Current
Vcc = 2.0V, CE1 ≥ Vcc – 0.2V
tSDR
Data Retention Setup Time
See Data Retention Waveform
0
—
ns
tRDR
Recovery Time
See Data Retention Waveform
tRC
—
ns
DATA RETENTION WAVEFORM
Com. (-L)
Com. (-LL)
Ind. (-L)
Ind. (-LL)
Min.
Max.
Unit
1.5
3.6
V
—
—
—
—
20
5
25
7
µA
µA
µA
µA
(CE1 Controlled)
Data Retention Mode
tSDR
tRDR
VCC
2.7V
2.2V
VDR
CE1 ≥ VCC - 0.2V
CE
GND
DATA RETENTION WAVEFORM
(CE2 Controlled)
Data Retention Mode
VCC
2.7V
t RDR
t SDR
CE2
2.2V
VDR
0.4V
CE2 ≤ 0.2V
GND
Integrated Circuit Solution Inc.
LPSR001-0A 05/01/2001
9
IC62LV2568L
IC62LV2568LL
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Industrial Range: -40°C to +85°C
Speed (ns) Order Part No.
Speed (ns) Order Part No.
Package
Package
55
IC62LV2568L-55T
IC62LV2568L-55H
IC62LV2568L-55B
8*20mm TSOP-1
8*13.4mm TSOP-1
6*8mm TF-BGA
55
IC62LV2568L-55TI
IC62LV2568L-55HI
IC62LV2568L-55BI
8*20mm TSOP-1
8*13.4mm TSOP-1
6*8mm TF-BGA
70
IC62LV2568L-70T
IC62LV2568L-70H
IC62LV2568L-70B
8*20mm TSOP-1
8*13.4mm TSOP-1
6*8mm TF-BGA
70
IC62LV2568L-70TI
IC62LV2568L-70HI
IC62LV2568L-70BI
8*20mm TSOP-1
8*13.4mm TSOP-1
6*8mm TF-BGA
100
IC62LV2568L-100T
IC62LV2568L-100H
IC62LV2568L-100B
8*20mm TSOP-1
8*13.4mm TSOP-1
6*8mm TF-BGA
100
IC62LV2568L-100TI
IC62LV2568L-100HI
IC62LV2568L-100BI
8*20mm TSOP-1
8*13.4mm TSOP-1
6*8mm TF-BGA
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
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Integrated Circuit Solution Inc.
LPSR001-0A 05/01/2001