ISSI ISSI® IS61LV256 IS61LV256 32K x 8 LOW VOLTAGE CMOS STATIC RAM FEATURES • High-speed access time: 12, 15, 20, 25 ns • Automatic power-down when chip is deselected • CMOS low power operation — 345 mW (max.) operating — 7 mW (max.) CMOS standby • TTL compatible interface levels • Single 3.3V power supply • Fully static operation: no clock or refresh required • Three-state outputs ® FEBRUARY 1996 DESCRIPTION The ISSI IS61LV256 is a very high-speed, low power, 32,768-word by 8-bit static RAM. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 12 ns maximum. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation is reduced to 50 µW (typical) with CMOS input levels. Easy memory expansion is provided by using an active LOW Chip Enable (CE). The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61LV256 is available in the JEDEC standard 28-pin, 300-mil DIP and SOJ, plus the 450-mil TSOP package. FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 256 X 1024 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O7 CE OE CONTROL CIRCUIT WE ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1996, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. Rev. F 0296 SR81995LV61 2-1 ISSI IS61LV256 PIN CONFIGURATION PIN CONFIGURATION 28-Pin DIP and SOJ 28-Pin TSOP A14 1 28 VCC A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CE A0 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 I/O2 13 16 I/O4 GND 14 15 I/O3 PIN DESCRIPTIONS A0-A14 CE OE WE OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 Mode Chip Enable Input Not Selected (Power-down) Output Disabled Read Write Write Enable Input I/O0-I/O7 Input/Output Vcc Power GND Ground A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 TRUTH TABLE Address Inputs Output Enable Input 21 20 19 18 17 16 15 14 13 12 11 10 9 8 22 23 24 25 26 27 28 1 2 3 4 5 6 7 ® WE CE OE I/O Operation Vcc Current X H X High-Z ISB1, ISB2 H H L L L L H L X High-Z DOUT DIN ICC1, ICC2 ICC1, ICC2 ICC1, ICC2 ABSOLUTE MAXIMUM RATINGS(1) Symbol VTERM TBIAS TSTG PT IOUT Parameter Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current (LOW) Value –0.5 to +4.6 –55 to +125 –65 to +150 0.5 20 Unit V °C °C W mA Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2-2 Integrated Silicon Solution, Inc. Rev. F 0296 SR81995LV61 ISSI IS61LV256 ® OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V +10%, –5% 3.3V ± 5% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –2.0 mA 2.4 — V VOL Output LOW Voltage VCC = Min., IOL = 4.0 mA — 0.4 V VIH Input HIGH Voltage 2.2 VCC + 0.3 V VIL Input LOW Voltage(1) –0.3 0.8 V ILI Input Leakage GND ≤ VIN ≤ VCC Com. Ind. –2 –5 2 5 µA ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled Com. Ind. –2 –5 2 5 µA Notes: 1. VIL = –3.0V for pulse width less than 10 ns. 2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter -12 ns Min. Max. Test Conditions -15 ns Min. Max. -20 ns Min. Max. -25 ns Min. Max. Unit ICC1 Vcc Operating Supply Current VCC = Max., CE = VIL IOUT = 0 mA, f = 0 Com. Ind. — — 50 — — — 50 60 — — 50 60 — — 50 60 mA ICC2 Vcc Dynamic Operating Supply Current VCC = Max., CE = VIL IOUT = 0 mA, f = fMAX Com. Ind. — — 100 — — — 90 100 — — 80 90 — — 70 80 mA ISB1 TTL Standby Current (TTL Inputs) VCC = Max., VIN = VIH or VIL CE ≥ VIH, f = 0 Com. Ind. — — 10 — — — 10 20 — — 10 20 — — 10 20 mA ISB2 CMOS Standby Current (CMOS Inputs) VCC = Max., Com. Ind. — — 2 — — — 2 5 — — 2 5 — — 2 5 mA CE ≤ VCC – 0.2V, VIN > VCC – 0.2V, or VIN ≤ 0.2V, f = 0 Notes: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. CAPACITANCE(1,2) Symbol Parameter CIN Input Capacitance COUT Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 5 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V. Integrated Silicon Solution, Inc. Rev. F 0296 SR81995LV61 2-3 ISSI IS61LV256 ® READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol -12 ns Min. Max. Parameter -15 ns Min. Max. -20 ns Min. Max. -25 ns Min. Max. Unit tRC Read Cycle Time 12 — 15 — 20 — 25 — ns tAA Address Access Time — 12 — 15 — 20 — 25 ns tOHA Output Hold Time 2 — 2 — 2 — 2 — ns — 12 — 15 — 20 — 25 ns — 6 — 7 — 8 — 9 ns 0 — 0 — 0 — 0 — ns — 7 — 8 — 9 — 10 ns 3 — 3 — 3 — 3 — ns — 5 — 6 — 9 — 10 ns 0 — 0 — 0 — 0 — ns — 13 — 15 — 18 — 20 ns tACE tDOE tLZOE(2) tHZOE (2) tLZCE (2) tHZCE(2) tPU(3) tPD (3) CE Access Time OE Access Time OE to Low-Z Output OE to High-Z Output CE to Low-Z Output CE to High-Z Output CE to Power-Up CE to Power-Down Notes: 1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. Not 100% tested. AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Levels Output Load Unit 0V to 3.0V 3 ns 1.5V See Figures 1a and 1b AC TEST LOADS 635 Ω 3.3V OUTPUT OUTPUT 30 pF Including jig and scope Figure 1a. 2-4 635 Ω 3.3V 702 Ω 5 pF Including jig and scope 702 Ω Figure 1b. Integrated Silicon Solution, Inc. Rev. F 0296 SR81995LV61 ISSI IS61LV256 ® AC WAVEFORMS READ CYCLE NO. 1(1,2) tRC ADDRESS tAA tOHA tOHA DOUT DATA VALID READ CYCLE NO. 2(1,3) tRC ADDRESS tAA tOHA OE tDOE tLZOE CE tACE tLZCE DOUT HIGH-Z tHZCE DATA VALID tPU SUPPLY CURRENT tHZOE tPD 50% ICC 50% ISB Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE = VIL. 3. Address is valid prior to or coincident with CE LOW transitions. Integrated Silicon Solution, Inc. Rev. F 0296 SR81995LV61 2-5 ISSI IS61LV256 ® WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) Symbol -12 ns Min. Max. Parameter -15 ns Min. Max. -20 ns Min. Max. -25 ns Min. Max. Unit tWC Write Cycle Time 12 — 15 — 20 — 25 — ns tSCE CE to Write End 8 — 10 — 13 — 15 — ns tAW Address Setup Time to Write End 8 — 10 — 15 — 20 — ns tHA Address Hold from Write End 0 — 0 — 0 — 0 — ns Address Setup Time 0 — 0 — 0 — 0 — ns tPWE WE Pulse Width 8 — 10 — 13 — 15 — ns tSD Data Setup to Write End 6 — 8 — 10 — 12 — ns tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns — 6 — 7 — 8 — 10 ns 0 — 0 — 0 — 0 — ns tSA (4) tHZWE(2) tLZWE (2) WE LOW to High-Z Output WE HIGH to Low-Z Output Notes: 1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1a. 2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 4. Tested with OE HIGH. AC WAVEFORMS WRITE CYCLE NO. 1 (WE Controlled)(1,2) tWC ADDRESS tHA tSCE CE tAW tPWE WE tSA DOUT tHZWE DATA UNDEFINED tLZWE HIGH-Z tSD DIN 2-6 tHD DATA-IN VALID Integrated Silicon Solution, Inc. Rev. F 0296 SR81995LV61 ISSI IS61LV256 ® WRITE CYCLE NO. 2 (CE Controlled)(1,2) tWC ADDRESS tSA tHA tSCE CE tAW tPWE WE tHZWE DOUT DATA UNDEFINED tLZWE HIGH-Z tHD tSD DIN DATA-IN VALID Notes: 1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the Write. 2. I/O will assume the High-Z state if OE ≥ VIH. ORDERING INFORMATION Commercial Range: 0°C to +70°C ORDERING INFORMATION Industrial Range: –40°C to +85°C Speed (ns) Order Part No. Package Speed (ns) Order Part No. Package 12 12 12 IS61LV256-12N IS61LV256-12T IS61LV256-12J 300-mil Plastic DIP TSOP - 450 mil 300-mil Plastic SOJ 12 12 12 IS61LV256-12NI IS61LV256-12TI IS61LV256-12JI 300-mil Plastic DIP TSOP - 450 mil 300-mil Plastic SOJ 15 15 15 IS61LV256-15N IS61LV256-15T IS61LV256-15J 300-mil Plastic DIP 450-mil TSOP 300-mil Plastic SOJ 15 15 15 IS61LV256-15NI IS61LV256-15TI IS61LV256-15JI 300-mil Plastic DIP 450-mil TSOP 300-mil Plastic SOJ 20 20 20 IS61LV256-20N IS61LV256-20T IS61LV256-20J 300-mil Plastic DIP 450-mil TSOP 300-mil Plastic SOJ 20 20 20 IS61LV256-20NI IS61LV256-20TI IS61LV256-20JI 300-mil Plastic DIP 450-mil TSOP 300-mil Plastic SOJ 25 25 25 IS61LV256-25N IS61LV256-25T IS61LV256-25J 300-mil Plastic DIP 450-mil TSOP 300-mil Plastic SOJ 25 25 25 IS61LV256-25NI IS61LV256-25TI IS61LV256-25JI 300-mil Plastic DIP 450-mil TSOP 300-mil Plastic SOJ Integrated Silicon Solution, Inc. Rev. F 0296 SR81995LV61 2-7 IS61LV256 ISSI ISSI ® ® Integrated Silicon Solution, Inc. 680 Almanor Avenue Sunnyvale, CA 94086 Fax: (408) 245-4774 Toll Free: 1-800-379-4774 http://www.issiusa.com 2-8 Integrated Silicon Solution, Inc. Rev. F 0296 SR81995LV61