MK3805 Buffer/Clock Driver Description Features The MK3805 is a non-inverting clock driver/buffer providing two independent banks of four outputs each. These buffers have a tri-state output enable input (active low) with 1-input, 5-output configuration per group. The skew between the outputs of the same package is 0.5 ns and the skew between the outputs of different packages is 0.8 ns. The maximum input to output delay is 4.5 ns. • • • • • • • • Packaged in 20-pin SSOP Five outputs for each bank with one clock input Two separate banks of five outputs each Advanced, low-power, CMOS process Ten output clocks Two separate inputs Industrial temperature range -40°C to +85°C Hysteresis on all inputs Block Diagram VDD 2 OEA INA 5 OA0-4 OEB INB 5 OB0-4 MON 3 GND MDS 3805 B 1 Revision 031104 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK3805 Buffer/Clock Driver Pin Assignment Truth Table Inputs VCC 1 20 VCC OA0 2 19 OB0 OA1 3 18 OB1 OA2 4 17 GND 5 OA3 Outputs OEA, OEB INA, INB OAN, OBN MON L L L L OB2 L H H H 16 GND H L Z L 6 15 OB3 H H Z H OA4 7 14 OB4 GND 8 13 MON OEA 9 12 OEB 10 11 INB INA 20 pin (150 mil) SSOP/20 pin (300mil) SOIC Pin Descriptions Pin Number Pin Name Pin Type 1 VCC Power Connect to +3.3 V 2 OA0 Output Clock output. 3 OA1 Output Clock output. 4 OA2 Output Clock output. 5 GND Power Connect to ground. 6 OA3 Output Clock output. 7 OA4 Output Clock output. 8 GND Power Connect to ground. 9 OEA Input Tri state output enable input (active low). 10 INA Input Clock input. 11 INB Input Clock input. 12 OEB Input Tri state output enable input (active low). 13 MON Output Monitor output. 14 OB4 Output Clock output. 15 OB3 Output Clock output. 16 GND Power Connect to ground. 17 OB2 Output Clock output. 18 OB1 Output Clock output. 19 OB0 Output Clock output. 20 VCC Power Connect to +3.3 V MDS 3805 B Pin Description 2 Revision 031104 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK3805 Buffer/Clock Driver External Components PCB Layout Recommendations The MK3805 requires a minimum number of external components for proper operation. For optimum device performance and lowest output phase noise, the following guidelines should be observed. Decoupling Capacitors Decoupling capacitors of 0.01µF must be connected between VDD and GND, as close to these pins as possible. For optimum device performance, the decoupling capacitors should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Series Termination Resistor When the PCB trace between the clock outputs and the loads are over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance) place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. 1) The 0.01µF decoupling capacitors should be mounted on the component side of the board as close to the VDD pins as possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to VDD pin should be kept as short as possible, as should the PCB trace to the ground via. 2) To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output. 3) An optimum layout is one with all components on the same side of the board, minimizing vias through the signal layers. Other signal traces should be routed away from the MK3805. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the MK3805. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature -40 to +85°C Storage Temperature -65 to +150°C Junction Temperature 125°C Soldering Temperature 260°C MDS 3805 B 3 Revision 031104 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK3805 Buffer/Clock Driver Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Typ. Max. Units +85 °C +3.46 V -40 Power Supply Voltage (measured in respect to GND) +3.13 +3.3 DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40°C to +85°C Parameter Symbol Conditions Min. Typ. Max. Units 3.13 3.3 3.46 V Operating Voltage VDD Supply Current IDD No load, OEA,OEB GND, fo=10MHz, 50% duty cycle 3.3 mA IDD No load, OEA,OEB GND, fo=2.5MHz, 50% duty cycle 1.8 mA 3 30 µA Quiescent Current ICC Input High Voltage VIH Input Low Voltage VIL Output High Voltage VOH IOH = -4 mA VDD-0.4 V Output High Voltage VOH IOH = -12 mA 2.4 V Output Low Voltage VOL IOL = 12 mA Short Circuit Current IOS CLK output 2 V 0.8 Input Capacitance 0.4 V V ±50 mA 5 pF Nominal Output Impedance ZO 20 Ω Input Hysteresis VH 150 mV MDS 3805 B 4 Revision 031104 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK3805 Buffer/Clock Driver AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40°C to +85°C Parameter Symbol Conditions Skew between outputs of same package) tsk(o) CL=50 pF, RL=500Ω 0.5 ns Skew between outputs of different packages at same temp (same transition) tsk(t) CL=50 pF, RL=500Ω 0.8 ns Propagation Delay INA to OAN INB to OBN tPLH, tPHL CL=50 pF, RL=500Ω 4.5 ns Output Rise Time 0.8 V to 2.0 V tR CL=50 pF, RL=500Ω 2 ns Output Fall Time 2.0 V to 0.8 V tF CL=50 pF, RL=500Ω 2 ns Output Enable Time OEA to OAN, OEB to OBN CL=50 pF, RL=500Ω 1.5 6.2 ns Output Disable Time OEA to OAN, OEB to OBN CL=50 pF, RL=500Ω 1.5 5.0 ns Duty Cycle Measured at VDD/2 CL=50 pF, RL=500Ω 45 55 % Operating Frequency CL=50 pF, RL=500Ω 1 100 MHz MDS 3805 B 5 Min. 1.5 Typ. Max. Units Revision 031104 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com MK3805 Buffer/Clock Driver Package Outline and Package Dimensions (20-pin SSOP, 150Mil. Body) Package dimensions are kept current with JEDEC Publication No. 95 20 Millimeters Symbol E1 A A1 A2 b C D E E1 e L α E INDEX AREA 1 2 D Min Inches Max Min 1.35 1.75 0.10 0.25 -1.50 0.20 0.30 0.18 0.25 8.55 8.75 5.80 6.20 3.80 4.00 0.635 Basic 0.40 1.27 0° 8° Max .053 .069 .0040 .010 -.059 0.008 0.012 .007 .010 .337 .344 .228 .244 .150 .157 0.025 Basic .016 .050 0° 8° A A2 A1 c -Ce SEATING PLANE b L .10 (.004) C Ordering Information Part / Order Number Marking Shipping packaging Package Temperature MK3805RI MK3805RI Tubes 20-pin SSOP -40 to +85° C MK3805RIT MK3805RI Tape and Reel 20-pin SSOP -40 to +85° C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. MDS 3805 B 6 Revision 031104 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com