LINER LTC4301LCDD

LTC4301L
Hot Swappable 2-Wire
Bus Buffer with Low Voltage
Level Translation
DESCRIPTIO
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FEATURES
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The LTC®4301L hot swappable, 2-wire bus buffer allows
I/O card insertion into a live backplane without corruption
of the data and clock busses. In addition, the LTC4301L
SDAIN and SCLIN pins are compatible with systems with
pull-up voltages as low as 1V. Control circuitry prevents
the backplane from being connected to the card until a
stop bit or a bus idle is present. When the connection is
made, the LTC4301L provides bidirectional buffering,
keeping the backplane and card capacitances isolated.
Level Translates 1V Signals to Standard 3.3V and
5V Logic Rails
Allows Bus Pull-Up Voltages as Low as 1V on
SDAIN and SCLIN
Bidirectional Buffer* for SDA and SCL Lines
Increases Fanout
Prevents SDA and SCL Corruption During Live Board
Insertion and Removal from Backplane
Isolates Input SDA and SCL Line from Output
10kV Human Body Model ESD Protection
Supports Clock Stretching, Arbitration and
Synchronization
High Impedance SDA, SCL Pins for VCC = 0V
CS Gates Connection from Input to Output
Compatible with I2CTM, I2C Fast Mode and SMBus
Standards (Up to 400kHz Operation)
Small 8-Pin MSOP and DFN (3mm × 3mm) Packages
When driven low, the CS input pin allows the part to
connect after a stop bit or bus idle occurs. Driving CS high
breaks the connection between SCLIN and SCLOUT and
between SDAIN and SDAOUT. A logic high on READY
indicates that the backplane and card sides are connected
together.
The LTC4301L is offered in 8-pin DFN (3mm × 3mm) and
MSOP packages.
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APPLICATIO S
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, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 7032051.
Hot Board Insertion
Servers
Capacitance Buffer/Bus Extender
Desktop Computers
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TYPICAL APPLICATIO
Input-Output Connection
1.2V
3.3V
0.01µF
2k
VCC
SDA
2k
10k
VCC
SDAIN
µP
SDAOUT
10k
SDA
LTC4301L
SCL
SCLIN
SCLOUT
SCL
INPUT
SIDE
55pF
OUTPUT
SIDE
20pF
0.5V/DIV
CS
GND
READY
GND
4301l TA01a
1µs/DIV
4301 TA01b
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LTC4301L
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ABSOLUTE MAXIMUM RATINGS
(Note 1)
VCC to GND ................................................. –0.3V to 7V
SDAIN, SCLIN, SDAOUT, SCLOUT, CS ........ –0.3V to 7V
READY ........................................................ –0.3V to 6V
Operating Temperature Range
LTC4301LC ............................................. 0°C to 70°C
LTC4301LI .......................................... – 40°C to 85°C
Storage Temperature Range
MSOP ............................................... – 65°C to 150°C
DFN .................................................. – 65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER INFORMATION
TOP VIEW
CS 1
8
VCC
SCLOUT 2
7
SDAOUT
6
SDAIN
5
READY
SCLIN 3
9
GND 4
TOP VIEW
CS
SCLOUT
SCLIN
GND
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 9) IS GND
PCB CONNECTION OPTIONAL
LTC4301LCDD
LTC4301LIDD
VCC
SDAOUT
SDAIN
READY
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 125°C, θJA = 200°C/W
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
ORDER PART NUMBER
8
7
6
5
1
2
3
4
DD PART MARKING
ORDER PART NUMBER
MS8 PART MARKING
LTC4301LCMS8
LTC4301LIMS8
LTBHQ
LBHS
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
5.5
V
4.5
300
6.2
mA
µA
Power Supply
VCC
Positive Supply Voltage
ICC
Supply Current
●
2.7
VCC = 5.5V, VSDAIN = VSCLIN = 0V
VCC = 5.5V, CS = 5.5V
●
SDAOUT, SCLOUT Floating
●
0.85
1.05
1.25
V
●
60
95
175
µs
0.4
V
1.4
2
V
±0.1
±1
µA
Start-Up Circuitry
VPRE
Precharge Voltage
tIDLE
Bus Idle Time
RDYVOL
READY Output Low Voltage
VTHRCS
Connection Sense Threshold
ICS
CS Input Current
IPULLUP = 3mA
●
0.8
CS from 0V to VCC
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LTC4301L
ELECTRICAL CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VTHR
SDAIN, SCLIN Logic Input Threshold Voltage
SDAOUT, SCLOUT Logic Input Threshold Voltage
Rising Edge
Rising Edge
0.45
1.55
0.6
1.8
0.75
2.0
V
V
VHYS
SDAIN, SCLIN Logic Input Threshold Hysteresis
SDAOUT, SCLOUT Logic Input Threshold Hysteresis
(Note 3)
(Note 3)
tPLH
85
50
mV
mV
CS Delay On-Off
READY Delay Off-On
10
10
ns
ns
tPHL
CS Delay Off-On
READY Delay On-Off
95
10
µs
ns
IOFF
Ready Off Leakage Current
±0.1
µA
Input-Output Connection
VOS
Input-Output Offset Voltage
10k to VCC on SDA, SCL, VCC = 3.3V,
SDA or SCL = 0.2V (Note 2)
CIN
Digital Input Capacitance SDAIN, SDAOUT,
SCLIN, SCLOUT
(Note 3)
ILEAK
Input Leakage Current
SDA, SCL Pins
VOL
Output Low Voltage, Input = 0V
SDA, SCL Pins,
ISINK = 3mA, VCC = 2.7V
SDA, SCL Pins,
ISINK = 1mA, VCC = 2.7V
●
●
0
100
175
mV
10
pF
±5
µA
0
0.4
V
0
0.2
V
Timing Characteristics
fI2C,MAX
I2C Maximum Operating Frequency
(Note 3)
tBUF
Bus Free Time Between Stop and Start
Condition
(Note 3)
1.3
µs
tHD,STA
Hold Time After (Repeated) Start Condition
(Note 3)
100
ns
tSU,STA
Repeated Start Condition Set-Up Time
(Note 3)
0
ns
tSU,STO
Stop Condition Set-Up Time
(Note 3)
0
ns
tHD,DATI
Data Hold Time Input
(Note 3)
0
ns
tSU,DAT
Data Set-Up Time
(Note 3)
100
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
400
600
kHz
Note 2: The connection circuitry always regulates its output to a higher
voltage than its input. The magnitude of this offset voltage as a function of
the pull-up resistor and VCC voltage is shown in the Typical Performance
Characteristics section.
Note 3: Determined by design, not tested in production.
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LTC4301L
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TYPICAL PERFOR A CE CHARACTERISTICS
Input – Output High to Low
Propagation Delay vs
Temperature
ICC vs Temperature
4.9
100
4.8
300
VCC = 5.5V
250
80
4.6
TIME (ns)
VCC = 3.3V
4.3
VCC = 2.7V
4.2
4.1
60
40
20
4.0
3.9
–80 –60 –40 –20 0 20 40 60
TEMPERATURE (°C)
80 100
VOUT – VIN (mV)
VCC = 3.3V
4.5
4.4
TA = 25°C
VIN = 0V
VCC = 2.7V
4.7
ICC (mA)
Connection Circuitry VOUT – VIN
0
–50
VCC = 5.5V
200
150
VCC = 5V
100
VCC = 3.3V
CIN = COUT = 100pF
RPULLUPIN = RPULLUPOUT = 10k
–25
0
25
50
TEMPERATURE (°C)
4301 G01
50
75
100
4301 G02
0
0
10,000
20,000
30,000
RPULLUP (Ω)
40,000
4301 G03
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CS (Pin 1): The connection sense pin is a 1.4V threshold
digital input pin. For normal operation CS is grounded.
Driving CS above the 1.4V threshold isolates SDAIN from
SDAOUT and SCLIN from SCLOUT and asserts READY
low.
READY (Pin 5): The READY pin is an open drain N-channel
MOSFET output which pulls down when CS is high or
when the start-up sequence described in the Operation
section has not been completed. READY goes high when
CS is low and a start-up is complete.
SCLOUT (Pin 2): Serial Clock Output. Connect this pin to
the SCL bus on the card.
SDAIN (Pin 6): Serial Data Input. Connect this pin to the
SDA bus on the backplane.
SCLIN (Pin 3): Serial Clock Input. Connect this pin to SCL
on the bus backplane.
SDAOUT (Pin 7): Serial Data Output. Connect this pin to
the SDA bus on the card.
GND (Pin 4, 9): Ground. Connect this pin to a ground plane
for best results. Exposed pad (DFN package) is ground.
VCC (Pin 8): Main Input Supply. Place a bypass capacitor
of at least 0.01µF close to VCC for best results.
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LTC4301L
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BLOCK DIAGRA
LTC4301L Supply Independent 2-Wire Bus Buffer
PRECHARGE
VCC 8
CONNECT PRECHARGE
CONNECT
6
R1
200k
SDAIN
R2
200k
SDAOUT
7
CONNECT
3
SCLOUT
SCLIN
LOGIC
2
PRECHARGE
CONNECT
0.6V
1.8V
1
CONNECT
CS
1.4V
UVLO
READY
5
95µs
DELAY
CONNECT
GND
4
4301l BD
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LTC4301L
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OPERATIO
Start-Up
Input-to-Output Offset Voltage
When the LTC4301L first receives power on its VCC pin,
either during power-up or live insertion, it starts in an
undervoltage lockout (UVLO) state, ignoring any activity
on the SDA or SCL pins until VCC rises above 2.5V. This is
to ensure that the part does not try to function until it has
enough voltage to do so.
When a logic low voltage, VLOW1, is driven on any of the
LTC4301L’s data or clock pins, the LTC4301L regulates
the voltage on the other side of the device (call it VLOW2)
at a slightly higher voltage, as directed by the following
equation:
During this time, the 1V precharge circuitry is active and
forces 1V through 200k nominal resistors to the SDAOUT
and SCLOUT pins. Precharging the SCLOUT and SDAOUT
pins to 1V minimizes the worst-case voltage differential
these pins will see at the moment of connection, therefore
minimizing bus disturbances.
where R is the bus pull-up resistance in ohms. For example, if a device is forcing SDAOUT to 10mV where VCC
= 3.3V and the pull-up resistor R on SDAIN is 10k, then the
voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 70 =
108mV(typical). See the Typical Performance Characteristics section for curves showing the offset voltage as a
function of VCC and R.
Once the LTC4301L comes out of UVLO, it assumes that
SDAIN and SCLIN have been inserted into a live system
and that SDAOUT and SCLOUT are being powered up at
the same time as itself. Therefore, it looks for either a stop
bit or bus idle condition on the backplane side to indicate
the completion of a data transaction. When either one
occurs, the part also verifies that both the SDAOUT and
SCLOUT voltages are high. When all of these conditions
are met, the input-to-output connection circuitry is activated, joining the SDA and SCL busses on the I/O card with
those on the backplane.
VLOW2 = VLOW1 + 75mV + (VCC/R) • 70Ω (typical)
Propagation Delays
During a rising edge, the rise time on each side is determined by the bus pull-up resistor and the equivalent
capacitance on the line. In Figure 1, VCC = 3.3V, SDAOUT
and SCLOUT are pulled-up to 3.3V with 10k resistor (20pF
on this side) and SDAIN and SCLIN are pulled-up to 1.2V
with a 2k resistor (55pF on this side). Lower pull-up
resistor values are used on the input side to allow the
output side to be released sooner.
Connection Circuitry
Once the connection circuitry is activated, the functionality of the SDAIN and SDAOUT pins is identical. A low
forced on either pin at any time results in both pin voltages
being low. For proper operation, logic low input voltages
should be no higher than 0.4V with respect to the ground
pin voltage of the LTC4301L. SDAIN and SDAOUT enter a
logic high state only when all devices on both SDAIN and
SDAOUT release high. The same is true for SCLIN and
SCLOUT. This important feature ensures that clock stretching, clock synchronization, arbitration and the acknowledge protocol always work, regardless of how the devices
in the system are tied to the LTC4301L.
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the backplane
and card capacitances isolated. Because of this isolation,
the waveforms on the backplane busses look slightly
different than the corresponding card bus waveforms as
described here.
INPUT
SIDE
55pF
OUTPUT
SIDE
20pF
0.5V/DIV
1µs/DIV
4301 TA01b
Figure 1. Input-Output Connection
There is a finite high to low propagation delay through the
connection circuitry for falling waveforms. Figure 2 shows
the falling edge waveforms for the same pull-up resistors
and equivalent capacitance conditions as used in Figure 1.
An external N-channel MOSFET device pulls down the
voltage on the side with 55pF capacitance; LTC4301L pulls
down the voltage on the opposite side with a delay of 60ns.
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LTC4301L
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OPERATIO
This delay is always positive and is a function of supply
voltage, temperature and the pull-up resistors and equivalent bus capacitances on both sides of the bus. The Typical
Performance Characteristics section shows the high to
low propagation delay as a function of temperature and
voltage for 10k pull-up resistors pulled-up to VCC and
100pF equivalent capacitance on both sides of the part.
Larger output capacitances translate to longer delays (up
to 150ns). Users must quantify the difference in propaga-
tion times for a rising edge versus a falling edge in their
systems and adjust setup and hold times accordingly.
Ready Digital Output
This pin provides a digital flag which is low when either CS
is high or the start-up sequence described earlier in this
section has not been completed. READY goes high when
CS is low and start-up is complete. The pin is driven by an
open-drain pull-down capable of sinking 3mA while holding 0.4V on the pin. Connect a resistor of 10k to VCC to
provide the pull-up.
Connection Sense
OUTPUT
SIDE
20pF
INPUT
SIDE
55pF
0.5V/DIV
4301 F02
20ns/DIV
Figure 2. Input-Output Connection
High to Low Propagation Delay
When the CS pin is driven above 1.4V with respect to the
LTC4301L’s ground, the backplane side is disconnected
from the card side and the READY pin is internally pulled
low. When the pin voltage is low, the part waits for data
transactions on both the backplane and card sides to be
complete (as described in the Start-Up section) before
reconnecting the two sides. At this time the internal
pulldown on READY releases.
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APPLICATIO S I FOR ATIO
Live Insertion and Capacitance Buffering Application
Figure 3 illustrates applications of the LTC4301L with
different bus pull-up and VCC voltages, demonstrating its
ability to recognize and buffer bus data levels that are
above or below its VCC supply. All of these applications
take advantage of the LTC4301L’s Hot SwapTM controlling,
capacitance buffering and precharge features. If the I/O
cards were plugged directly into the backplane without the
LTC4301L buffer, all of the backplane and card capacitances would add directly together, making rise- and falltime requirements difficult to meet. Placing an LTC4301L
on the edge of each card, however, isolates the card
capacitance from the backplane. For a given I/O card, the
LTC4301L drives the capacitance of everything on the card
and the backplane must drive only the capacitance of the
LTC4301L, which is less than 10pF.
In most applications the LTC4301L will be used with a
staggered connector where VCC and GND will be long pins.
SDA and SCL are medium length pins to ensure that the
VCC and GND pins make contact first. This will allow the
precharge circuitry to be activated on SDA and SCL before
they make contact. CS is a short pin that is pulled up when
not connected. This is to ensure that the connection
between the backplane and the cards data and clock
busses is not enabled until the transients associated with
live insertion have settled.
Figure 4 shows the LTC4301L in an application where all
of the pins have the same length. In this case, an RC filter
circuit on the I/O card with a product of 10ms provides a
filter to prevent the LTC4301L from becoming activated
until the transients associated with live insertion have
settled. Connect the capacitor between VCC and CS, and
the resistor from CS to GND.
Hot Swap is a trademark of Linear Technology Corporation.
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LTC4301L
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APPLICATIO S I FOR ATIO
STAGGERED CONNECTOR
5V
1.2V
2k
2k
SDA
SCL
0.01µF
10k
10k
CS
SDAIN
SCLIN
BACKPLANE
CONNECTOR
10k
VCC
SDAOUT
CARD_SDA
LTC4301L
SCLOUT
CARD_SCL
GND
READY
CARD
STAGGERED CONNECTOR
3.3V
1.2V
2k
2k
SDA
SCL
0.01µF
10k
10k
CS
SDAIN
SCLIN
BACKPLANE
CONNECTOR
10k
VCC
SDAOUT
CARD_SDA
LTC4301L
SCLOUT
CARD_SCL
GND
READY
CARD
3V
STAGGERED CONNECTOR
3.3V
1V
2k
2k
SDA
SCL
0.01µF
10k
10k
CS
SDAIN
SCLIN
10k
VCC
SDAOUT
CARD_SDA
LTC4301L
SCLOUT
CARD_SCL
GND
READY
4301l F03
BACKPLANE
CONNECTOR
CARD
Figure 3. Typical Supply Independent Applications
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LTC4301L
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APPLICATIO S I FOR ATIO
1.2V
3.3V
0.01µF
10k
10k
VCC
2k
LTC4301L
STAGGERED CONNECTOR
2k
BACK_SCL
BACK_SDA
SCLIN
SCLOUT
CARD_SCL
SDAIN
SDAOUT
CARD_SDA
3.3V
10k
FROM
MICROPROCESSOR
CS
GND
READY
4301l F05
BACKPLANE
CONNECTOR
CARD
Figure 4. Inserting Multiple I/O Cards into a Live Backplane Using a Connector with All the Pins the Same Length
4301lfa
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LTC4301L
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PACKAGE DESCRIPTIO
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
0.675 ±0.05
3.5 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
PACKAGE
OUTLINE
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
5
3.00 ±0.10
(4 SIDES)
0.38 ± 0.10
8
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
(DD) DFN 1203
0.200 REF
0.75 ±0.05
0.00 – 0.05
4
0.25 ± 0.05
1
0.50 BSC
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
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LTC4301L
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PACKAGE DESCRIPTIO
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.42 ± 0.038
(.0165 ± .0015)
TYP
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.65
(.0256)
BSC
8
7 6 5
0.52
(.0205)
REF
RECOMMENDED SOLDER PAD LAYOUT
0.254
(.010)
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0° – 6° TYP
GAUGE PLANE
0.53 ± 0.152
(.021 ± .006)
DETAIL “A”
1
2 3
4
1.10
(.043)
MAX
0.86
(.034)
REF
0.18
(.007)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.65
(.0256)
BSC
0.127 ± 0.076
(.005 ± .003)
MSOP (MS8) 0204
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
4301lfa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTC4301L
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TYPICAL APPLICATIO
System with Active Connection Control
1.2V
3.3V
0.01µF
10k
10k
VCC
2k
LTC4301L
STAGGERED CONNECTOR
2k
BACK_SCL
BACK_SDA
SCLIN
SCLOUT
CARD_SCL
SDAIN
SDAOUT
CARD_SDA
3.3V
10k
FROM
MICROPROCESSOR
CS
GND
READY
4301l F05
BACKPLANE
CONNECTOR
CARD
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4301lfa
12 Linear Technology Corporation
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