Part Numbers May Be Marked With "IMP" or "Ei." Ei82C684 Ei68C684 QUAD UART Semiconductor, Inc. FEATURES • Programmable internal clock:X1/CLK or X1/CLK divided by 2 • Full duplex, four channel asynchronous receiver and transmitter • Buffered system clock output pin • Stand-by mode to reduce operating power • Quadruple-buffered receiver and transmitter • Advanced CMOS low power technology • Internal bit rate generator with 23 industry standard bit rates operating from either of two standard crystal clocks Independent bit rate selection for each receiver and transmitter • Maximum bit rate: 1 x clock - 2 Mb/sec., 16 x clock- 250 Kb/sec. • Normal, auto-echo, local loop-back and remote loop-back modes • Multi-function 16-bit counter/timer • Programmable interrupt daisy chain • Up to 32 I/O pins (depending on package and version) • Change of state detectors on inputs • Multidrop mode compatible with 8051 ninebit mode • Stop bits programmable in 1/16-bit increments • Pin selectable 88xxx/68xxx interface • Debounced reset pin (20 nsec. min) • On-chip oscillator for crystal The Epic Ei68C684/Ei88C684 Quad Universal Asynchronous Receiver and Transmitter (QUART) is a data communication device that provides four fully independent full duplex asynchronous communication channels in a single package. The QUART is designed for use in microprocessor based systems and may be used in a polled or interrupt driven environment. Two basic versions of the QUART are pin selectable with SEL pin and each is optimized for use with various microprocessor families: the Ei88C684 for 8080/5, 8086/88, Z80, Z8000, 68XX and 65XX family based systems., and the 68C681 for 68000 family based systems.and the Ei68C684 for 68000family based systems A programmable mode of the Ei88C684 versions provides an interrupt daisy chain for use in Z80 and Z8000 based systems. The bus interfaces are however general enough to allow interfacing with other microprocessors and microcontrollers. The Ei88C684 and Ei68C684 are high integrated versions of Epic Semiconductor’s Ei88C681 and Ei66C681 DUART’s respectively, and are function compatible with those devices. 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 OP4 X2 X1/CLK RXDB TXDB OP3 OP2 SEL VCC0 VCC1 RESET OP1(RTSB•) OP0(RTSA•) TXDA RXDA IP7 IP6 X2 X1/CLK RXDB TXDB OP3 SEL VCC RESET OP1(RTSB) OP0(RTSA) TXDA • DESCRIPTION Ei82C684 1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 IP5 IP4• RD• IP3 IP2 IP1(CTSB•) IP0(CTSA•) A1 A2 A3 A4 A5 IP8(CTSC•) IP9(CTSD•) IP10 IP11 IEI D0 D1 D2 D3 D4 D5 D6 D7 R/WN CEN RXDD Ei82C684 RXDA RDN IP1(CTSB) IP0(CTSA) A1 A2 A3 A4 A5 IP8(CTSC) IP9(CTSD) 68-PIN PLCC TXDD (IEO) IACKN INTRN OP11 GND OP9(RTSD) OP8(RTSB) TXDC RXDC IEI 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 RXDD TXDD (IEO) IACK• INTR• CLKBUF+OP11 GND GND OP10 OP9(RTSD•) OP8(RTSC•) TXDC RXDC IP15 IP14 IP13 IP12 OP5 OP6 OP7 D0 D1 D2 D3 D4 D5 D6 D7 WR• CE• OP15 OP14 OP13 OP12 44-PIN PLCC 15 For additional information, contact IMP, Inc. at 408.432.9100 or visit www.impweb.com IMP, Inc. acquired Epic products on January 26, 2001. (see press release at http://www.impweb.com/PRESS/PR012601.htm) Ei68C684 Ei88C684 QUAD UART Semiconductor, Inc. BLOCK DIAGRAM TXDx(•) RXDx CHANNEL x INPUT PORT A INPUT PORT b OUTPUT PORT A OUTPUT PORT B TRANSMIT AND RECEIVE SHIFT REGISTER CHANGE OF STATE DETECTORS (4) CHANGE OF STATE DETECTORS (4) FUNCTION SELECT LOGIC FUNCTION SELECT LOGIC ACRA ACRB OPRA OPRB IPCRA IPCRB OPCRA OPCRB MR1x RECEIVE FIFO (3) MR2x SRx • TRANSMIT HOLDING REGISTER • • • • INTERNAL DATA BUS • • • • • • TIMING BUS BUFFER COMMAND DECODE CRA CRA CRA CRA IVRA IVRB IMRA IMRB ISRA IVRB BIT RATE GENERATOR CSRA IEO/DTACK• IEI IACK• INTR• RESET/RESET• CE• WR•/R/W• RD• A0-A4/A1/A5 D0-D7 CSRB 16 COUNTER TIMER B COUNTER TIMER A CSRC CSRD CRYSTAL OSCILLATOR ACRA ACRB X1/CLK ADDRESS DECODE CLOCK SELECTORS INTERRUPT CONTROL CTURA CTURB X2 OPERATION CONTROL CTLRA CTLRB