DATA SHEET Part No. AN8150FB Package Code No. QFP044-P-1010F Publication date: February 2008 SDJ00021AEB 1 AN8150FB Contents Overview ……..……………………………………………………………………………………………………. 3 Features ……..……………………………………………………………………………………………………. 3 Applications Package Type ………………………………………………………………………………………………………. 3 …………………………………...………………………………………………………………………. 3 …………….………………………………………………………………………………………………… 3 Block Diagram ………………………………………….…………………………………………………………. 4 Pin Descriptions …………………..………………………………………………………………………………. 5 Absolute Maximum Ratings ……………………..……………..…………………………......………………… 7 Operating Supply Voltage Range …………………………………………..……………………………………. 7 Electrical Characteristics Technical Data Usage Notes ………………….………………….…………………………………………………. 8 …………………………………….………….…………………………………………………. 9 ……….……………………….………………….…………………………………………………. 17 SDJ00021AEB 2 AN8150FB AN8150FB Octal, high precision 13-bit voltage output DAC Overview AN8150FB is IC which has octal 13 bit DACs constituted by Bi-CMOS process. Features y Resolution: 13-bit y Built-in DAC: 8 DACs. y Integral linearity error: ±2 LSB typ. y Differential linearity error: ±0.5 LSB typ. y Supply voltage: +10.5 V (AVCC), –7.5 V (AVEE), +5 V (VDD) y Output range: –3.3 V to +7.7 V y DAC input data: 13-bit parallel y DAC selection address data: 3-bit parallel y Input interface: TTL compatible Applications y Industrial instrumentation Package y 44 pin plastic quad flat package (QFP type) Type y Silicon monolithic bipolar IC SDJ00021AEB 3 AN8150FB D0(LSB) 15 D1 16 D2 17 D3 18 D4 19 D5 20 D6 21 D7 22 D8 23 D9 24 INPUT LATCH A DAC LATCH A (DAC+BUF) INPUT LATCH B DAC LATCH B (DAC+BUF) INPUT LATCH C DAC LATCH C (DAC+BUF) INPUT LATCH D DAC LATCH D (DAC+BUF) INPUT LATCH E DAC LATCH E (DAC+BUF) INPUT LATCH F DAC LATCH F (DAC+BUF) INPUT LATCH G DAC LATCH G (DAC+BUF) INPUT LATCH H DAC LATCH H (DAC+BUF) DAC A DAC B 2 VOUTA 44 VOUTB 1 AMPREFAB DAC C DAC D 43 VOUTC 41 VOUTD 42 AMPREFCD DAC E DAC F 37 VOUTE 35 VOUTF 36 AMPREFEF D10 25 D11 26 38 AVCC 5 AVCC 29 AVEE 6 AVEE 4 VRMAB 3 VRBAB 14 VSS 13 VDD Block Diagram DAC G 34 VOUTG D12(MSB) 27 A2 8 A1 9 DAC H 32 VOUTH 33 AMPREFGH CONTROL LOGIC CLR 28 VRMGH 30 VRBGH 31 VRMCDEF 39 VRBCDEF 40 LD 7 WR 12 CS 11 A0 10 Note) This block diagram is for explaining functions. The part of the block diagram may be omitted, or it may be simplified. SDJ00021AEB 4 AN8150FB Pin Descriptions Pin No. Pin name Type Input Description 1 AMPREFAB 2 VOUTA Output 3 VRBAB Input Reference voltage (Bottom) for DAC A, B 4 VRMAB Input Reference voltage (Midpoint) for DAC A, B 5 AVCC Power supply Analogue positive supply voltage 6 AVEE Power supply Analogue negative supply voltage 7 LD Input Load input 8 A2 Input Address 2 digital input (MSB) 9 A1 Input Address 1 digital input 10 A0 Input Address 0 digital input (LSB) 11 CS Input Chip selection digital input 12 WR Input Write digital input 13 VDD Power supply 14 VSS GND Ground for digital 15 D0(LSB) Input Digital input (LSB) 16 D1 Input Digital input 17 D2 Input Digital input 18 D3 Input Digital input 19 D4 Input Digital input 20 D5 Input Digital input 21 D6 Input Digital input 22 D7 Input Digital input 23 D8 Input Digital input 24 D9 Input Digital input 25 D10 Input Digital input 26 D11 Input Digital input 27 D12(MSB) Input Digital input (MSB) 28 CLR Input Asynchronous clear input 29 AVEE Power supply 30 VRMGH Input Reference voltage (Midpoint) for DAC G, H 31 VRBGH Input Reference voltage (Bottom) for DAC G, H 32 VOUTH Output 33 AMPREFGH 34 VOUTG Input Output Offset adjustment for DAC A, B Output voltage of DAC A Digital positive supply voltage Analogue negative supply voltage Output voltage of DAC H Offset adjustment for DAC G, H Output voltage of DAC G SDJ00021AEB 5 AN8150FB Pin Descriptions (continued) Pin No. Pin name Type Output Description 35 VOUTF 36 AMPREFEF 37 VOUTE 38 AVCC 39 VRMCDEF Input Reference voltage (Midpoint) for DAC C, D, E, F 40 VRBCDEF Input Reference voltage (Bottom) for DAC C, D, E, F 41 VOUTD 42 AMPREFCD 43 VOUTC Output Output voltage of DAC C 44 VOUTB Output Output voltage of DAC B Input Output Power supply Output Input Output voltage of DAC F Offset adjustment for DAC E, F Output voltage of DAC E Analog positive supply voltage Output voltage of DAC D Offset adjustment for DAC C, D SDJ00021AEB 6 AN8150FB Absolute Maximum Ratings A No. 1 2 Parameter Supply voltage Supply current Symbol Rating Unit Note AVCC – AVEE 19.7 V VDD 7 V ICC 50 mA ⎯ IEE –50 mA ⎯ IDD 10 mA ⎯ *1 3 Power dissipation PD 359 mW *2 4 Operating ambient temperature Topr 0 to +70 °C *3 5 Storage temperature Tstg –55 to +125 °C *3 Note) *1: The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2: The power dissipation shown is the value at Ta = 70°C for the independent (unmounted) IC package without a heat sink. When using this IC, refer to the • PD – Ta diagram in the Technical Data and use under the condition not exceeding the allowable value. *3: Except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for Ta = 25°C. Operating Supply Voltage Range Parameter Supply voltage range Symbol Range AVCC +10.0 V to +11.0 V AVEE –7.7 V to –6.8 V VDD 4.75 V to 5.25 V Unit Note ⎯ V ⎯ ⎯ Note) The values under the condition not exceeding the above absolute maximum ratings and the power dissipation. SDJ00021AEB 7 AN8150FB Electrical Characteristics at AVCC = 10.5 V, AVEE = –7.5 V, VDD = 5 V Note) Ta = 25°C±2° unless otherwise specified. B No. Parameter Symbol Conditions Limits Min Typ Max Unit No te 1 Supply current ICC — 28 33 38 mA — 2 Supply current IEE — –33 –28 –23 mA — 3 Supply current IDD — — 0.01 1 mA — 4 High digital input current IIH — –1 — 1 μA — 5 Low digital input current IIL — –1 — 1 μA — 6 High reference resistor current (1) IVRM VRMAB, VRMGH VRM = 2.2 V, VRB = 0 V –3 –1.5 — μA — 7 Low reference resistor current (1) IVRB VRBAB, VRBGH VRM = 2.2 V, VRB = 0 V μA — 8 High reference resistor current (2) IVRM VRMCDEF VRM = 2.2 V, VRB = 0 V μA — 9 Low reference resistor current (2) IVRB VRBCDEF VRM = 2.2 V, VRB = 0 V μA — –1 870 –1 600 –1 330 –6 –3 — –3 740 –3 200 – 2 660 10 High-level digital input voltage DIH — 0.7 × VDD — VDD V — 11 Low-level digital input voltage DIL — VSS — 0.3 × VDD V — 12 Max. output voltage VOMAX — AVCC –2 — — V *1 13 Min. output voltage VOMIN — — — AVEE +3 V *1 14 Reference voltage (midpoint) VRM — VRB 2.2 — V *1 15 Reference voltage (bottom) VRB — — 0 VRM V *1 16 Resolution Res — — 13 — Bits — 17 Linearity error EL — — ±2 ±4 LSB — 18 Differential linearity error ED — — ±0.5 ±1 LSB — 19 Full-scale error EFS — — ±4 ±8 LSB — 20 Zero-scale error EZS — — ±4 ±8 LSB 21 Gain error EG — — ±4 ±10 LSB 22 Offset error EOFF — — ±4 ±8 LSB 23 Output voltage slew rate SR — 3 — — V/μs 24 Settling time TST — — — 30 μs Note) *1: Sets so that the following conditions are satisfied. For details, refer to Technical Data. VOMAX = 5 × VRM – 2.5 × VRB – 1.5 × AMPREF < AVCC – 2 V VOMIN = 2.5 × VRB – 1.5 × AMPREF > AVEE + 3 V SDJ00021AEB 8 AN8150FB Technical Data 1. I/O block circuit diagrams and pin function descriptions Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage Internal circuit Impedance Offset adjustment pin of DAC A, B. Apply the same voltage as VRMAB normally. AVCC (Pin5, Pin38) 1 DC = 2.2 V Description 1 10 MΩ or more AVEE (Pin6, Pin29) 2, 32, 34, 35, 37, 41, 43, 44 7.7 V Pin 2, 32, 34, 35, 37, 41, 43, 44 DAC A to H output voltage AVCC (Pin 5, Pin 38) 80 Ω –3.3 V AVEE (Pin 6, Pin 29) Reference voltage of DAC A, B (bottom). Apply 0 V normally. AVCC (Pin 5, Pin 38) 3 DC = 0 V 3 1.38 kΩ or more AVEE (Pin 6, Pin 29) AVCC (Pin 5, Pin 38) 4 DC = 2.2 V 4 10 MΩ or more Reference voltage of DAC A, B (midpoint) VRTAB. i.e., 2 × (VRMAB–VRBAB) is generated inside the IC. DAC A, B output amplitude = 2.5 × (VRTAB – VRBAB) AVEE (Pin 6, Pin 29) 5, 38 +10.0 V to +11.0 V — — Analog positive supply voltage Apply 10.5 V normally 6, 29 –7.7 V to –6.8 V — — Analog negative supply voltage Apply –7.5 V normally. SDJ00021AEB 9 AN8150FB Technical Data (continued) 1. I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage Internal circuit Impedance Load input Transfer the data of input latch to DAC latch at LD. Start DAC settling. VDD (Pin 13) 5V 7 7 Description 10 MΩ or more 0V VSS (Pin 14) Address input A2: MSB, A0: LSB VDD (Pin13) 5V Pin 8, 9, 10 8, 9, 10 10 MΩ or more 0V VSS (Pin14) Chip select digital input Level trigger. DAC determined by A1, A2, and A0 is selected when this pin is low. VDD (Pin 13) 5V 11 11 10 MΩ or more 0V VSS (Pin 14) VDD (Pin 13) 5V 10 MΩ or more 12 12 Write digital input Level trigger. The data is written to the input latch of DAC selected at A2, A1, A0 when this pin is low. 0V VSS (Pin 14) 13 +4.75 V to +5.25 V — — Digital positive supply voltage Apply 5 V normally. 14 0V — — Digital ground SDJ00021AEB 10 AN8150FB Technical Data (continued) 1. I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage Internal circuit Impedance Description Digital input DB0: LSB, DB12: MSB VDD (Pin 13) 5V Pin 15 to 27 15 to 27 10 MΩ or more 0V VSS (Pin 14) Asynchronous clear input 0 V is output during low. The previous value is hold as for latch. VDD (Pin 13) 5V 28 28 10 MΩ or more 0V VSS (Pin 14) AVCC (Pin 5, Pin 38) 30 DC = 2.2 V 30 10 MΩ or more Reference voltage of DAC G, H (midpoint) VRTGH. i.e., 2 × (VRMGH – VRBGH) is generated inside the IC. DAC G, H output amplitude = 2.5 × (VRTGH – VRBGH) AVEE (Pin 6, Pin 29) Reference voltage of DAC G, H (bottom). Apply 0 V normally. AVCC (Pin 5, Pin 38) 31 DC = 0 V 31 1.38 kΩ AVEE (Pin 6, Pin 29) SDJ00021AEB 11 AN8150FB Technical Data (continued) 1. I/O block circuit diagrams and pin function descriptions (continued) Note) The characteristics listed below are reference values based on the IC design and are not guaranteed. Pin No. Waveform and voltage Internal circuit Impedance Offset adjustment pin of DAC G, H. Apply the same voltage as VRMGH normally. AVCC (Pin 5, Pin 38) 33 DC = 2.2 V 33 Description 9 kΩ AVEE (Pin 6, Pin 29) Offset adjustment pin of DAC E, F. Apply the same voltage as VRMEF normally. AVCC (Pin 5, Pin 38) 36 DC = 2.2 V 36 9 kΩ AVEE (Pin 6, Pin 29) AVCC (Pin 5, Pin 38) 39 DC = 2.2 V 39 10 MΩ or more Reference voltage of DAC C, D, E, F (midpoint) VRTAB. i.e., 2 × (VRMCDEF – VRBCDEF) is generated inside the IC. DAC C, D, E, F output amplitude = 2.5 × (VRTCDEF – VRBCDEF) AVEE (Pin 6, Pin 29) Reference voltage of DAC C, D, E, F (bottom). Apply 0 V normally. AVCC (Pin 5, Pin 38) 40 DC = 0 V 40 0.69 kΩ AVEE (Pin 6, Pin 29) Offset adjustment pin of DAC C, D. Apply the same voltage as VRMCD normally. AVCC (Pin 5, Pin 38) 42 DC = 2.2 V 42 9 kΩ AVEE (Pin 6, Pin 29) SDJ00021AEB 12 AN8150FB Technical Data (continued) 2. Timing chart At operation of D/A converter t1 t2 A0, A1, A2 t5 t6 t3 CS t4 WR t8 t7 DATA t10 LDAC t9 t11 VOUT At CLR operation t12 CLR t14 t13 VOUT Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 0V Rating 25 25 75 75 0 0 15 15 75 100 30 75 30 30 Unit ns ns ns ns ns ns ns ns ns ns μs ns μs μs Description Setup time of A0, A1, A2 compared to WR Hold time of A0, A1, A2 compared to WR Pulse width of CS Min. pulse width of WR Setup time of CS compared to WR Hold time of CS compared to WR Setup time of DATA compared to WR Hold time of DATA compared to WR Min. pulse width of LDAC Setup time of WR compared to LDAC Settling time of VOUT compared to LDAC Min. pulse width of CLR Settling time of VOUT compared to CLR Settling time of VOUT compared to CLR cancel SDJ00021AEB 13 AN8150FB Technical Data (continued) 3. Truth table DAC address A2 A1 A0 0 0 0 DAC A input latch 0 0 1 DAC B input latch 0 1 0 DAC C input latch 0 1 1 DAC D input latch 1 0 0 DAC E input latch 1 0 1 DAC F input latch 1 1 0 DAC G input latch 1 1 1 DAC H input latch 機能 DAC operation CLR LD WR CS INPUT LATCH DAC LATCH 1 0 0 0 T T 1 1 1 x L L 1 1 x 1 L L 1 x 0 0 T x 1 x 1 x L x 1 x x 1 L x 1 0 x x x T (0 V) 0 x x x T (0 V) T (0 V) Note) T: through L: latch SDJ00021AEB 14 AN8150FB Technical Data (continued) 4. DAC code table Bipolar Unipolar VRM 2.2 V (VRT = 4.4 V) *1 2 V (VRT = 4 V) VRB 0V 0V Output amplitude 11 V[p-p] 10 V[p-p] Midpoint electric potential 2.2 V 2V DACOUT (Max) 7.69866 V 6.99878 V DACOUT (Min) –3.3 V –3 V 1 1111 1111 1111 7.69866 V 6.99878 V : : : 1 0000 0000 0001 2.20134 V 2.00122 V 1 0000 0000 0000 2.2 V 2V 0 1111 1111 1111 2.19866 V 1.99878 V : : : 0 0000 0000 0001 –3.29866 V –2.99878 V 0 0000 0000 0000 –3.3 V –3 V Note) *1: VRT = 2 × VRM – VRB (generated inside) VDAC = (VRM–VRB) × 2 × D/8192+VRB (internal DAC output voltage) DACOUT = 2.5 × VDAC – 1.5 × AMPREF AMPREF = VRM VRT VRB DAC VDAC + amp. – DACOUT 1.5R R AMPREF Equivalent circuit of DAC output block SDJ00021AEB 15 AN8150FB Technical Data (continued) 5. PD ⎯ Ta diagram SDJ00021AEB 16 AN8150FB Usage Notes 1. This IC is intended to be used for Industrial instrumentation. Consult our sales staff in advance for information on the following applications: • Special applications in which exceptional quality and reliability are required, or if the failure or malfunction of this IC may directly jeopardize life or harm the human body. • Any applications other than the standard applications intended. 1) Space appliance (such as artificial satellite, and rocket) 2) Traffic control equipment (such as for automobile, airplane, train, and ship) 3) Medical equipment for life support 4) Submarine transponder 5) Control equipment for power plant 7) Weapon 8) Others: Applications of which reliability equivalent to 1) to 7) is required. 2. Pay attention to the direction of LSI. When mounting it in the wrong direction onto the PCB (printed-circuit-board), it might smoke or ignite. 3. Pay attention in the PCB (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins. In addition, refer to the Pin Description for the pin configuration. 4. Perform a visual inspection on the PCB before applying power, otherwise damage might happen due to problems such as a solderbridge between the pins of the semiconductor device. Also, perform a full technical verification on the assembly quality, because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the LSI during transportation. 5. Take notice in the use of this product that it might break or occasionally smoke when an abnormal state occurs such as output pin – VCC short (Power supply fault), output pin – GND short (Ground fault), or output-to-output-pin short (load short). And, safety measures such as an installation of fuses are recommended because the extent of the above-mentioned damage and smoke emission will depend on the current capability of the power supply. 6. When using the LSI for new models, verify the safety including the long-term reliability for each product. 7. When the application system is designed by using this LSI, be sure to confirm notes in this book. Be sure to read the notes to descriptions and the usage notes in the book. 8. Power-on sequence Note that this IC may be latched up depending on the power-on sequence because it has positive/negative multi-power supplies. The recommended power-on sequence is described below. 1) DVDD ↓ 2) AVCC , VRT, VRB, AMPREF (No sequence limit) Note) The sequence of AVEE does not matter; that is, AVEE does not malfunction either before or after DVDD . 9. DVDD voltage supply range The conversion accuracy of this IC may deteriorates depending on the voltage of DVDD and VRM. Use the IC within the following range. 2 × VRM – VRB – DVDD ≤ 0.3 V 10.The conversion accuracy of this IC deteriorates depending on the voltage of VRM. Use the IC within the following range. VRB ≥ – 0.3 V SDJ00021AEB 17 AN8150FB Usage Notes (continued) 11. Output voltage and load resistance This IC has been designed to drive an output load resistance of 50 Ω. When this IC is used with a resistance under 50 kΩ, the integral linearity error might be worse. In this case, raise the power supply voltage to prevent it. Determine the power supply voltage referring to the diagrams below. VCC – VOUTmax (V) VCC – VOUTmax output load resistance characteristics Output load resistance (kΩ) VOUTmin – VEE (V) VEE – VOUTmin output load resistance characteristics Output load resistance (kΩ) SDJ00021AEB 18 Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products, and no license is granted under any intellectual property right or other right owned by our company or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: – Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. – Any applications other than the standard applications intended. (4) The products and product specifications described in this book are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd.