INTEGRAL IN74HC273A

IN74HC273A
OCTAL D FLIP-FLOP WITH
COMMON CLOCK AND RESET
High-Performance Silicon-Gate CMOS
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The IN74HC273A is identical in pinout to the LS/ALS273. The
device inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LS/ALSTTL outputs.
This device consists of eight D flip-flops with common Clock
and Reset inputs. Each flip-flop is loaded with a low-to-high
transition of the Clock input. Reset is asynchronous and active
low.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 µA
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
IN74HC273AN Plastic
IN74HC273ADW SOIC
TA = -55° to 125° C for all
packages
PIN ASSIGNMENT
LOGIC DIAGRAM
PIN 20=VCC
PIN 10 = GND
FUNCTION TABLE
Reset
L
H
H
H
H
Inputs
Clock
X
L
X = don’t care
1
D
X
H
L
X
X
Output
Q
L
H
L
no change
no change
IN74HC273A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
VOUT
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
IIN
DC Input Current, per Pin
mA
±20
IOUT
DC Output Current, per Pin
mA
±35
ICC
DC Supply Current, VCC and GND Pins
mA
±75
PD
Power Dissipation in Still Air, Plastic DIP+
750
mW
SOIC Package+
500
Tstg
Storage Temperature
-65 to +150
°C
260
TL
Lead Temperature, 1 mm from Case for 10
°C
Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
DC Supply Voltage (Referenced to GND)
VIN, VOUT DC Input Voltage, Output Voltage (Referenced to
GND)
TA
Operating Temperature, All Package Types
t r, tf
Input Rise and Fall Time
(Figure VCC =2.0 V
1)
VCC =4.5 V
VCC =6.0 V
Min
2.0
0
Max
6.0
VCC
Unit
V
V
-55
0
0
0
+125
1000
500
400
°C
ns
This device contains protection circuitry to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage
higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and
VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or
VCC). Unused outputs must be left open.
2
IN74HC273A
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
Guaranteed Limit
VCC
Symbol Parameter
Test Conditions
V
≤85
≤125
25 °C
to
°C
°C
-55°C
1.5
1.5
VOUT=0.1 V or VCC-0.1 V 2.0
1.5
VIH
Minimum High3.15
3.15
3.15
Level Input
4.5
IOUT≤ 20 µA
4.2
4.2
4.2
Voltage
6.0
0.5
0.5
VOUT=0.1 V or VCC-0.1 V 2.0
0.5
VIL
Maximum Low 1.35
1.35
1.35
Level Input
4.5
IOUT ≤ 20 µA
1.8
1.8
1.8
Voltage
6.0
1.9
1.9
VIN=VIH or VIL
1.9
VOH
Minimum High2.0
4.4
4.4
4.4
Level Output
4.5
IOUT ≤ 20 µA
5.9
5.9
5.9
Voltage
6.0
VIN=VIH or VIL
3.7
3.84
3.98
4.5
IOUT ≤ 4.0 mA
5.2
5.34
5.48
6.0
IOUT ≤ 5.2 mA
0.1
0.1
VIN= VIL or VIH
0.1
VOL
Maximum Low2.0
0.1
0.1
0.1
Level Output
4.5
IOUT ≤ 20 µA
0.1
0.1
0.1
Voltage
6.0
VIN= VIL or VIH
0.4
0.33
0.26
4.5
IOUT ≤ 4.0 mA
0.4
0.33
0.26
6.0
IOUT ≤ 5.2 mA
IIN
Maximum Input
VIN=VCC or GND
6.0
±0.1
±1.0
±1.0
Leakage Current
VIN=VCC or GND
ICC
Maximum
6.0
4.0
40
160
Quiescent Supply IOUT=0µA
Current
(per Package)
3
Unit
V
V
V
V
µA
µA
IN74HC273A
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
VCC
Symbol
Parameter
V
25 °C ≤85°C ≤125
to
°C
-55°C
4.0
5.0
6.0
fmax
Maximum Clock Frequency (50% Duty 2.0
20
24
30
Cycle) (Figures 1 and 4)
4.5
24
28
35
6.0
220
180
145
tPLH,
Maximum Propagation Delay, Clock to Q 2.0
44
36
29
tPHL
(Figures 1 and 4)
4.5
38
31
25
6.0
220
180
145
tPHL
Maximum Propagation Delay , Reset to 2.0
44
36
29
Q (Figures 2 and 4)
4.5
38
31
25
6.0
110
95
75
tTLH, tTHL Maximum Output Transition Time, Any 2.0
22
19
15
Output (Figures 1 and 4)
4.5
19
16
13
6.0
CIN
Maximum Input Capacitance
10
10
10
Power Dissipation Capacitance (Per
Typical @25°C,VCC=5.0 V
Enabled Output)
CPD
Used to determine the no-load dynamic
48
power consumption: PD=CPDVCC2f+ICCVCC
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit
VCC
Symbol
Parameter
V
25 °C to≤85°C
≤125°C
55°C
90
75
60
tSU
Minimum Setup Time, 2.0
18
15
12
Data to Clock (Figure 3)
4.5
15
13
10
6.0
3.0
3.0
3.0
th
Minimum Hold Time, 2.0
3.0
3.0
3.0
Clock to Data (Figure 3)
4.5
3.0
3.0
3.0
6.0
5.0
5.0
5.0
trec
Minimum
Recovery 2.0
5.0
5.0
5.0
Time, Reset Inactive to 4.5
5.0
5.0
5.0
6.0
Clock (Figure 2)
90
75
60
tw
Minimum Pulse Width, 2.0
18
15
12
Clock (Figure 1)
4.5
15
13
10
6.0
90
75
60
tw
Minimum Pulse Width, 2.0
18
15
12
Reset (Figure 2)
4.5
15
13
10
6.0
1000
1000
1000
tr, tf
Maximum Input Rise and 2.0
500
500
500
Fall Times (Figure 1)
4.5
400
400
400
6.0
4
Unit
MHz
ns
ns
ns
pF
pF
Unit
ns
ns
ns
ns
ns
ns
IN74HC273A
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
5