TECHNICAL DATA IN74HC174A Hex D Flip-Flop with Common Clock and Reset High-Performance Silicon-Gate CMOS The IN74HC174A is identical in pinout to the LS/ALS174. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of six D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input. Reset is asynchronous and active-low. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION IN74HC174AN Plastic IN74HC174AD SOIC IZ74HC174A Chip TA = -55° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE Inputs PIN 16=VCC PIN 8 = GND Output Reset Clock D Q L X X L H H H H L L X no change X no change H L H X = Don’t care L = LOW voltage level H = HIGH voltage level INTEGRAL 1 IN74HC174A MAXIMUM RATINGS * Symbol Parameter Value Unit -0.5 to +7.0 V VCC DC Supply Voltage (Referenced to GND) VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin ±20 mA DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ 750 500 mW -65 to +150 °C 260 °C VOUT IIN IOUT Tstg Storage Temperature TL Lead Temperature, 1,5 mm from Case for 4 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, t f Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min Max Unit 2.0 6.0 V 0 VCC V -55 +125 °C 0 0 0 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. INTEGRAL 2 IN74HC174A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) VCC V -55°C to 25°C ≤85 °C ≤125 °C Unit VOUT≥ VCC-0.1 V or ≤0.1 V IOUT≤ 20 µA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V Maximum Low -Level Input Voltage VOUT≤0.1 V or ≥VCC-0.1 V IOUT ≤ 20 µA 2.0 4.5 6.0 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V Minimum High-Level Output Voltage VIN=VIH or VIL IOUT ≤ 20 µA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 VIN= VIL or VIH IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 Symbol Parameter VIH Minimum High-Level Input Voltage VIL VOH Test Conditions VIN=VIH or VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA VOL Guaranteed Limit Maximum Low-Level Output Voltage VIN= VIL or VIH IOUT ≤ 20 µA V IIN Maximum Input Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 6.0 4.0 40 160 µA INTEGRAL 3 IN74HC174A AC ELECTRICAL CHARACTERISTICS (CL=50pF, Input t r=t f=6.0 ns, VIL= 0 V, VIH=Vcc) VCC V -55°C to 25°C ≤85°C ≤125°C Unit Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) 2.0 4.5 6.0 6.0 30 35 4.8 24 28 4.0 20 24 MHz Maximum Propagation Delay, Clock to Q (Figures 1 and 4) 2.0 4.5 6.0 110 22 19 140 28 24 165 33 28 ns Maximum Propagation Delay , Reset to Q (Figures 2 and 4) 2.0 4.5 6.0 110 21 19 140 28 24 160 32 27 ns Maximum Output Transition Time, Any Output (Figures 1 and 4) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns - 10 10 10 pF Symbol fmax tPLH, t PHL tPHL tTLH, t THL CIN Parameter Maximum Input Capacitance Power Dissipation Capacitance (Per Enabled Output) CPD Guaranteed Limit Typical @25°C,VCC=5.0 V Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC 62 pF TIMING REQUIREMENTS (CL=50pF,Input t r=t f=6.0 ns, VIL= 0 V, VIH=Vcc) VCC Guaranteed Limit Symbol Parameter V -55 °C to 25°C ≤85°C ≤125°C Unit tSU Minimum Setup Time, Data to Clock (Figure 3) 2.0 4.5 6.0 50 10 9 65 13 11 75 15 13 ns th Minimum Hold Time, Clock to Data (Figure 3) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns trec Minimum Recovery Time, Reset Inactive to Clock (Figure 2) 2.0 4.5 6.0 5 5 5 5 5 5 5 5 5 ns tw Minimum Pulse Width, Clock (Figure 1) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns tw Minimum Pulse Width, Reset (Figure 2) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns tr, tf Maximum Input Rise and Fall Times (Figure 1) 2.0 4.5 6.0 1000 500 400 1000 500 400 1000 500 400 ns INTEGRAL 4 IN74HC174A tw tr CLOCK tf VCC 90% 50% 10% tPLH 50% 10% GND tPHL Q 1/fmax VCC 50% GND tw Q RESET 50% t PHL t rec 90% VCC CLOCK tTLH 50% Figure 1. Switching Waveforms Figure 2. Switching Waveforms TEST POINT VALID DATA VCC 50% GND t su CLOCK GND t THL th DEVICE UNDER TEST OUTPUT * CL VCC 50% GND Figure 3. Switching Waveforms Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM INTEGRAL 5 IN74HC174A CHIP PAD DIAGRAM Chip marking 15 14 13 12 11 10 1.3 + 0.03 09 16 08 01 02 03 04 05 06 07 1.6 + 0.03 Chip marking :15HC174 Location of marking (mm): left lower corner x = 0.110, y = 0.870; right lower corner x = 0.240, y = 0.900 Chip thickness: 0.46 ± 0.02 mm PAD LOCATION Pad No Symbol Location (left lower corner), mm X 01 Reset 0.115 02 Q0 0.115 03 D0 0.325 04 D1 0.580 05 Q1 0.850 06 D2 1.145 07 Q2 1.345 08 GND 1.370 09 Clock 1.365 10 Q3 1.355 11 D3 1.155 12 Q4 0.880 13 D4 0.620 14 D5 0.320 15 Q5 0.125 16 Vcc 0.115 Note: Location is given as per passivation layer INTEGRAL Y 0.340 0.140 0.115 0.115 0.115 0.115 0.140 0.355 0.815 1.045 1.065 1.065 1.065 1.065 1.045 0.660 Pad size, mm 0.12×0.12 0.12×0.12 0.12×0.12 0.12×0.12 0.12×0.12 0.12×0.12 0.12×0.12 0.12×0.16 0.12×0.12 0.12×0.12 0.12×0.12 0.12×0.12 0.12×0.12 0.12×0.12 0.12×0.12 0.12×0.19 6