INTEGRAL IN74LS06D

TECHNICAL DATA
IN74LS06
Hex Inverted Buffers with
Open-Collector Outputs
This device contains hex inverted buffers with open-collector. It
performs the Boolean function Y=A in positive Logic.
• High Output Voltage (30 V)
• High Speed ( tPD = 8.5 ns typical)
• Low Power Dissipation (PD = 18 mW per Gate)
ORDERING INFORMATION
IN74LS06N Plastic
IN74LS06D SOIC
TA = 0° to 70° C for all
packages
LOGIC DIAGRAM
PIN ASSIGNMENT
A1
A2
A3
A4
A5
A6
1
2
3
4
5
6
9
8
11
10
13
12
PIN 14 =VCC
PIN 7 = GND
Y1
Y2
Y3
Y4
Y5
Y6
FUNCTION TABLE
Inputs
Output
A
Y
H
L
L
H
1
IN74LS06
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
Supply Voltage
7.0
V
VIN
Input Voltage
5.5
V
VOUT
Output Voltage
30
V
Tstg
Storage Temperature Range
-65 to +150
°C
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
5.25
V
VCC
Supply Voltage
4.75
VIH
High Level Input Voltage
2.0
VIL
Low Level Input Voltage
0.8
V
VOH
High Level Output Voltage
30
V
IOL
Low Level Output Current
40
mA
TA
Ambient Temperature Range
+70
°C
0
V
DC ELECTRICAL CHARACTERISTICS over full operating conditions
Guaranteed Limit
Symbol
Test Conditions
Min
Max
Unit
VIK
Input Clamp Voltage
VCC = min, IIN = -18 mA
-1.5
V
IOH
High Level Output Current
VCC = min, VOH= max
250
µA
VOL
Low Level Output Voltage
VCC = min, IOL = 16 mA
0.4
V
VCC = min, IOL = 40 mA
0.7
VCC = max, VIN = 2.7 V
20
µA
VCC = max, VIN = 5.5 V
1
mA
IIH
2
Parameter
High Level Input Current
IIL
Low Level Input Current
VCC = max, VIN = 0.4 V
-0.2
mA
ICC
Supply Current
VCC = max
Total with
outputs high
18
mA
Total with
outputs low
60
IN74LS06
AC ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC = 5.0 V, CL = 15 pF,
RL = 110 Ω, tr = 15 ns, tf = 6.0 ns)
Symbol
Parameter
Min
Max
Unit
tPLH
Propagation Delay, Input A to Output Y
15
ns
tPHL
Propagation Delay, Input A to Output Y
20
ns
Figure 1. Switching Waveforms
NOTE A. CL includes probe and jig capacitance.
Figure 2. Test Circuit
3