TI TPS2100D

TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197C – JUNE 1999 – REVISED APRIL 2000
features
D
D
D
D
D
D
D
D
D
D
typical applications
Dual-Input, Single-Output MOSFET Switch
With No Reverse Current Flow (No Parasitic
Diodes)
IN1 . . . 250-mΩ, 500-mA N-Channel;
16-µA Max Supply Current
IN2 . . . 1.3-Ω, 10-mA P-Channel;
1.5-µA Max Supply Current (VAUX Mode)
Advanced Switch Control Logic
CMOS- and TTL-Compatible Enable Input
Controlled Rise, Fall, and Transition Times
2.7-V to 4 V Operating Range
SOT-23-5 and SOIC-8 Package
– 40°C to 70°C Ambient Temperature Range
2-kV Human-Body-Model, 750-V CDM,
200-V Machine-Model ElectrostaticDischarge Protection
D
D
Notebook and Desktop PCs
Palmtops and PDAs
TPS2100
IN1
3.3 V VCC
3.3 V
IN2
3.3 V VAUX
EN
D3 or PME Status
Control Signal
Controller
(CardBus,
1394,
PCI,
et al.)
Hold-Up
Capacitor
Figure 1. Typical Dual-Input Single-Output
Application
description
The TPS2100 and TPS2101 are dual-input, single-output power switches designed to provide uninterrupted
output voltage when transitioning between two independent power supplies. Both devices combine one
n-channel (250 mΩ) and one p-channel (1.3 Ω) MOSFET with a single output. The p-channel MOSFET (IN2)
is used with auxiliary power supplies that deliver lower current for standby modes. The n-channel MOSFET
(IN1) is used with a main power supply that delivers higher current required for normal operation. Low
on-resistance makes the n-channel the ideal path for higher main supply current when power-supply regulation
and system voltage drops are critical. When using the p-channel MOSFET, quiescent current is reduced to
0.75 µA to decrease the demand on the standby power supply. The MOSFETs in the TPS2100 and TPS2101
do not have the parasitic diodes, found in discrete MOSFETs, which allow the devices to prevent back-flow
current when the switch is off.
TPS2100
D PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
PCI Bus
VAUX
VGA
3.3 V
EN
GND
1
IN2
3
5
IN1
2
4
OUT
TPS210x
VCC
IN2
GND
EN
NC
1
8
2
7
3
6
4
5
OUT
OUT
NC
IN1
TPS2101
D3-STAT
D PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
PCI12xx / PCI14xx
CardBus Controller
Figure 2. VAUX CardBus Implementation
EN
GND
1
IN2
3
5
IN1
2
4
OUT
IN2
GND
EN
NC
1
8
2
7
3
6
4
5
OUT
OUT
NC
IN1
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197C – JUNE 1999 – REVISED APRIL 2000
AVAILABLE OPTIONS
PACKAGED DEVICES
TJ
– 40°C to 85°C
DEVICE
ENABLE
SOT-23-5
(DBV)†
SOIC-8
(D)
TPS2100
EN
TPS2100D
TPS2101
EN
TSP2100DBV†
TPS2101DBV†
TPS2101D
Both packages are available left-end taped and reeled. Add an R suffix to the D device type
(e.g., TPS2101DR).
† Add T (e.g., TPS2100DBVT) to indicate tape and reel at order quantity of 250 parts.
Add R (e.g., TPS2100DBVR) to indicate tape and reel at order quantity of 3000 parts.
TPS2100 functional block diagram
SW1
250 mΩ
IN1
OUT
Charge
Pump
Pullup
Circuit
VCC
Select
EN
IN2
Discharge
Circuit
Driver
SW2
1.3 Ω
GND
Driver
TPS2101 functional block diagram
SW1
250 mΩ
IN1
OUT
Charge
Pump
VCC
Select
EN
IN2
Pulldown
Circuit
Driver
SW2
1.3 Ω
GND
Driver
2
Discharge
Circuit
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197C – JUNE 1999 – REVISED APRIL 2000
Function Tables
TPS2100
VIN1
TPS2101
VIN2
EN
OUT
VIN1
VIN2
EN
OUT
0V
0V
XX
GND
0V
3.3 V
L
GND
0V
0V
XX
GND
0V
3.3 V
H
3.3 V
3.3 V
L
GND
VIN1
3.3 V
3.3 V
H
3.3 V
0V
VIN1
L
VIN1
3.3 V
0V
H
0V
VIN1
3.3 V
H
VIN2
0V
3.3 V
L
VIN2
3.3 V
0V
H
VIN2
3.3 V
0V
L
VIN2
3.3 V
3.3 V
H
VIN2
3.3 V
3.3 V
L
VIN2
XX = don’t care
Terminal Functions
TERMINAL
NO.
NAME
TPS2100
DBV
D
EN
DESCRIPTION
I/O
TPS2101
DBV
D
1
3
Active-high enable for IN1-OUT switch
EN
1
3
I
Active-low enable for IN1-OUT switch
GND
2
2
2
2
I
Ground
IN1
5
5
5
5
I
Main Input voltage, NMOS drain (250 mΩ)
IN2
3
1
3
1
I
Auxilliary input voltage, PMOS drain (1.3 Ω)
OUT
4
7, 8
4
7, 8
O
Power switch output
NC
4, 6
4, 6
No connection
detailed description
power switches
n-channel MOSFET
The IN1-OUT n-channel MOSFET power switch has a typical on-resistance of 250 mΩ at 3.3-V input voltage,
and is configured as a high-side switch.
p-channel MOSFET
The IN2-OUT p-channel MOSFET power switch with typical on-resistance of 1.3 Ω at 3.3-V input voltage and
is configured as a high-side switch. When operating, the p-channel MOSFET quiescent current is reduced to
less than 1.5 µA.
charge pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
driver
The driver controls the gate voltage of the IN1-OUT and IN2-OUT power switches. To limit large current surges
and reduce the associated electromagnetic interference (EMI) produced, the drivers incorporate circuitry that
controls the rise times and fall times of the output voltage.
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3
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197C – JUNE 1999 – REVISED APRIL 2000
detailed description (continued)
enable
The logic enable will turn on the IN2-OUT power switch when a logic high is present on EN (TPS2100) or logic
low is present on EN (TPS2101). A logic low input on EN (TPS2100) or logic high on EN (TPS2101) restores
bias to the drive and control circuits and turns on the IN1-OUT power switch. The enable input is compatible
with both TTL and CMOS logic levels.
the VAUX application for CardBus controllers
The PC Card specification requires the support of VAUX to the CardBus controller as well as to the PC Card
sockets. Both are 3.3-V requirements; however the CardBus controller’s current demand from the VAUX supply
is limited to 10 µA, whereas the PC Card may consume as much as 200 mA. In either implementation, if support
of a wake-up event is required, the controller and the socket will transition from the 3.3-V VCC rail to the 3.3-V
VAUX rail when the equipment moves into a low power mode such as D3. The transition from VCC to VAUX needs
to be seamless in order to maintain all memory and register information in the system. If VAUX is not supported,
the system will lose all register information when it transitions to the D3 state.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Input voltage range, VI(IN1) (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 5 V
Input voltage range, VI(IN2) (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 5 V
Input voltage range, VI at EN or EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 5 V
Continuous output current, IO(IN1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700 mA
Continuous output current, IO(IN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See dissipation rating table
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
Electrostatic discharge (ESD) protection: Human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
Machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 V
Charged device model (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . 750 V
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE
TA < 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DBV
309 mW
3.1 mW/°C
170 mW
123 mW
D
568 mW
5.7 mW/°C
313 mW
227 mW
recommended operating conditions
Input voltage, VI(INx)
Input voltage, VI at EN and EN
Continuous output current, IO(IN1)
MIN
MAX
2.7
4
V
0
4
V
500
100‡
Continuous output current, IO(IN2)
UNIT
mA
mA
Operating virtual junction temperature, TJ
– 40
85
°C
‡ The device can deliver up to 220 mA at IO(IN2). However, operation at the higher current levels will result in greater voltage drop across the device,
and greater voltage droop when switching between IN1 and IN2.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197C – JUNE 1999 – REVISED APRIL 2000
electrical characteristics over recommended operating junction temperature range,
VI(IN1) = V(IN2) = 3.3 V, IO = rated current (unless otherwise noted)
power switch
TEST
CONDITIONS†
PARAMETER
rDS(on)
DS( )
MIN
TYP
IN1 OUT
IN1-OUT
TJ = 25°C
TJ = 85°C
250
IN2 OUT
IN2-OUT
TJ = 25°C
TJ = 85°C
1.3
On state resistance
On-state
300
1.5
MAX
375
2.1
UNIT
mΩ
Ω
† Pulse-testing techniques maintain junction temperature close to ambient termperature; thermal effects must be taken into account separately.
enable input (EN and EN)
PARAMETER
VIH
VIL
II
TEST CONDITIONS
High-level input voltage
2.7 V ≤ VI(INx) ≤ 4 V
Low-level input voltage
2.7 V ≤ VI(INx) ≤ 4 V
Input current
MIN
TYP
MAX
2
UNIT
V
0.8
V
TPS2100
EN = 0 V or EN = VI(INx)
–0.5
0.5
µA
TPS2101
EN = 0 V or EN = VI(INx)
–0.5
0.5
µA
supply current
PARAMETER
TEST CONDITIONS
TYP
EN = H,
IN2 selected
TJ = 25°C
–40°C ≤ TJ ≤ 85°C
0.75
EN = L,
IN1 selected
TJ = 25°C
–40°C ≤ TJ ≤ 85°C
10
EN = L,,
IN2 selected
TJ = 25°C
–40°C ≤ TJ ≤ 85°C
0.75
EN = H,,
IN1 selected
TJ = 25°C
–40°C ≤ TJ ≤ 85°C
10
TPS2100
II
MIN
Supply current
TPS2101
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MAX
1.5
16
1.5
16
UNIT
µA
µA
µA
µA
5
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197C – JUNE 1999 – REVISED APRIL 2000
switching characteristics, TJ = 25°C, VI(IN1) = VI(IN2) = 3.3 V (unless otherwise noted)†
TEST CONDITIONS†
PARAMETER
CL = 1 µF,
IN1-OUT
tr
VI(IN2)
(
)=0
CL = 10 µF,
CL = 1 µF,
Output rise time
CL = 1 µF,
IN2-OUT
VI(IN1)
(
)=0
CL = 10 µF,
CL = 1 µF,
CL = 1 µF,
IN1-OUT
tf
VI(IN2)
(
)=0
CL = 10 µF,
CL = 1 µF,
Output fall time
CL = 1 µF,
IN2-OUT
tPLH
Propagation delay time,
time low-to-high
low to high output
tPHL
time high-to-low
high to low output
Propagation delay time,
IN1-OUT
IN2-OUT
IN1-OUT
IN2-OUT
VI(IN1)
(
)=0
CL = 10 µF,
6
IL = 10 mA
IL = 10 mA
640
IL = 500 mA
IL = 500 mA
93
VI(IN2) = 0
VI(IN1) = 0
CL = 10 µF
µF,
IL = 10 mA
VI(IN2) = 0
VI(IN1) = 0
CL = 10 µF
µF,
IL = 10 mA
• DALLAS, TEXAS 75265
5.5
5.5
IL = 10 mA
IL = 10 mA
MAX
UNIT
840
IL = 10 mA
IL = 1 mA
IL = 10 mA
IL = 1 mA
POST OFFICE BOX 655303
TYP
830
CL = 1 µF,
† All timing parameters refer to Figure 3.
MIN
IL = 500 mA
IL = 500 mA
µs
70
8
23
690
µs
6900
6900
75
2
3
370
µs
µs
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197C – JUNE 1999 – REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
OUT
IO
CL
LOAD CIRCUIT
50%
EN or EN
50%
EN or EN
tPHL
VI
tPLH
VI
90%
VO
GND
GND
VO
10%
Propagation Delay Time, Low-to-High-Level Output
Propagation Delay Time, High-to–Low-Level Output
tr
tf
VI
90%
VO
10%
GND
Rise/Fall Time
50%
EN or EN
50%
EN or EN
ton
toff
VI
VI
90%
VO
VO
GND
GND
10%
Turn-off Transition Time
Turn-on Transition Time
WAVEFORMS
Figure 3. Test Circuit and Voltage Waveforms
Table of Timing Diagrams†
FIGURE
Propagation Delay and Rise Time With 0.1-µF Load, IN1
4
Propagation Delay and Rise Time With 0.1-µF Load, IN2
5
Propagation Delay and Fall Time With 0.1-µF Load, IN1
6
Propagation Delay and Fall Time With 0.1-µF Load, IN2
7
Propagation Delay and Rise Time With 1-µF Load, IN1
8
Propagation Delay and Rise Time With 1-µF Load, IN2
9
Propagation Delay and Fall Time With 1-µF Load, IN1
10
Propagation Delay and Fall Time With 1-µF Load, IN2
† Waveforms shown in Figures 4–11 refer to TPS2100 at TJ = 25°C
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• DALLAS, TEXAS 75265
11
7
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197C – JUNE 1999 – REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
VI(IN1) = 3.3 V
VI(IN2) = 0 V
CL = 0.1 µF
RL = 330 Ω
EN
(2 V/div)
EN
(2 V/div)
VO
(2 V/div)
VO
(2 V/div)
t – Time – 1 µs/div
t – Time – 250 µs/div
Figure 4. Propagation Delay and Rise Time
With 0.1-µF Load, IN1
EN
(2 V/div)
VI(IN1) = 3.3 V
VI(IN2) = 0 V
CL = 0.1 µF
RL = 330 Ω
Figure 5. Propagation Delay and Fall Time
With 0.1-µF Load, IN2
VI(IN1) = 0 V
VI(IN2) = 3.3 V
CL = 0.1 µF
RL = 330 Ω
EN
(2 V/div)
VO
(2 V/div)
VO
(2 V/div)
t – Time – 50 µs/div
t – Time – 5 µs/div
Figure 6. Propagation Delay and Fall Time
With 0.1-µF Load, IN1
8
VI(IN1) = 0 V
VI(IN2) = 3.3 V
CL = 0.1 µF
RL = 330 Ω
POST OFFICE BOX 655303
Figure 7. Propagation Delay and Fall Time
With 0.1-µF Load, IN2
• DALLAS, TEXAS 75265
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197C – JUNE 1999 – REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
VI(IN1) = 3.3 V
VI(IN2) = 0 V
CL = 1 µF
RL = 330 Ω
EN
(2 V/div)
EN
(2 V/div)
VO
(2 V/div)
VO
(2 V/div)
t – Time – 2.5 µs/div
t – Time – 250 µs/div
Figure 8. Propagation Delay and Rise Time
With 1-µF Load, IN1
EN
(2 V/div)
VI(IN1) = 0 V
VI(IN2) = 3.3 V
CL = 1 µF
RL = 330 Ω
VI(IN1) = 3.3 V
VI(IN2) = 0 V
CL = 1 µF
RL = 330 Ω
Figure 9. Propagation Delay and Rise Time
With 1-µF Load, IN2
VI(IN1) = 0 V
VI(IN2) = 3.3 V
CL = 1 µF
RL = 330 Ω
EN
(2 V/div)
VO
(2 V/div)
VO
(2 V/div)
t – Time – 250 µs/div
t – Time – 10 µs/div
Figure 10. Propagation Delay and Fall Time
With 1-µF Load, IN1
POST OFFICE BOX 655303
Figure 11. Propagation Delay and Fall Time
With 1-µF Load, IN2
• DALLAS, TEXAS 75265
9
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197C – JUNE 1999 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
IN1 Switch Rise Time
vs Output Current
12
IN2 Switch Fall Time
vs Output Current
13
IN1 Switch Fall Time
vs Output Current
14
IN2 Switch Fall Time
vs Output Current
15
Output Voltage Droop
vs Output Current When Output Is Switched From IN2 to IN1
16
Inrush Current
vs Output Capacitance
17
IN1 Supply Current
vs Junction Temperature (IN1 Enabled)
18
IN1 Supply Current
vs Junction Temperature (IN1 Disabled)
19
IN2 Supply Current
vs Junction Temperature (IN2 Enabled)
20
IN2 Supply Current
vs Junction Temperature (IN2 Disabled)
21
IN1-OUT On-State Resistance
vs Junction Temperature
22
IN2-OUT On-State Resistance
vs Junction Temperature
23
IN1 SWTICH RISE TIME
vs
OUTPUT CURRENT
IN2 SWTICH RISE TIME
vs
OUTPUT CURRENT
900
t r – Rise Time – µ s
800
CL = 47 µF
100
CL = 47 µF
750
700
CL = 10 µF
650
600
550
500
0.01
CL = 100 µF
CL = 100 µF
t r – Rise Time – µ s
850
1000
VI(IN1) = 3.3 V
VI(IN2) = 0 V
TJ = 25°C
0.1
100
1
10
IO – Output Current – mA
10
CL = 1 µF
1
CL = 1 µF
CL = 0.1 µF
CL = 10 µF
CL = 0.1 µF
1000
0.1
0
1
Figure 12
10
2
7
8
3
4
5
6
IO – Output Current – mA
Figure 13
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VI(IN1) = 0 V
VI(IN2) = 3.3 V
TJ = 25°C
9
10
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197C – JUNE 1999 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS
IN1 SWITCH FALL TIME
vs
OUTPUT CURRENT
10000
CL = 47 µF
CL = 10 µF
100
CL = 100 µF
CL = 100 µF
t f – Output Fall Time – ms
t f – Fall Time – µ s
1000
VI(IN1) = 3.3 V
VI(IN2) = 0 V
TJ = 25°C
1000
IN2 SWITCH FALL TIME
vs
OUTPUT CURRENT
CL = 1 µF
10
100
CL = 10 µF
CL = 1 µF
10
CL = 0.1 µF
1
VI(IN1) = 0 V
VI(IN2) = 3.3 V
TJ = 25°C
CL = 0.1 µF
1
0.01
0.1
100
1
10
IO – Output Current – mA
0.1
0.01
1000
Figure 14
1.6
CL = 0.1 µF
CL = 1 µF
VI(IN1) = 3.3 V
VI(IN2) = 0 V
RL = 6.6 Ω
TJ = 25°C
1.4
0.8
1.2
CL = 10 µF
0.6
CL = 47 µF
0.4
10
INRUSH CURRENT
vs
OUTPUT CAPACITANCE
Inrush Current – A
VO– Output Voltage Droop – V
VI(IN1) = 3.3 V
VI(IN2) = 3.3 V
TJ = 25°C
1
0.1
IO – Output Current – mA
Figure 15
OUTPUT VOLTAGE DROOP
vs
OUTPUT CURRENT WHEN OUTPUT
IS SWITCHED FROM IN2 TO IN1
1
CL = 47 µF
CL = 100 µF
1
0.8
0.6
0.4
0.2
0.2
0
0.01
0
0.1
1
IO – Output Current – mA
10
0
Figure 16
400
100
200
300
Co – Output Capacitance – µF
500
Figure 17
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• DALLAS, TEXAS 75265
11
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197C – JUNE 1999 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS
IN1 SUPPLY CURRENT
vs
JUNCTION TEMPERATURE (IN1 DISABLED)
IN1 SUPPLY CURRENT
vs
JUNCTION TEMPERATURE (IN1 ENABLED)
0.25
0.23
VI(INx) = 4 V
I CC – Supply Currenmt – µ A
I CC – Supply Currenmt – µ A
14
12
VI(INx) = 3.3 V
10
VI(INx) = 2.7 V
8
VI(INx) = 4 V
0.21
VI(INx) = 3.3 V
0.19
VI(INx) = 2.7 V
0.17
6
–40
–20
60
80
0
20
40
TJ Junction Temperature – °C
0.15
–40
100
–20
Figure 18
100
Figure 19
IN2 SUPPLY CURRENT
vs
JUNCTION TEMPERATURE (IN2 ENABLED)
IN2 SUPPLY CURRENT
vs
JUNCTION TEMPERATURE (IN2 DISABLED)
0.75
0.6
0.7
0.56
I CC – Supply Currenmt – µ A
I CC – Supply Currenmt – µ A
60
80
0
20
40
TJ Junction Temperature – °C
VI(INx) = 4 V
0.65
VI(INx) = 3.3 V
0.6
VI(INx) = 2.7 V
0.55
0.52
VI(INx) = 4 V
0.48
VI(INx) = 3.3 V
0.44
VI(INx) = 2.7 V
0.5
–40
–20
0
20
40
60
80
TJ Junction Temperature – °C
100
0.4
–40
Figure 20
12
–20
60
80
0
20
40
TJ Junction Temperature – °C
Figure 21
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100
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197C – JUNE 1999 – REVISED APRIL 2000
TYPICAL CHARACTERISTICS
IN2-OUT ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
IN1-OUT ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
2
r on – IN1-OUT On-State resistance – Ω
r on – IN1-OUT On-State resistance – m Ω
305
280
255
VI(INx) = 2.7 V
230
VI(INx) = 3.3 V
205
1.75
VI(INx) = 2.7 V
1.5
VI(INx) = 3.3 V
1.25
VI(INx) = 4 V
1
0.75
VI(INx) = 4 V
180
–40
–20
60
80
0
20
40
TJ Junction Temperature – °C
0.5
–40
100
–20
0
20
40
60
80
100
TJ Junction Temperature – °C
Figure 22
Figure 23
APPLICATION INFORMATION
TPS2100
CardBus or System Controller
0.1 µF
EN
3.3 V VCC
IN1
3.3 V VAUX
IN2
3.3 V
OUT
0.1 µF
xx µF
GND
0.1 µF
Figure 24. Typical Application
power supply considerations
A 0.01-µF to 0.1-µF ceramic bypass capacitor between IN and GND, close to the device is recommended. The
output capacitor should be chosen based on the size of the load during the transition of the switch. A 47-µF
capacitor is recommended for 10-mA loads. Typical output capacitors (xx µF, shown in Figure 24) required for
a given load can be determined from Figure 16 which shows the output voltage droop when output is switched
from IN2 to IN1. The output voltage droop is insignificant when output is switched from IN1 to IN2. Additionally,
bypassing the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to
short-circuit transients.
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TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197C – JUNE 1999 – REVISED APRIL 2000
APPLICATION INFORMATION
power supply considerations (continued)
switch transition
The n-channel MOSFET on IN1 uses a charge-pump to create the gate-drive voltage, which gives the IN1 switch
a rise time of approximately 1 ms. The p-channel MOSFET on IN2 has a simpler drive circuit that allows a rise
time of approximately 8 µs. Because the device has two switches and a single enable pin, these rise times are
seen as transition times, from IN1 to IN2, or IN2 to IN1, by the output. The controlled transition times help limit
the surge currents seen by the power supply during switching.
thermal protection
Thermal protection provided on the IN1 switch prevents damage to the IC when heavy-overload or short-circuit
faults are present for extended periods of time. The increased dissipation causes the junction temperature to
rise to dangerously high levels. The protection circuit senses the junction temperature of the switch and shuts
it off at approximately 125°C (TJ). The switch remains off until the junction temperature has dropped. The switch
continues to cycle in this manner until the load fault or input power is removed.
undervoltage lockout
An undervoltage lockout function is provided to ensure that the power switch is in the off state at power-up.
Whenever the input voltage falls below approximately 2 V, the power switch quickly turns off. This function
facilitates the design of hot-insertion systems that may not have the capability to turn off the power switch before
input power is removed. Upon reinsertion, the power switch will be turned on with a controlled rise time to reduce
EMI and voltage overshoots.
power dissipation and junction temperature
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to that of power packages; it is
good design practice to check power dissipation and junction temperature. First, find ron at the input voltage,
and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and
read ron from Figure 22 or Figure 23. Next calculate the power dissipation using:
P
D
+ ron
I2
Finally, calculate the junction temperature:
T
J
+ PD
R
qJA
) TA
Where:
TA = Ambient temperature
RθJA = Thermal resistance
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation using the calculated value as the new estimate. Two or three iterations are generally
sufficient to obtain a reasonable answer.
ESD protection
All TPS2100 and TPS2101 terminals incorporate ESD-protection circuitry designed to withstand a 2-kV
human-body-model discharge as defined in MIL-STD-883C.
14
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TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197C – JUNE 1999 – REVISED APRIL 2000
MECHANICAL DATA
DBV (R-PDSO-G5)
PLASTIC SMALL-OUTLINE
0,50
0,30
0,95
5
0,20 M
4
1,70
1,50
1
0,15 NOM
3,00
2,60
3
Gage Plane
3,00
2,80
0,25
0°–8°
0,55
0,35
Seating Plane
1,45
0,95
0,05 MIN
0,10
4073253-4/E 05/99
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-178
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TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197C – JUNE 1999 – REVISED APRIL 2000
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
14
0.010 (0,25) M
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047 / D 10/96
NOTES: A.
B.
C.
D.
16
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
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