80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR • Two Instructions/Clock Sustained Execution • Four 59 Mbytes/s DMA Channels with Data Chaining • Demultiplexed 32-bit Burst Bus with Pipelining ■ 32-bit Parallel Architecture ■ ■ ■ ■ — Two Instructions/clock Execution — Load/Store Architecture — Sixteen 32-bit Global Registers — Sixteen 32-bit Local Registers — Manipulates 64-bit Bit Fields — 11 Addressing Modes — Full Parallel Fault Model — Supervisor Protection Model Fast Procedure Call/Return Model — Full Procedure Call in 4 Clocks On-Chip Register Cache — Caches Registers on Call/Ret — Minimum of 6 Frames Provided — Up to 15 Programmable Frames On-Chip Instruction Cache — 1 Kbyte Two-Way Set Associative — 128-bit Path to Instruction Sequencer — Cache-Lock Modes — Cache-Off Mode High Bandwidth On-Chip Data RAM — 1 Kbyte On-Chip Data RAM — Sustains 128 bits per Clock Access ■ Four On-Chip DMA Channels — 59 Mbytes/s Fly-by Transfers — 32 Mbytes/s Two-Cycle Transfers — Data Chaining — Data Packing/Unpacking — Programmable Priority Method ■ 32-Bit Demultiplexed Burst Bus — 128-bit Internal Data Paths to and from Registers — Burst Bus for DRAM Interfacing — Address Pipelining Option — Fully Programmable Wait States — Supports 8-, 16- or 32-bit Bus Widths — Supports Unaligned Accesses — Supervisor Protection Pin ■ Selectable Big or Little Endian Byte Ordering ■ High-Speed Interrupt Controller — — — — — — Up to 248 External Interrupts 32 Fully Programmable Priorities Multi-mode 8-bit Interrupt Port Four Internal DMA Interrupts Separate, Non-maskable Interrupt Pin Context Switch in 750 ns Typical Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel. © INTEL CORPORATION, 1993 November 1993 Order Number: 270727-006 80960CA-33, -25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR CONTENTS PAGE 1.0 PURPOSE .................................................................................................................................................. 1 2.0 80960CA OVERVIEW................................................................................................................................. 1 2.1 The C-Series Core ..............................................................................................................................2 2.2 Pipelined, Burst Bus ...........................................................................................................................2 2.3 Flexible DMA Controller ......................................................................................................................2 2.4 Priority Interrupt Controller ..................................................................................................................2 2.5 Instruction Set Summary ....................................................................................................................3 3.0 PACKAGE INFORMATION.........................................................................................................................4 3.1 Package Introduction ..........................................................................................................................4 3.2 Pin Descriptions .................................................................................................................................. 4 3.3 80960CA Mechanical Data ............................................................................................................... 11 3.3.1 80960CA PGA Pinout ............................................................................................................ 11 3.3.2 80960CA PQFP Pinout .......................................................................................................... 15 3.4 Package Thermal Specifications ...................................................................................................... 18 3.5 Stepping Register Information .......................................................................................................... 20 3.6 Suggested Sources for 80960CA Accessories.................................................................................. 20 4.0 ELECTRICAL SPECIFICATIONS............................................................................................................. 21 4.1 Absolute Maximum Ratings .............................................................................................................. 21 4.2 Operating Conditions ........................................................................................................................ 21 4.3 Recommended Connections ............................................................................................................ 21 4.4 DC Specifications ............................................................................................................................. 22 4.5 AC Specifications .............................................................................................................................. 23 4.5.1 AC Test Conditions ................................................................................................................ 29 4.5.2 AC Timing Waveforms ........................................................................................................... 29 4.5.3 Derating Curves ..................................................................................................................... 33 5.0 RESET, BACKOFF AND HOLD ACKNOWLEDGE ................................................................................. 35 6.0 BUS WAVEFORMS ................................................................................................................................. 36 7.0 REVISION HISTORY ................................................................................................................................ 64 ii CONTENTS PAGE LIST OF FIGURES Figure 1 80960CA Block Diagram .............................................................................................................. 1 Figure 2 80960CA PGA Pinout—View from Top (Pins Facing Down) ...................................................... 13 Figure 3 80960CA PGA Pinout —View from Bottom (Pins Facing Up) .................................................... 14 Figure 4 80960CA PQFP Pinout (View from Top Side) ............................................................................ 17 Figure 5 Measuring 80960CA PGA and PQFP Case Temperature .......................................................... 18 Figure 6 Register g0 ................................................................................................................................. 20 Figure 7 AC Test Load .............................................................................................................................. 29 Figure 8 Input and Output Clocks Waveform ............................................................................................ 29 Figure 9 CLKIN Waveform ........................................................................................................................ 29 Figure 10 Output Delay and Float Waveform ............................................................................................. 30 Figure 11 Input Setup and Hold Waveform ................................................................................................ 30 Figure 12 NMI, XINT7:0 Input Setup and Hold Waveform .......................................................................... 31 Figure 13 Hold Acknowledge Timings ........................................................................................................ 31 Figure 14 Bus Backoff (BOFF) Timings ...................................................................................................... 32 Figure 15 Relative Timings Waveforms ...................................................................................................... 33 Figure 16 Output Delay or Hold vs. Load Capacitance .............................................................................. 33 Figure 17 Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC .................. 34 Figure 18 ICC vs. Frequency and Temperature ........................................................................................... 34 Figure 19 Cold Reset Waveform ................................................................................................................ 36 Figure 20 Warm Reset Waveform .............................................................................................................. 37 Figure 21 Entering the ONCE State ........................................................................................................... 38 Figure 22 Clock Synchronization in the 2-x Clock Mode ............................................................................ 39 Figure 23 Clock Synchronization in the 1-x Clock Mode ............................................................................ 39 Figure 24 Non-Burst, Non-Pipelined Requests Without Wait States .......................................................... 40 Figure 25 Non-Burst, Non-Pipelined Read Request With Wait States ....................................................... 41 Figure 26 Non-Burst, Non-Pipelined Write Request With Wait States ....................................................... 42 Figure 27 Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus ........................................ 43 Figure 28 Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus ............................................. 44 Figure 29 Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus ....................................... 45 Figure 30 Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus ............................................. 46 Figure 31 Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus ............................................ 47 Figure 32 Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus ............................................... 48 Figure 33 Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ....................................... 49 Figure 34 Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus ............................................ 50 Figure 35 Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ............................................... 51 Figure 36 Burst, Pipelined Read Request With Wait States, 32-Bit Bus ..................................................... 52 Figure 37 Burst, Pipelined Read Request With Wait States, 16-Bit Bus ..................................................... 53 Figure 38 Burst, Pipelined Read Request With Wait States, 8-Bit Bus ....................................................... 54 iii CONTENTS PAGE LIST OF FIGURES (continued) Figure 39 Using External READY ............................................................................................................... 55 Figure 40 Terminating a Burst with BTERM ............................................................................................... 56 Figure 41 BOFF Functional Timing ............................................................................................................ 57 Figure 42 HOLD Functional Timing ............................................................................................................ 58 Figure 43 DREQ and DACK Functional Timing .......................................................................................... 59 Figure 44 EOP Functional Timing .............................................................................................................. 59 Figure 45 Terminal Count Functional Timing .............................................................................................. 60 Figure 46 FAIL Functional Timing ............................................................................................................... 60 Figure 47 A Summary of Aligned and Unaligned Transfers for Little Endian Regions ................................ 61 Figure 48 A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued) ............ 62 Figure 49 Idle Bus Operation ...................................................................................................................... 63 LIST OF TABLES Table 1 80960CA Instruction Set .............................................................................................................. 3 Table 2 Pin Description Nomenclature ...................................................................................................... 4 Table 3 80960CA Pin Description — External Bus Signals ...................................................................... 5 Table 4 80960CA Pin Description — Processor Control Signals .............................................................. 8 Table 5 80960CA Pin Description — DMA and Interrupt Unit Control Signals ....................................... 10 Table 6 80960CA PGA Pinout — In Signal Order ................................................................................... 11 Table 7 80960CA PGA Pinout — In Pin Order ........................................................................................ 12 Table 8 80960CA PQFP Pinout — In Signal Order ................................................................................. 15 Table 9 80960CA PQFP Pinout — In Pin Order ..................................................................................... 16 Table 10 Maximum TA at Various Airflows in oC (PGA Package Only) ..................................................... 18 Table 11 80960CA PGA Package Thermal Characteristics ...................................................................... 19 Table 12 80960CA PQFP Package Thermal Characteristics .................................................................... 19 Table 13 Die Stepping Cross Reference ................................................................................................... 20 Table 14 Operating Conditions (80960CA-33, -25, -16) ............................................................................ 21 Table 15 DC Characteristics ..................................................................................................................... 22 Table 16 80960CA AC Characteristics (33 MHz) ...................................................................................... 23 Table 17 80960CA AC Characteristics (25 MHz) ...................................................................................... 25 Table 18 80960CA AC Characteristics (16 MHz) ...................................................................................... 27 Table 19 Reset Conditions ........................................................................................................................ 35 Table 20 Hold Acknowledge and Backoff Conditions ................................................................................ 35 iv 80960CA-33, -25, -16 1.0 PURPOSE This document provides electrical characteristics for the 33, 25 and 16 MHz versions of the 80960CA. For a detailed description of any 80960CA functional topic—other than parametric performance—consult the 80960CA Product Overview (Order No. 270669) or the i960 CA Microprocessor User’s Manual (Order No. 270710). To obtain data sheet updates and errata, please call Intel’s FaxBACK data-ondemand system (1-800-628-2283 or 916-356-3105). Other information can be obtained from Intel’s technical BBS (916-356-3600). 2.0 80960CA OVERVIEW The 80960CA is the second-generation member of the 80960 family of embedded processors. The 80960CA is object code compatible with the 32-bit 80960 Core Architecture while including Special Function Register extensions to control on-chip peripherals and instruction set extensions to shift 64bit operands and configure on-chip hardware. Multiple 128-bit internal buses, on-chip instruction caching and a sophisticated instruction scheduler allow the processor to sustain execution of two instructions every clock and peak at execution of three instructions per clock. A 32-bit demultiplexed and pipelined burst bus provides a 132 Mbyte/s bandwidth to a system’s high-speed external memory sub-system. In addition, the 80960CA’s on-chip caching of instructions, procedure context and critical program data substantially decouple system performance from the wait states associated with accesses to the system’s slower, cost sensitive, main memory subsystem. The 80960CA bus controller integrates full wait state and bus width control for highest system performance with minimal system design complexity. Unaligned access and Big Endian byte order support reduces the cost of porting existing applications to the 80960CA. The processor also integrates four complete datachaining DMA channels and a high-speed interrupt controller on-chip. DMA channels perform: singlecycle or two-cycle transfers, data packing and unpacking and data chaining. Block transfers—in addition to source or destination synchronized transfers—are provided. The interrupt controller provides full programmability of 248 interrupt sources into 32 priority levels with a typical interrupt task switch (”latency”) time of 750 ns. Instruction Prefetch Queue Instruction Cache (1 KByte, Two-way Set Associative) 128-BIT CACHE BUS Interrupt Programmable Port Interrupt Controller Parallel Instruction Scheduler Multiply/Divide Unit Execution Unit Register-side Machine Bus Memory-side Machine Bus Six-port Register File 64-Bit SRC1 Bus 32-Bit Base Bus 64-Bit SRC2 Bus 128-Bit Load Bus 64-Bit DST Bus 128-Bit Store Bus Four-Channel DMA Controller DMA Port Memory Region Configuration Bus Controller Control Bus Request Queues Address Data 1 KByte Data RAM 5 to 15 Sets Register Cache Address Generation Unit F_CX001A Figure 1. 80960CA Block Diagram 1 80960CA-33, -25, -16 2.1 The C-Series Core The C-Series core is a very high performance microarchitectural implementation of the 80960 Core Architecture. The C-Series core can sustain execution of two instructions per clock (66 MIPs at 33 MHz). To achieve this level of performance, Intel has incorporated state-of-the-art silicon technology and innovative microarchitectural constructs into the implementation of the C-Series core. Factors that contribute to the core’s performance include: • Parallel instruction decoding allows issuance of up to three instructions per clock • Single-clock execution of most instructions • Parallel instruction decode allows sustained, simultaneous execution of two single-clock instructions every clock cycle • Efficient instruction pipeline minimizes pipeline break losses • Register and resource scoreboarding allow simultaneous multi-clock instruction execution • Branch look-ahead and prediction allows many branches to execute with no pipeline break • Local Register Cache integrated on-chip caches Call/Return context • Two-way set associative, 1 Kbyte integrated instruction cache • 1 Kbyte integrated Data RAM sustains a fourword (128-bit) access every clock cycle 2.2 Pipelined, Burst Bus A 32-bit high performance bus controller interfaces the 80960CA to external memory and peripherals. The Bus Control Unit features a maximum transfer rate of 132 Mbytes per second (at 33 MHz). Internally programmable wait states and 16 separately configurable memory regions allow the processor to interface with a variety of memory subsystems with a minimum of system complexity and a maximum of performance. The Bus Controller’s main features include: 2 • Demultiplexed, Burst Bus to exploit most efficient DRAM access modes • Address Pipelining to reduce memory cost while maintaining performance • 32-, 16- and 8-bit modes for I/O interfacing ease • Full internal wait state generation to reduce system cost • Little and Big Endian support to ease application development • Unaligned access support for code portability • Three-deep request queue to decouple the bus from the core 2.3 Flexible DMA Controller A four-channel DMA controller provides high speed DMA control for data transfers involving peripherals and memory. The DMA provides advanced features such as data chaining, byte assembly and disassembly and a high performance fly-by mode capable of transfer speeds of up to 59 Mbytes per second at 33 MHz. The DMA controller features a performance and flexibility which is only possible by integrating the DMA controller and the 80960CA core. 2.4 Priority Interrupt Controller A programmable-priority interrupt controller manages up to 248 external sources through the 8bit external interrupt port. The Interrupt Unit also handles the four internal sources from the DMA controller and a single non-maskable interrupt input. The 8-bit interrupt port can also be configured to provide individual interrupt sources that are level or edge triggered. Interrupts in the 80960CA are prioritized and signaled within 270 ns of the request. If the interrupt is of higher priority than the processor priority, the context switch to the interrupt routine typically is complete in another 480 ns. The interrupt unit provides the mechanism for the low latency and high throughput interrupt service which is essential for embedded applications. 80960CA-33, -25, -16 2.5 Instruction Set Summary Table 1 summarizes the 80960CA instruction set by logical groupings. See the i960 CA Microprocessor User’s Manual for a complete description of the instruction set. Table 1. 80960CA Instruction Set Data Movement Arithmetic Logical Bit and Bit Field and Byte Load Add And Set Bit Store Subtract Not And Clear Bit Move Multiply And Not Not Bit Load Address Divide Or Alter Bit Remainder Exclusive Or Scan For Bit Modulo Not Or Span Over Bit Shift Or Not Extract *Extended Shift Nor Modify Extended Multiply Exclusive Nor Scan Byte for Equal Extended Divide Not Add with Carry Nand Subtract with Carry Rotate Comparison Branch Call/Return Fault Compare Unconditional Branch Call Conditional Fault Conditional Compare Conditional Branch Call Extended Synchronize Faults Compare and Increment Compare and Branch Call System Return Compare and Decrement Branch and Link Test Condition Code Check Bit Debug Processor Management Atomic Modify Trace Controls Flush Local Registers Atomic Add Mark Modify Arithmetic Controls Atomic Modify Force Mark Modify Process Controls *System Control *DMA Control NOTES: Instructions marked by (*) are 80960CA extensions to the 80960 instruction set. 3 80960CA-33, -25, -16 3.0 PACKAGE INFORMATION 3.1 Package Introduction Table 2. Pin Description Nomenclature Symbol This section describes the pins, pinouts and thermal characteristics for the 80960CA in the 168-pin Ceramic Pin Grid Array (PGA) package and the 196pin Plastic Quad Flat Package (PQFP). For complete package specifications and information, see the Packaging Handbook (Order No. 240800). 3.2 Input only pin O Output only pin I/O Pin can be either an input or output – Pins “must be” connected as described S(...) Synchronous. Inputs must meet setup and hold times relative to PCLK2:1 for proper operation. All outputs are synchronous to PCLK2:1. S(E) Edge sensitive input S(L) Level sensitive input A(...) Asynchronous. Inputs may be asynchronous to PCLK2:1. A(E) Edge sensitive input A(L) Level sensitive input H(...) While the processor’s bus is in the Hold Acknowledge or Bus Backoff state, the pin: H(1) is driven to VCC H(0) is driven to VSS H(Z) floats H(Q) continues to be a valid input R(...) While the processor’s RESET pin is low, the pin: R(1) is driven to VCC R(0) is driven to VSS R(Z) floats R(Q) continues to be a valid output Pin Descriptions The 80960CA pins are described in this section. Table 2 presents the legend for interpreting the pin descriptions in the following tables. Pins associated with the 32-bit demultiplexed processor bus are described in Table 3. Pins associated with basic processor configuration and control are described in Table 4. Pins associated with the 80960CA DMA Controller and Interrupt Unit are described in Table 5. All pins float while the processor is in the ONCE mode. 4 Description I 80960CA-33, -25, -16 Table 3. 80960CA Pin Description — External Bus Signals (Sheet 1 of 3) Type Description A31:2 Name O S H(Z) R(Z) ADDRESS BUS carries the physical address’ upper 30 bits. A31 is the most significant address bit; A2 is the least significant. During a bus access, A31:2 identify all external addresses to word (4-byte) boundaries. The byte enable signals indicate the selected byte in each word. During burst accesses, A3:2 increment to indicate successive data cycles. D31:0 I/O S(L) H(Z) R(Z) DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width configuration. The least significant bit of the data is carried on D0 and the most significant on D31. When the bus is configured for 8-bit data, the lower 8 data lines, D7:0 are used. For 16-bit data bus widths, D15:0 are used. For 32-bit bus widths the full data bus is used. BE3:0 O S H(Z) R(1) BYTE ENABLES select which of the four bytes addressed by A31:2 are active during an access to a memory region configured for a 32-bit data-bus width. BE3 applies to D31:24; BE2 applies to D23:16; BE1 applies to D15:8 BE0 applies to D7:0. 32-bit bus: BE3 –Byte Enable 3 –enable D31:24 BE2 –Byte Enable 2 –enable D23:16 BE1 –Byte Enable 1 –enable D15:8 BE0 –Byte Enable 0 –enable D7:0 For accesses to a memory region configured for a 16-bit data-bus width, the processor uses the BE3, BE1 and BE0 pins as BHE, A1 and BLE respectively. 16-bit bus: BE3 –Byte High Enable (BHE) BE2 –Not used (driven high or low) BE1 –Address Bit 1 (A1) BE0 –Byte Low Enable (BLE) –enable D15:8 –enable D7:0 For accesses to a memory region configured for an 8-bit data-bus width, the processor uses the BE1 and BE0 pins as A1 and A0 respectively. 8-bit bus: BE3 –Not used (driven high or low) BE2 –Not used (driven high or low) BE1 –Address Bit 1 (A1) BE0 –Address Bit 0 (A0) W/R O S H(Z) R(0) WRITE/READ is asserted for read requests and deasserted for write requests. The W/R signal changes in the same clock cycle as ADS. It remains valid for the entire access in non-pipelined regions. In pipelined regions, W/R is not guaranteed to be valid in the last cycle of a read access. ADS O S H(Z) R(1) ADDRESS STROBE indicates a valid address and the start of a new bus access. ADS is asserted for the first clock of a bus access. 5 80960CA-33, -25, -16 Table 3. 80960CA Pin Description — External Bus Signals (Sheet 2 of 3) 6 Name Type Description READY I S(L) H(Z) R(Z) READY is an input which signals the termination of a data transfer. READY is used to indicate that read data on the bus is valid or that a write-data transfer has completed. The READY signal works in conjunction with the internally programmed wait-state generator. If READY is enabled in a region, the pin is sampled after the programmed number of wait-states has expired. If the READY pin is deasserted, wait states continue to be inserted until READY becomes asserted. This is true for the NRAD, NRDD, NWAD and NWDD wait states. The NXDA wait states cannot be extended. BTERM I S(L) H(Z) R(Z) BURST TERMINATE is an input which breaks up a burst access and causes another address cycle to occur. The BTERM signal works in conjunction with the internally programmed wait-state generator. If READY and BTERM are enabled in a region, the BTERM pin is sampled after the programmed number of wait states has expired. When BTERM is asserted, a new ADS signal is generated and the access is completed. The READY input is ignored when BTERM is asserted. BTERM must be externally synchronized to satisfy BTERM setup and hold times. WAIT O S H(Z) R(1) WAIT indicates internal wait state generator status. WAIT is asserted when wait states are being caused by the internal wait state generator and not by the READY or BTERM inputs. WAIT can be used to derive a write-data strobe. WAIT can also be thought of as a READY output that the processor provides when it is inserting wait states. BLAST O S H(Z) R(0) BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the last data transfer of burst and non-burst accesses after the wait state counter reaches zero. BLAST remains asserted until the clock following the last cycle of the last data transfer of a bus access. If the READY or BTERM input is used to extend wait states, the BLAST signal remains asserted until READY or BTERM terminates the access. DT/R O S H(Z) R(0) DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R is used in conjunction with DEN to provide control for data transceivers attached to the external bus. When DT/R is asserted, the signal indicates that the processor receives data. Conversely, when deasserted, the processor sends data. DT/R changes only while DEN is high. DEN O S H(Z) R(1) DATA ENABLE indicates data cycles in a bus request. DEN is asserted at the start of the bus request first data cycle and is deasserted at the end of the last data cycle. DEN is used in conjunction with DT/R to provide control for data transceivers attached to the external bus. DEN remains asserted for sequential reads from pipelined memory regions. DEN is deasserted when DT/R changes. LOCK O S H(Z) R(1) BUS LOCK indicates that an atomic read-modify-write operation is in progress. LOCK may be used to prevent external agents from accessing memory which is currently involved in an atomic operation. LOCK is asserted in the first clock of an atomic operation and deasserted in the clock cycle following the last bus access for the atomic operation. To allow the most flexibility for memory system enforcement of locked accesses, the processor acknowledges a bus hold request when LOCK is asserted. The processor performs DMA transfers while LOCK is active. HOLD I S(L) H(Z) R(Z) HOLD REQUEST signals that an external agent requests access to the external bus. The processor asserts HOLDA after completing the current bus request. HOLD, HOLDA and BREQ are used together to arbitrate access to the processor’s external bus by external bus agents. 80960CA-33, -25, -16 Table 3. 80960CA Pin Description — External Bus Signals (Sheet 3 of 3) Type Description BOFF Name I S(L) H(Z) R(Z) BUS BACKOFF, when asserted, suspends the current access and causes the bus pins to float. When BOFF is deasserted, the ADS signal is asserted on the next clock cycle and the access is resumed. HOLDA O S H(1) R(Q) HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has relinquished control of the external bus. When HOLDA is asserted, the external address bus, data bus and bus control signals are floated. HOLD, BOFF, HOLDA and BREQ are used together to arbitrate access to the processor’s external bus by external bus agents. Since the processor grants HOLD requests and enters the Hold Acknowledge state even while RESET is asserted, the state of the HOLDA pin is independent of the RESET pin. BREQ O S H(Q) R(0) BUS REQUEST is asserted when the bus controller has a request pending. BREQ can be used by external bus arbitration logic in conjunction with HOLD and HOLDA to determine when to return mastership of the external bus to the processor. D/C O S H(Z) R(Z) DATA OR CODE is asserted for a data request and deasserted for instruction requests. D/C has the same timing as W/R. DMA O S H(Z) R(Z) DMA ACCESS indicates whether the bus request was initiated by the DMA controller. DMA is asserted for any DMA request. DMA is deasserted for all other requests. SUP O S H(Z) R(Z) SUPERVISOR ACCESS indicates whether the bus request is issued while in supervisor mode. SUP is asserted when the request has supervisor privileges and is deasserted otherwise. SUP can be used to isolate supervisor code and data structures from non-supervisor requests. 7 80960CA-33, -25, -16 Table 4. 80960CA Pin Description — Processor Control Signals (Sheet 1 of 2) Name RESET Type Description I A(L) H(Z) R(Z) RESET causes the chip to reset. When RESET is asserted, all external signals return to the reset state. When RESET is deasserted, initialization begins. When the 2-x clock mode is selected, RESET must remain asserted for 32 CLKIN cycles before being deasserted to guarantee correct processor initialization. When the 1-x clock mode is selected, RESET must remain asserted for 10,000 CLKIN cycles before being deasserted to guarantee correct processor initialization. The CLKMODE pin selects 1-x or 2-x input clock division of the CLKIN pin. The processor’s Hold Acknowledge bus state functions while the chip is reset. If the processor’s bus is in the Hold Acknowledge state when RESET is asserted, the processor will internally reset, but maintains the Hold Acknowledge state on external pins until the Hold request is removed. If a Hold request is made while the processor is in the reset state, the processor bus will grant HOLDA and enter the Hold Acknowledge state. FAIL O S H(Q) R(0) FAIL indicates failure of the processor’s self-test performed at initialization. When RESET is deasserted and the processor begins initialization, the FAIL pin is asserted. An internal self-test is performed as part of the initialization process. If this self-test passes, the FAIL pin is deasserted; otherwise it remains asserted. The FAIL pin is reasserted while the processor performs an external bus self-confidence test. If this self-test passes, the processor deasserts the FAIL pin and branches to the user’s initialization routine; otherwise the FAIL pin remains asserted. Internal self-test and the use of the FAIL pin can be disabled with the STEST pin. STEST I S(L) H(Z) R(Z) SELF TEST causes the processor’s internal self-test feature to be enabled or disabled at initialization. STEST is read on the rising edge of RESET. When asserted, the processor’s internal self-test and external bus confidence tests are performed during processor initialization. When deasserted, only the bus confidence tests are performed during initialization. ONCE I A(L) H(Z) R(Z) ON CIRCUIT EMULATION, when asserted, causes all outputs to be floated. ONCE is continuously sampled while RESET is low and is latched on the rising edge of RESET. To place the processor in the ONCE state: (1) assert RESET and ONCE (order does not matter) (2) wait for at least 16 CLKIN periods in 2-x mode—or 10,000 CLKIN periods in 1-x mode—after VCC and CLKIN are within operating specifications (3) deassert RESET (4) wait at least 32 CLKIN periods (The processor will now be latched in the ONCE state as long as RESET is high.) To exit the ONCE state, bring VCC and CLKIN to operating conditions, then assert RESET and bring ONCE high prior to deasserting RESET. CLKIN must operate within the specified operating conditions of the processor until Step 4 above has been completed. CLKIN may then be changed to DC to achieve the lowest possible ONCE mode leakage current. ONCE can be used by emulator products or for board testers to effectively make an installed processor transparent in the board. 8 80960CA-33, -25, -16 Table 4. 80960CA Pin Description — Processor Control Signals (Sheet 2 of 2) Type Description CLKIN Name I A(E) H(Z) R(Z) CLOCK INPUT is an input for the external clock needed to run the processor. The external clock is internally divided as prescribed by the CLKMODE pin to produce PCLK2:1. CLKMODE I A(L) H(Z) R(Z) CLOCK MODE selects the division factor applied to the external clock input (CLKIN). When CLKMODE is high, CLKIN is divided by one to create PCLK2:1 and the processor’s internal clock. When CLKMODE is low, CLKIN is divided by two to create PCLK2:1 and the processor’s internal clock. CLKMODE should be tied high or low in a system as the clock mode is not latched by the processor. If left unconnected, the processor will internally pull the CLKMODE pin low, enabling the 2-x clock mode. PCLK2:1 O S H(Q) R(Q) PROCESSOR OUTPUT CLOCKS provide a timing reference for all processor inputs and outputs. All input and output timings are specified in relation to PCLK2 and PCLK1. PCLK2 and PCLK1 are identical signals. Two output pins are provided to allow flexibility in the system’s allocation of capacitive loading on the clock. PCLK2:1 may also be connected at the processor to form a single clock signal. VSS – GROUND connections must be connected externally to a VSS board plane. V CC – POWER connections must be connected externally to a VCC board plane. V CCPLL – VCCPLL is a separate VCC supply pin for the phase lock loop used in 1-x clock mode. Connecting a simple lowpass filter to VCCPLL may help reduce clock jitter (TCP) in noisy environments. Otherwise, VCCPLL should be connected to VCC. This pin is implemented starting with the D-stepping. See Table 13 for die stepping information. NC – NO CONNECT pins must not be connected in a system. 9 80960CA-33, -25, -16 Table 5. 80960CA Pin Description — DMA and Interrupt Unit Control Signals Name Type Description DREQ3:0 I A(L) H(Z) R(Z) DMA REQUEST causes a DMA transfer to be requested. Each of the four signals requests a transfer on a single channel. DREQ0 requests channel 0, DREQ1 requests channel 1, etc. When two or more channels are requested simultaneously, the channel with the highest priority is serviced first. The channel priority mode is programmable. DACK3:0 O S H(1) R(1) DMA ACKNOWLEDGE indicates that a DMA transfer is being executed. Each of the four signals acknowledges a transfer for a single channel. DACK0 acknowledges channel 0, DACK1 acknowledges channel 1, etc. DACK3:0 are asserted when the requesting device of a DMA is accessed. I/O A(L) H(Z/Q) R(Z) END OF PROCESS/TERMINAL COUNT can be programmed as either an input (EOP3:0) or as an output (TC3:0), but not both. Each pin is individually programmable. When programmed as an input, EOPx causes the termination of a current DMA transfer for the channel corresponding to the EOPx pin. EOP0 corresponds to channel 0, EOP1 corresponds to channel 1, etc. When a channel is configured for source and destination chaining, the EOP pin for that channel causes termination of only the current buffer transferred and causes the next buffer to be transferred. EOP3:0 are asynchronous inputs. EOP/TC3:0 When programmed as an output, the channel’s TCx pin indicates that the channel byte count has reached 0 and a DMA has terminated. TCx is driven with the same timing as DACKx during the last DMA transfer for a buffer. If the last bus request is executed as multiple bus accesses, TCx will stay asserted for the entire bus request. XINT7:0 NMI 10 I A(E/L) H(Z) R(Z) I A(E) H(Z) R(Z) EXTERNAL INTERRUPT PINS cause interrupts to be requested. These pins can be configured in three modes: Dedicated Mode: each pin is a dedicated external interrupt source. Dedicated inputs can be individually programmed to be level (low) or edge (falling) activated. Expanded Mode: the eight pins act together as an 8-bit vectored interrupt source. The interrupt pins in this mode are level activated.Since the interrupt pins are active low, the vector number requested is the one’s complement of the positive logic value place on the port. This eliminates glue logic to interface to combinational priority encoders which output negative logic. Mixed Mode: XINT7:5 are dedicated sources and XINT4:0 act as the five most significant bits of an expanded mode vector. The least significant bits are set to 010 internally. NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur. NMI is the highest priority interrupt recognized. NMI is an edge (falling) activated source. 80960CA-33, -25, -16 3.3 80960CA Mechanical Data 3.3.1 80960CA PGA Pinout 80960CA PGA pinout as viewed from the top side of the component (i.e., pins facing down). Figure 3 shows the complete 80960CA PGA pinout as viewed from the pin-side of the package (i.e., pins facing up). See Section 4.0, ELECTRICAL SPECIFICATIONS for specifications and recommended connections. Tables 6 and 7 list the 80960CA pin names with package location. Figure 2 depicts the complete Table 6. 80960CA PGA Pinout — In Signal Order Address Bus Signal Pin Data Bus Signal Pin Bus Control Signal Pin A31 S15 D31 R3 BE3 S5 A30 Q13 D30 Q5 BE2 S6 A29 R14 D29 S2 BE1 S7 A28 Q14 D28 Q4 BE0 R9 A27 S16 D27 R2 W/R Signal Pin R15 D26 Q3 S17 D25 S1 A24 Q15 D24 R1 A23 R16 D23 Q2 A22 R17 D22 P3 READY S3 BTERM R4 A21 Q16 D21 Q1 P15 D20 P2 A19 P16 D19 P1 WAIT S12 A18 Q17 D18 N2 BLAST S8 A17 P17 D17 N1 Pin A16 DREQ3 A7 DREQ2 B6 FAIL A2 DREQ1 A6 DREQ0 B5 STEST B2 ONCE C3 R6 A20 I/O Signal RESET S10 A26 A25 ADS Processor Control CLKIN C13 CLKMODE C14 DACK3 A10 DACK2 A9 DACK1 A8 DACK0 B8 PLCK1 B14 EOP/TC3 A14 PLCK2 B13 EOP/TC2 A13 EOP/TC1 A12 EOP/TC0 A11 XINT7 C17 XINT6 C16 XINT5 B17 XINT4 C15 XINT3 B16 VCC XINT2 A17 VSS Location A16 N16 D16 M1 DT/R S11 A15 N17 D15 L1 DEN S9 A14 M17 D14 L2 A13 L16 D13 K1 A12 L17 D12 J1 A11 K17 D11 H1 A10 J17 D10 H2 HOLD R5 Location XINT1 A15 A9 H17 D9 G1 HOLDA S4 XINT0 B15 A8 G17 D8 F1 BREQ R13 NMI D15 D/C S13 LOCK S14 C7, C8, C9, C10, C11, C12, F15, G3, G15, H3, H15, J3, J15, K3, K15, L3, L15, M3, M15, Q7, Q8, Q9, Q10, Q11 A7 G16 D7 E1 A6 F17 D6 F2 A5 E17 D5 D1 DMA R12 B7, B9, B11, B12, C6, E15, F3, F16, G2, H16, J2, J16, K2, K16, M2, M16, N3, N15, Q6, R7, R8, R10, R11 A4 E16 D4 E2 SUP Q12 VCCPLL A3 D17 D3 C1 A2 D16 D2 D2 D1 C2 D0 E3 B10 No Connect BOFF B1 Location A1, A3, A4, A5, B3, B4, C4, C5, D3 11 80960CA-33, -25, -16 Table 7. 80960CA PGA Pinout — In Pin Order Pin A1 Signal NC Pin C1 Signal D3 Pin G1 Signal Pin Signal Pin Signal D9 M1 D16 R1 D24 A2 FAIL C2 D1 G2 VCC M2 VCC R2 D27 A3 NC C3 ONCE G3 VSS M3 VSS R3 D31 A4 NC C4 NC G15 VSS M15 VSS R4 BTERM A5 NC C5 NC G16 A7 M16 VCC R5 HOLD A6 DREQ1 C6 VCC G17 A8 M17 A14 R6 ADS A7 DREQ3 C7 VSS R7 VCC A8 DACK1 C8 VSS H1 D11 N1 D17 R8 VCC A9 DACK2 C9 VSS H2 D10 N2 D18 R9 BE0 A10 DACK3 C10 VSS H3 VSS N3 VCC R10 VCC A11 EOP/TC0 C11 VSS H15 VSS N15 VCC R11 VCC A12 EOP/TC1 C12 VSS H16 VCC N16 A16 R12 DMA A13 EOP/TC2 C13 CLKIN H17 A9 N17 A15 R13 BREQ A14 EOP/TC3 C14 CLKMODE R14 A29 A15 XINT1 C15 XINT4 J1 D12 P1 D19 R15 A26 A16 RESET C16 XINT6 J2 VCC P2 D20 R16 A23 A17 XINT2 C17 XINT7 J3 VSS P3 D22 R17 A22 J15 VSS P15 A20 B1 BOFF D1 D5 J16 VCC P16 A19 S1 D25 B2 STEST D2 D2 J17 A10 P17 A17 S2 D29 B3 NC D3 NC S3 READY B4 NC D15 NMI K1 D13 Q1 D21 S4 HOLDA B5 DREQ0 D16 A2 K2 VCC Q2 D23 S5 BE3 B6 DREQ2 D17 A3 B7 VCC B8 DACK0 E1 B9 VCC B10 B11 K3 VSS Q3 D26 S6 BE2 K15 VSS Q4 D28 S7 BE1 D7 K16 VCC Q5 D30 S8 BLAST E2 D4 K17 A11 Q6 VCC S9 DEN VCCPLL E3 D0 Q7 VSS S10 W/R VCC E15 VCC L1 D15 Q8 VSS S11 DT/R B12 VCC E16 A4 L2 D14 Q9 VSS S12 WAIT B13 PCLK2 E17 A5 L3 VSS Q10 VSS S13 D/C B14 PCLK1 L15 VSS Q11 VSS S14 LOCK B15 XINT0 F1 D8 L16 A13 Q12 SUP S15 A31 B16 XINT3 F2 D6 L17 A12 Q13 A30 S16 A27 B17 XINT5 F3 VCC Q14 A28 S17 A25 12 F15 VSS Q15 A24 F16 VCC Q16 A21 F17 A6 Q17 A18 80960CA-33, -25, -16 S R Q P N M L K J H G F E D C B A D25 D24 D21 D19 D17 D16 D15 D13 D12 D11 D9 D8 D7 D5 D3 BOFF NC D29 D27 D23 D20 D18 V CC D14 V CC V CC D10 V CC D6 D4 D2 D1 STEST FAIL READY D31 D26 D22 VCC V SS V SS V SS V SS V SS V SS V CC D0 NC ONCE NC NC D28 NC NC NC NC 1 1 2 2 3 3 4 4 HOLDA BTERM 5 5 BE3 HOLD D30 NC DREQ0 BE2 ADS V CC VCC DREQ2 DREQ1 BE1 V CC V SS VSS BLAST V CC V SS VSS DEN BE0 V SS VSS W/R V CC V SS VSS DT/R V CC V SS VSS V CC EOP/TC0 WAIT DMA SUP VSS V CC EOP/TC1 D/C BREQ A30 CLKIN PCLK2 EOP/TC2 LOCK A29 A28 CLK MODE PCLK1 EOP/TC3 A31 A26 A24 A20 VCC V SS V SS V SS V SS V SS V SS V SS V CC NMI XINT4 XINT0 XINT1 A27 A23 A21 A19 A16 V CC A13 V CC V CC VCC A7 V CC A4 A2 XINT6 XINT3 RESET A25 A22 A18 A17 A15 A14 A12 A11 A10 A9 A8 A6 A5 A3 XINT7 XINT5 XINT2 S R Q P N L K J 6 6 7 7 V CC DREQ3 8 8 DACK0 DACK1 9 9 V CC DACK2 10 10 V CCPLL DACK3 11 11 12 12 13 13 14 14 15 15 16 16 17 17 M H G F E D C B A F_CA002A Figure 2. 80960CA PGA Pinout — View from Top (Pins Facing Down) 13 80960CA-33, -25, -16 A B C D E F G H J K L M N P Q R S NC BOFF D3 D5 D7 D8 D9 D11 D12 D13 D15 D16 D17 D19 D21 D24 D25 FAIL STEST D1 D2 D4 D6 V CC D10 V CC V CC D14 V CC D18 D20 D23 D27 D29 NC NC ONCE NC D0 VCC V SS V SS V SS V SS VSS V SS V CC D22 D26 D31 READY NC NC NC D28 NC DREQ0 NC D30 HOLD BE3 DREQ1 DREQ2 V CC VCC ADS BE2 DREQ3 V SS V SS V CC BE1 V SS V CC BLAST 1 1 2 2 3 3 4 4 BTERM HOLDA 5 5 6 6 7 7 V CC 8 8 DACK1 DACK0 V SS DACK2 V SS V SS BE0 DEN V SS V SS V CC W/R Metal Lid 9 V CC 9 10 10 DACK3 V CCPLL 11 11 EOP/TC0 V CC V SS V SS V CC DT/R EOP/TC1 V CC V SS SUP DMA WAIT EOP/TC2 PCLK2 CLKIN A30 BREQ D/C EOP/TC3 PCLK1 CLK MODE A28 A29 LOCK 12 12 13 13 14 14 15 15 XINT1 XINT0 XINT4 NMI V CC VSS V SS V SS V SS V SS VSS V SS V CC A20 A24 A26 A31 RESET XINT3 XINT6 A2 A4 V CC A7 V CC V CC V CC A13 V CC A16 A19 A21 A23 A27 XINT2 XINT5 XINT7 A3 A5 A6 A8 A9 A10 A11 A12 A14 A15 A17 A18 A22 A25 D E F G H J K L M N P Q R S 16 16 17 17 A B C F_CA003A Figure 3. 80960CA PGA Pinout — View from Bottom (Pins Facing Up) 14 80960CA-33, -25, -16 3.3.2 80960CA PQFP Pinout See Section 4.0, ELECTRICAL SPECIFICATIONS for specifications and recommended connections. Tables 8 and 9 list the 80960CA pin names with package location. Figure 4 shows the 80960CA PQFP pinout as viewed from the top side. Table 8. 80960CA PQFP Pinout — In Signal Order Address Bus Signal Pin Data Bus Signal Bus Control Pin Signal Pin Processor Control Signal Pin I/O Signal Pin A31 153 D31 186 BE3 176 RESET 91 DREQ3 60 A30 152 D30 187 BE2 175 FAIL 45 DREQ2 59 A29 151 D29 188 BE1 172 STEST 46 DREQ1 58 A28 145 D28 189 BE0 170 ONCE 43 DREQ0 57 A27 144 D27 191 CLKIN 87 W/R 164 A26 143 D26 192 A25 142 D25 194 A24 141 D24 195 A23 139 D23 3 A22 138 D22 4 READY 182 BTERM 184 ADS 178 CLKMODE 85 DACK3 65 PCLK2 74 DACK2 64 PCLK1 78 DACK1 63 DACK0 62 V SS A21 137 D21 5 A20 136 D20 6 A19 134 D19 8 WAIT 162 A18 133 D18 9 BLAST 169 A17 132 D17 10 A16 130 D16 11 DT/R 163 A15 129 D15 13 DEN 167 A14 128 D14 14 A13 124 D13 15 A12 123 D12 17 A11 122 D11 18 HOLD 181 A10 120 D10 19 HOLDA 179 A9 119 D9 21 BREQ 155 A8 118 D8 22 LOCK 156 Location 2, 7, 16, 24, 30, 38, 39, 49, 56, 70, 75, 77, 81, 83, 88, 89, 92, 98, 105, 109, 110, 121, 125, 131, 135, 147, 150, 161, 165, 173, 174, 185, 196 102 XINT4 101 XINT3 100 XINT2 95 XINT1 94 XINT0 93 NMI 108 VCCPLL 72 23 D/C 159 No Connect 25 DMA 160 Location SUP 158 BOFF 40 29, 31, 41, 42, 47, 48, 51, 52, 53, 54, 55, 73, 76, 80, 84, 86, 90, 97, 104, 126, 146, 149, 157, 166, 177, 183, 193 26 27 A3 112 D3 33 A2 111 D2 34 D1 35 D0 36 107 1, 12, 20, 28, 32, 37, 44, 50, 61, 71, 79, 82, 96, 99, 103, 115, 127, 140, 148, 154, 168, 171, 180, 190 D7 D5 XINT7 106 D6 D4 66 XINT6 117 114 67 EOP/TC0 XINT5 116 113 68 EOP/TC1 VCC A7 A5 69 Location A6 A4 EOP/TC3 EOP/TC2 15 80960CA-33, -25, -16 Table 9. 80960CA PQFP Pinout — In Pin Order Pin Signal Pin Signal Pin Signal Pin Signal Pin Signal Pin 166 Signal 1 VCC 34 D2 67 EOP/TC1 100 XINT3 133 A18 NC 2 VSS 35 D1 68 EOP/TC2 101 XINT4 134 A19 167 DEN 3 D23 36 D0 69 EOP/TC3 102 XINT5 135 VSS 168 VCC 4 D22 37 VCC 70 VSS 103 VCC 136 A20 169 BLAST 5 D21 38 VSS 71 VCC 104 NC 137 A21 170 BE0 6 D20 39 VSS 72 VCCPLL 105 VSS 138 A22 171 VCC 7 VSS 40 BOFF 73 NC 106 XINT6 139 A23 172 BE1 8 D19 41 NC 74 PCLK2 107 XINT7 140 VCC 173 VSS 9 D18 42 NC 75 VSS 108 NMI 141 A24 174 VSS 10 D17 43 ONCE 76 NC 109 VSS 142 A25 175 BE2 11 D16 44 VCC 77 VSS 110 VSS 143 A26 176 BE3 12 VCC 45 FAIL 78 PCLK1 111 A2 144 A27 177 NC 13 D15 46 STEST 79 VCC 112 A3 145 A28 178 ADS 14 D14 47 NC 80 NC 113 A4 146 NC 179 HOLDA 15 D13 48 NC 81 VSS 114 A5 147 VSS 180 VCC HOLD 16 VSS 49 VSS 82 VCC 115 VCC 148 VCC 181 17 D12 50 V CC 83 VSS 116 A6 149 NC 182 READY 18 D11 51 NC 84 NC 117 A7 150 VSS 183 NC 19 D10 52 NC 85 CLKMODE 118 A8 151 A29 184 BTERM 20 VCC 53 NC 86 NC 119 A9 152 A30 185 VSS 21 D9 54 NC 87 CLKIN 120 A10 153 A31 186 D31 22 D8 55 NC 88 VSS 121 VSS 154 VCC 187 D30 23 D7 56 V SS 89 VSS 122 A11 155 BREQ 188 D29 D28 24 VSS 57 DREQ0 90 NC 123 A12 156 LOCK 189 25 D6 58 DREQ1 91 RESET 124 A13 157 NC 190 VCC 26 D5 59 DREQ2 92 VSS 125 VSS 158 SUP 191 D27 27 D4 60 DREQ3 93 XINT0 126 NC 159 D/C 192 D26 28 VCC 61 VCC 94 XINT1 127 VCC 160 DMA 193 NC 29 NC 62 DACK0 95 XINT2 128 A14 161 VSS 194 D25 30 VSS 63 DACK1 96 VCC 129 A15 162 WAIT 195 D24 31 NC 64 DACK2 97 NC 130 A16 163 DT/R 196 VSS 32 VCC 65 DACK3 98 VSS 131 VSS 164 W/R 33 D3 66 EOP/TC0 99 VCC 132 A17 165 VSS 16 80960CA-33, -25, -16 98 50 99 49 147 Pin 1 148 196 F_CA004A Figure 4. 80960CA PQFP Pinout (View from Top Side) 17 80960CA-33, -25, -16 3.4 Package Thermal Specifications The 80960CA is specified for operation when TC (case temperature) is within the range of 0oC–100oC. TC may be measured in any environment to determine whether the 80960CA is within specified operating range. Case temperature should be measured at the center of the top surface, opposite the pins. Refer to Figure 5. TA (ambient temperature) can be calculated from θCA (thermal resistance from case to ambient) using the following equation: Measure PGA temperature at center of top surface TA = TC – P*θCA Table 10 shows the maximum TA allowable (without exceeding TC) at various airflows and operating frequencies (fPCLK). Note that TA is greatly improved by attaching fins or a heatsink to the package. P (maximum power consumption) is calculated by using the typical ICC as tabulated in Section 4.4, DC Specifications and VCC of 5V. Measure PQFP case temperature at center of top surface. 168 - Pin PGA Pin 196 Pin 1 F_CX007A Figure 5. Measuring 80960CA PGA and PQFP Case Temperature Table 10. Maximum TA at Various Airflows in oC (PGA Package Only) Airflow-ft/min (m/sec) TA with Heatsink* TA without Heatsink* fPCLK (MHz) 0 200 400 600 800 1000 (0) (1.01) (2.03) (3.04) (4.06) (5.07) 33 51 66 79 81 85 87 25 61 73 83 85 88 89 16 74 82 89 90 92 93 33 36 47 59 66 73 75 25 49 58 67 73 78 80 16 66 72 78 82 86 87 NOTES: *0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). 18 80960CA-33, -25, -16 Table 11. 80960CA PGA Package Thermal Characteristics Thermal Resistance — °C/Watt Airflow — ft./min (m/sec) Parameter 0 200 400 600 800 1000 (0) (1.01) (2.03) (3.07) (4.06) (5.07) θ Junction-to-Case (Case measured as shown in Figure 5) 1.5 1.5 1.5 1.5 1.5 1.5 θ Case-to-Ambient (No Heatsink) 17 14 11 9 7.1 6.6 θ Case-to-Ambient (With Heatsink)* 13 9 5.5 5 3.9 3.4 θJA θJC NOTES: 1. This table applies to 80960CA PGA plugged into socket or soldered directly to board. 2. θJA = θJC + θCA *0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing). Table 12. 80960CA PQFP Package Thermal Characteristics Thermal Resistance — °C/Watt Airflow — ft./min (m/sec) Parameter θ Junction-to-Case (Case Measured as shown in Figure 5) θ Case-to-Ambient (No Heatsink) 0 50 100 200 400 600 800 (0) (0.25) (0.50) (1.01) (2.03) (3.04) (4.06) 5 5 5 5 5 5 5 19 18 17 15 12 10 9 NOTES: 1. This table applies to 80960CA PQFP soldered directly to board. 2. θJA = θJC + θCA θJC 19 80960CA-33, -25, -16 3.5 Stepping Register Information Upon reset, register g0 contains die stepping information. Figure 6 shows how g0 is configured. The most significant byte contains an ASCII 0. The upper middle byte contains an ASCII C. The lower middle byte contains an ASCII A. The least significant byte contains the stepping number in ASCII. g0 retains this information until it is overwritten by the user program. ASCII 00 43 41 Stepping Number DECIMAL 0 C A Stepping Number MSB LSB Figure 6. Register g0 Table 13 contains a cross reference of the number in the least significant byte of register g0 to the die stepping number. Table 13. Die Stepping Cross Reference 20 g0 Least Significant Byte Die Stepping 01 B 02 C-1 03 C-2,C-3 04 D 3.6 Suggested Sources for 80960CA Accessories The following is a list of suggested sources for 80960CA accessories. This is not an endorsement of any kind, nor is it a warranty of the performance of any of the listed products and/or companies. Sockets 1. 3M Textool Test and Interconnection Products Department P.O. Box 2963 Austin, TX 78769-2963 2. Augat, Inc. Interconnection Products Group 33 Perry Avenue P.O. box 779 Attleboro, MA 02703 (508) 699-7646 3. Concept Manufacturing, Inc. (Decoupling Sockets) 41484 Christy Street Fremont, CA 94538 (415) 651-3804 Heatsinks/Fins 1. Thermalloy, Inc. 2021 West Valley View Lane Dallas, TX 75234-8993 (214) 243-4321 FAX: (214) 241-4656 2. E G & G Division 60 Audubon Road Wakefield, MA 01880 (617) 245-5900 80960CA-33, -25, -16 4.0 ELECTRICAL SPECIFICATIONS 4.1 Absolute Maximum Ratings Parameter Maximum Rating Storage Temperature ................................–65oC to +150oC Case Temperature Under Bias .................–65oC to +110oC Supply Voltage wrt. VSS ............................. –0.5V to + 6.5V NOTICE: This is a production data sheet. The specifications are subject to change without notice. *WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. Voltage on Other Pins wrt. VSS ...........–0.5V to VCC + 0.5V 4.2 Operating Conditions Table 14. Operating Conditions (80960CA-33, -25, -16) Min Max Units VCC Symbol Supply Voltage 80960CA-33 80960CA-25 80960CA-16 4.75 4.50 4.50 5.25 5.50 5.50 V V V fCLK2x Input Clock Frequency (2-x Mode) 80960CA-33 80960CA-25 80960CA-16 0 0 0 66.66 50 32 MHz MHz MHz fCLK1x Input Clock Frequency (1-x Mode) 80960CA-33 80960CA-25 80960CA-16 8 8 8 33.33 25 16 MHz MHz MHz PGA Package 196-Pin PQFP 0 0 100 100 oC TC Parameter Case Temperature Under Bias 80960CA-33, -25, -16 Notes (1) oC NOTES: 1. When in the 1-x input clock mode, CLKIN is an input to an internal phase-locked loop and must maintain a minimum frequency of 8 MHz for proper processor operation. However, in the 1-x mode, CLKIN may still be stopped when the processor either is in a reset condition or is reset. If CLKIN is stopped, the specified RESET low time must be provided once CLKIN restarts and has stabilized. 4.3 Recommended Connections Power and ground connections must be made to multiple VCC and VSS (GND) pins. Every 80960CAbased circuit board should include power (VCC) and ground (VSS) planes for power distribution. Every V CC pin must be connected to the power plane, and every VSS pin must be connected to the ground plane. Pins identified as “NC” must not be connected in the system. Liberal decoupling capacitance should be placed near the 80960CA. The processor can cause transient power surges when its numerous output buffers transition, particularly when connected to large capacitive loads. Low inductance capacitors and interconnects are recommended for best high frequency electrical performance. Inductance can be reduced by shortening the board traces between the processor and decoupling capacitors as much as possible. Capacitors specifically designed for PGA packages will offer the lowest possible inductance. For reliable operation, always connect unused inputs to an appropriate signal level. In particular, any unused interrupt (XINT, NMI) or DMA (DREQ) input should be connected to VCC through a pull-up resistor, as should BTERM if not used. Pull-up resistors should be in the in the range of 20 KΩ for each pin tied high. If READY or HOLD are not used, the unused input should be connected to ground. N.C. pins must always remain unconnected. Refer to the i960 Cx Microprocessor User’s Manual (Order Number 270710) for more information. 21 80960CA-33, -25, -16 4.4 DC Specifications Table 15. DC Characteristics (80960CA-33, -25, -16 under the conditions described in Section 4.2, Operating Conditions.) Min Max Units VIL Symbol Input Low Voltage for all pins except RESET Parameter – 0.3 +0.8 V VIH Input High Voltage for all pins except RESET 2.0 VCC + 0.3 V 0.45 VOL Output Low Voltage VOH Output High Voltage VILR Input Low Voltage for RESET – 0.3 1.5 V 3.5 VCC + 0.3 V ±15 µA 0 ≤ VIN ≤ VCC (1) IOH = –1 mA IOH = – 200 µA 2.4 VCC – 0.5 V Notes IOL = 5 mA V V VIHR Input High Voltage for RESET ILI1 Input Leakage Current for each pin except: BTERM, ONCE, DREQ3:0, STEST, EOP3:0/TC3:0, NMI, XINT7:0, BOFF, READY, HOLD, CLKMODE ILI2 Input Leakage Current for: BTERM, ONCE, DREQ3:0, STEST, EOP3:0/TC3:0, NMI, XINT7:0, BOFF 0 – 300 µA VIN = 0.45V (2) ILI3 Input Leakage Current for: READY, HOLD, CLKMODE 0 500 µA VIN = 2.4V (3,7) ILO Output Leakage Current ±15 µA 0.45 ≤ VOUT ≤ VCC ICC Supply Current (80960CA-33): ICC Max ICCTyp 900 750 mA mA (4) (5) ICC Max ICCTyp 750 600 mA mA (4) (5) ICC Max ICCTyp 550 400 mA mA (4) (5) 100 mA ICC ICC Supply Current (80960CA-25): Supply Current (80960CA-16): IONCE ONCE-mode Supply Current CIN Input Capacitance for: CLKIN, RESET, ONCE, READY, HOLD, DREQ3:0, BOFF, XINT7:0, NMI, BTERM, CLKMODE 12 pF COUT Output Capacitance of each output pin 12 pF FC = 1 MHz (6) CI/O I/O Pin Capacitance 12 pF FC = 1 MHz 0 FC = 1 MHz NOTES: 1. No pullup or pulldown. 2. These pins have internal pullup resistors. 3. These pins have internal pulldown resistors. 4. Measured at worst case frequency, VCC and temperature, with device operating and outputs loaded to the test conditions described in Section 4.5.1, AC Test Conditions. 5. ICC Typical is not tested. 6. Output Capacitance is the capacitive load of a floating output. 7. CLKMODE pin has a pulldown resistor only when ONCE pin is deasserted. 22 80960CA-33, -25, -16 4.5 AC Specifications Table 16. 80960CA AC Characteristics (33 MHz) (80960CA-33 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) Symbol Parameter Min Max Units Notes Input Clock (1,9) CLKIN Frequency TF TC CLKIN Period 0 66.66 MHz In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) In 1-x Mode (f CLK1x) 30 15 125 ∞ ±0.1% ns ns ∆ (11) TCS CLKIN Period Stability TCH CLKIN High Time In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) 6 6 62.5 ∞ ns ns (11) TCL CLKIN Low Time In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) 6 6 62.5 ∞ ns ns (11) TCR CLKIN Rise Time 0 6 ns TCF CLKIN Fall Time 0 6 ns –2 2 2 25 ns ns (3,12) (3) ns ns (12) (3) Output Clocks (1,8) CLKIN to PCLK2:1 Delay TCP In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) TC 2TC In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) (12) T PCLK2:1 Period TPH TPL PCLK2:1 High Time PCLK2:1 Low Time (T/2) – 2 (T/2) – 2 T/2 T/2 ns ns (12) (12) TPR PCLK2:1 Rise Time 1 4 ns (3) TPF PCLK2:1 Fall Time 1 4 ns (3) 3 3 6 3 4 5 3 4 4 4 3 T/2 + 3 2 3 14 16 18 18 16 16 16 16 16 18 16 T/2 + 14 14 18 ns ns ns ns ns ns ns ns ns ns ns ns ns ns (6,10) 3 22 ns (6) Synchronous Outputs (8) Output Valid Delay, Output Hold TOH TOV TOH1, TOV1 TOH2, TOV2 TOH3, TOV3 TOH4, TOV4 TOH5, TOV5 TOH6, TOV6 TOH7, TOV7 TOH8, TOV8 TOH9, TOV9 TOH10, TOV10 TOH11, TOV11 TOH12, TOV12 TOH13, TOV13 TOH14, TOV14 TOF (6,10) A31:2 BE3:0 ADS W/R D/C, SUP, DMA BLAST, WAIT DEN HOLDA, BREQ LOCK DACK3:0 D31:0 DT/R FAIL EOP3:0/TC3:0 Output Float for all outputs Synchronous Inputs (1,9,10) Input Setup TIS TIS1 TIS2 TIS3 TIS4 Input Hold TIH TIH1 TIH2 TIH3 TIH4 D31:0 BOFF BTERM/READY HOLD 3 17 7 7 ns ns ns ns D31:0 BOFF BTERM/READY HOLD 5 5 2 3 ns ns ns ns 23 80960CA-33, -25, -16 Table 16. 80960CA AC Characteristics (33 MHz) (Continued) (80960CA-33 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) Symbol Parameter Min Max Units Notes Relative Output Timings (1,2,3,8) TAVSH1 A31:2 Valid to ADS Rising T–4 T+4 ns TAVSH2 BE3:0, W/R, SUP, D/C, DMA, DACK3:0 Valid to ADS Rising T–6 T+6 ns TAVEL1 A31:2 Valid to DEN Falling T–4 T+4 ns TAVEL2 BE3:0, W/R, SUP, INST, DMA, DACK3:0 Valid to DEN Falling T–6 T+6 ns TNLQV WAIT Falling to Output Data Valid ±4 ns TDVNH TNLNH Output Data Valid to WAIT Rising WAIT Falling to WAIT Rising N*T – 4 N*T + 4 N*T ± 4 ns ns TNHQX Output Data Hold after WAIT Rising (N+1)*T–8 (N+1)*T+6 ns (5) TEHTV DT/R Hold after DEN High T/2 – 7 ∞ ns (6) DT/R Valid to DEN Falling TTVEL Relative Input Timings (1,2,3) T/2 – 4 ns (4) (4) TIS5 RESET Input Setup (2-x Clock Mode) 6 ns TIH5 RESET Input Hold (2-x Clock Mode) 5 ns (13) (13) TIS6 TIH6 DREQ3:0 Input Setup DREQ3:0 Input Hold 12 7 ns ns (7) (7) TIS7 XINT7:0, NMI Input Setup 7 ns (15) TIH7 XINT7:0, NMI Input Hold 3 ns (15) TIS8 TIH8 RESET Input Setup (1-x Clock Mode) RESET Input Hold (1-x Clock Mode) 3 T/4 + 1 ns ns (14) (14) NOTES: 1. See Section 4.5.2, AC Timing Waveforms for waveforms and definitions. 2. See Figure 16 for capacitive derating information for output delays and hold times. 3. See Figure 17 for capacitive derating information for rise and fall times. 4. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus Controller Region Table. WAIT never goes active when there are no wait states in an access. 5. N = Number of wait states inserted with READY. 6. Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity. 7. Since asynchronous inputs are synchronized internally by the 80960CA, they have no required setup or hold times to be recognized and for proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1, the setup times shown must be met. Asynchronous inputs must be active for at least two consecutive PCLK2:1 rising edges to be seen by the processor. 8. These specifications are guaranteed by the processor. 9. These specifications must be met by the system for proper operation of the processor. 10. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating Curves to adjust the timing for PCLK2:1 loading. 11. In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When the processor is in reset, the input clock may stop even in 1-x mode. 12. When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than ± 0.1% between adjacent cycles. 13. In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the falling edge of the CLKIN. (See Figure 22.) 14. In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the rising edge of the CLKIN. (See Figure 23.) 15. The interrupt pins are synchronized internally by the 80960CA. They have no required setup or hold times for proper operation. These pins are sampled by the interrupt controller every other clock and must be active for at least three consecutive PCLK2:1 rising edges when asserting them asynchronously. To guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consecutive PCLK2:1 rising edges. 24 80960CA-33, -25, -16 Table 17. 80960CA AC Characteristics (25 MHz) (80960CA-25 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) Symbol Parameter Min Max Units Input Clock (1,9) TF CLKIN Frequency TC CLKIN Period In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) Notes 0 50 MHz 40 20 125 ∞ ns ns (11) TCS CLKIN Period Stability In 1-x Mode (f CLK1x) ±0.1% ∆ (12) TCH CLKIN High Time In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) 8 8 62.5 ∞ ns ns (11) TCL CLKIN Low Time In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) 8 8 62.5 ∞ ns ns (11) TCR CLKIN Rise Time 0 6 ns 0 6 ns –2 2 2 25 ns ns (3,12) (3) (12) (3) (12) (12) CLKIN Fall Time TCF Output Clocks (1,8) TCP CLKIN to PCLK2:1 Delay In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) T PCLK2:1 Period In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) TPH PCLK2:1 High Time (T/2) – 3 T/2 ns ns ns TPL PCLK2:1 Low Time (T/2) – 3 T/2 ns TPR PCLK2:1 Rise Time 1 4 ns (3) 1 4 ns (3) A31:2 BE3:0 ADS W/R D/C, SUP, DMA BLAST, WAIT DEN HOLDA, BREQ LOCK DACK3:0 D31:0 DT/R FAIL EOP3:0/TC3:0 3 3 6 3 4 5 3 4 4 4 3 T/2 + 3 2 3 3 16 18 20 20 18 18 18 18 18 20 18 T/2 + 16 16 20 22 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Input Setup TIS1 TIS2 TIS3 TIS4 D31:0 BOFF BTERM/READY HOLD 5 19 9 9 ns ns ns ns Input Hold TIH1 TIH2 TIH3 TIH4 D31:0 BOFF BTERM/READY HOLD 5 7 2 5 ns ns ns ns PCLK2:1 Fall Time TPF Synchronous Outputs (8) TOH TOV TOF Output Valid Delay, Output Hold TOH1, TOV1 TOH2, TOV2 TOH3, TOV3 TOH4, TOV4 TOH5, TOV5 TOH6, TOV6 TOH7, TOV7 TOH8, TOV8 TOH9, TOV9 TOH10, TOV10 TOH11, TOV11 TOH12, TOV12 TOH13, TOV13 TOH14, TOV14 Output Float for all outputs TC 2TC (6,10) (6,10) (6) Synchronous Inputs (1,9,10) TIS TIH 25 80960CA-33, -25, -16 Table 17. 80960CA AC Characteristics (25 MHz) (Continued) (80960CA-25 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) Symbol Parameter Min Max Units Relative Output Timings (1,2,3,8) Notes TAVSH1 A31:2 Valid to ADS Rising T–4 T+4 ns TAVSH2 BE3:0, W/R, SUP, D/C, DMA, DACK3:0 Valid to ADS Rising T–6 T+6 ns TAVEL1 A31:2 Valid to DEN Falling T–4 T+4 ns TAVEL2 BE3:0, W/R, SUP, INST, DMA, DACK3:0 Valid to DEN Falling T–6 T+6 ns TNLQV WAIT Falling to Output Data Valid ±4 ns TDVNH TNLNH Output Data Valid to WAIT Rising WAIT Falling to WAIT Rising N*T – 4 N*T + 4 N*T ± 4 ns ns TNHQX Output Data Hold after WAIT Rising (N+1)*T–8 (N+1)*T+6 ns (5) TEHTV DT/R Hold after DEN High T/2 – 7 ∞ ns (6) DT/R Valid to DEN Falling TTVEL Relative Input Timings (1,2,3) T/2 – 4 ns (4) (4) TIS5 RESET Input Setup (2-x Clock Mode) 8 ns TIH5 RESET Input Hold (2-x Clock Mode) 7 ns (13) (13) TIS6 TIH6 DREQ3:0 Input Setup DREQ3:0 Input Hold 14 9 ns ns (7) (7) TIS7 XINT7:0, NMI Input Setup 9 ns (15) TIH7 XINT7:0, NMI Input Hold 5 ns (15) TIS8 TIH8 RESET Input Setup (1-x Clock Mode) RESET Input Hold (1-x Clock Mode) 3 T/4 + 1 ns ns (14) (14) NOTES: 1. See Section 4.5.2, AC Timing Waveforms for waveforms and definitions. 2. See Figure 16 for capacitive derating information for output delays and hold times. 3. See Figure 17 for capacitive derating information for rise and fall times. 4. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus Controller Region Table. WAIT never goes active when there are no wait states in an access. 5. N = Number of wait states inserted with READY. 6. Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity. 7. Since asynchronous inputs are synchronized internally by the 80960CA, they have no required setup or hold times to be recognized and for proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1, the setup times shown must be met. Asynchronous inputs must be active for at least two consecutive PCLK2:1 rising edges to be seen by the processor. 8. These specifications are guaranteed by the processor. 9. These specifications must be met by the system for proper operation of the processor. 10. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating Curves to adjust the timing for PCLK2:1 loading. 11. In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When the processor is in reset, the input clock may stop even in 1-x mode. 12. When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than ± 0.1% between adjacent cycles. 13. In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the falling edge of the CLKIN. (See Figure 22.) 14. In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the rising edge of the CLKIN. (See Figure 23.) 15. The interrupt pins are synchronized internally by the 80960CA. They have no required setup or hold times for proper operation. These pins are sampled by the interrupt controller every other clock and must be active for at least three consecutive PCLK2:1 rising edges when asserting them asynchronously. To guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consecutive PCLK2:1 rising edges. 26 80960CA-33, -25, -16 Table 18. 80960CA AC Characteristics (16 MHz) (80960CA-16 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) Symbol Parameter Min Max Units Notes Input Clock (1,9) TF TC CLKIN Frequency CLKIN Period TCS TCH CLKIN Period Stability CLKIN High Time TCL CLKIN Low Time TCR TCF CLKIN Rise Time CLKIN Fall Time In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) 0 62.5 31.25 32 125 ∞ MHz ns ns In 1-x Mode (f CLK1x) In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) 10 10 10 10 ±0.1% 62.5 ∞ 62.5 ∞ ∆ ns ns ns ns 0 0 6 6 ns ns –2 2 2 25 ns ns (3,12) (3) ns ns (12) (3) (11) (12) (11) (11) Output Clocks (1,8) TCP CLKIN to PCLK2:1 Delay In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) T PCLK2:1 Period In 1-x Mode (f CLK1x) In 2-x Mode (f CLK2x) TPH PCLK2:1 High Time (T/2) – 4 T/2 ns (12) TPL TPR PCLK2:1 Low Time PCLK2:1 Rise Time (T/2) – 4 1 T/2 4 ns ns (12) (3) TPF PCLK2:1 Fall Time 1 4 ns (3) 3 3 6 3 4 5 3 4 4 4 3 T/2 + 3 2 3 18 20 22 22 20 20 20 20 20 22 20 T/2 + 18 18 22 ns ns ns ns ns ns ns ns ns ns ns ns ns ns (6,10) 3 22 ns (6) TC 2TC Synchronous Outputs (8) TOH TOV Output Valid Delay, Output Hold TOH1, TOV1 TOH2, TOV2 TOH3, TOV3 TOH4, TOV4 TOH5, TOV5 TOH6, TOV6 TOH7, TOV7 TOH8, TOV8 TOH9, TOV9 TOH10, TOV10 TOH11, TOV11 TOH12, TOV12 TOH13, TOV13 TOH14, TOV14 TOF Output Float for all outputs (6,10) A31:2 BE3:0 ADS W/R D/C, SUP, DMA BLAST, WAIT DEN HOLDA, BREQ LOCK DACK3:0 D31:0 DT/R FAIL EOP3:0/TC3:0 Synchronous Inputs (1,9,10) TIS TIH Input Setup TIS1 TIS2 TIS3 TIS4 D31:0 BOFF BTERM/READY HOLD 5 21 9 9 ns ns ns ns Input Hold TIH1 TIH2 TIH3 TIH4 D31:0 BOFF BTERM/READY HOLD 5 7 2 5 ns ns ns ns 27 80960CA-33, -25, -16 Table 18. 80960CA AC Characteristics (16 MHz) (Continued) (80960CA-16 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.) Symbol Parameter Min Max Units Notes Relative Output Timings (1,2,3,8) TAVSH1 TAVSH2 A31:2 Valid to ADS Rising BE3:0, W/R, SUP, D/C, DMA, DACK3:0 Valid to ADS Rising TAVEL1 TAVEL2 TNLQV A31:2 Valid to DEN Falling BE3:0, W/R, SUP, INST, DMA, DACK3:0 Valid to DEN Falling WAIT Falling to Output Data Valid TDVNH Output Data Valid to WAIT Rising TNLNH WAIT Falling to WAIT Rising TNHQX TEHTV Output Data Hold after WAIT Rising DT/R Hold after DEN High TTVEL DT/R Valid to DEN Falling T–4 T+4 ns T–6 T+6 ns T–6 T+6 ns T+6 ns ns N*T + 4 ns T–6 ±4 N*T – 4 N*T ± 4 (N+1)*T–8 T/2 – 7 (N+1)*T+6 ∞ (4) ns (4) ns ns (5) (6) T/2 – 4 ns Relative Input Timings (1,2,3) TIS5 TIH5 RESET Input Setup (2-x Clock Mode) RESET Input Hold (2-x Clock Mode) 10 9 ns ns (13) (13) (7) TIS6 DREQ3:0 Input Setup 16 ns TIH6 DREQ3:0 Input Hold 11 ns (7) TIS7 TIH7 XINT7:0, NMI Input Setup XINT7:0, NMI Input Hold 9 5 ns ns (15) (15) TIS8 RESET Input Setup (1-x Clock Mode) 3 ns (14) TIH8 RESET Input Hold (1-x Clock Mode) T/4 + 1 ns (14) NOTES: 1. See Section 4.5.2, AC Timing Waveforms for waveforms and definitions. 2. See Figure 16 for capacitive derating information for output delays and hold times. 3. See Figure 17 for capacitive derating information for rise and fall times. 4. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus Controller Region Table. WAIT never goes active when there are no wait states in an access. 5. N = Number of wait states inserted with READY. 6. Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity. 7. Since asynchronous inputs are synchronized internally by the 80960CA, they have no required setup or hold times to be recognized and for proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1, the setup times shown must be met. Asynchronous inputs must be active for at least two consecutive PCLK2:1 rising edges to be seen by the processor. 8. These specifications are guaranteed by the processor. 9. These specifications must be met by the system for proper operation of the processor. 10. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating Curves to adjust the timing for PCLK2:1 loading. 11. In the 1-x input clock mode, the maximum input clock period is limited to 125 ns while the processor is operating. When the processor is in reset, the input clock may stop even in 1-x mode. 12. When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than ± 0.1% between adjacent cycles. 13. In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the falling edge of the CLKIN. (See Figure 22.) 14. In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the rising edge of the CLKIN. (See Figure 23.) 15. The interrupt pins are synchronized internally by the 80960CA. They have no required setup or hold times for proper operation. These pins are sampled by the interrupt controller every other clock and must be active for at least three consecutive PCLK2:1 rising edges when asserting them asynchronously. To guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consecutive PCLK2:1 rising edges. 28 80960CA-33, -25, -16 4.5.1 AC Test Conditions The AC Specifications in Section 4.5 are tested with the 50 pF load shown in Figure 7. Figure 16 shows how timings vary with load capacitance. Output Pin CL Specifications are measured at the 1.5V crossing point, unless otherwise indicated. Input waveforms are assumed to have a rise and fall time of ≤ 2 ns from 0.8V to 2.0V. See Section 4.5.2, AC Timing Waveforms for AC spec definitions, test points and illustrations. 4.5.2 CL = 50 pF for all signals F_CX008A Figure 7. AC Test Load AC Timing Waveforms 1.5V CLKIN TCP T 2.4V 1.5V 0.45V 1.5V PCLK2:1 TPH TPR TPL TPF F_CX009A Figure 8. Input and Output Clocks Waveform TCR TCF 2.0V 1.5V 0.8V TCH TCL TC F_CX010A Figure 9. CLKIN Waveform 29 80960CA-33, -25, -16 1.5V PCLK2:1 TOH Outputs TOV Max Min 1.5V 1.5V TOF Outputs 1.5V Max Min 1.5V 1.5V F_CX011A Figure 10. Output Delay and Float Waveform PCLK2:1 1.5V 1.5V TIH TIS Min Inputs: (READY, HOLD, BTERM, BOFF, DREQ3:0, D31:0 on reads) 1.5V Max Valid F_CX012A Figure 11. Input Setup and Hold Waveform TOV TOH - OUTPUT DELAY - The maximum output delay is referred to as the Output Valid Delay (TOV). The minimum output delay is referred to as the Output Hold (TOH). 30 TOF - OUTPUT FLOAT DELAY - The output float condition occurs when the maximum output current becomes less that ILO in magnitude. TIS TIH - INPUT SETUP AND HOLD - The input setup and hold requirements specify the sampling window during which synchronous inputs must be stable for correct processor operation. 80960CA-33, -25, -16 PCLK2:1 1.5V 1.5V NMI, XINT7:0 TIH TIS Min 1.5V Min 1.5V Valid 1.5V F_CX013A Figure 12. NMI, XINT7:0 Input Setup and Hold Waveform 1.5V PCLK2:1 1.5V 1.5V TOV TOF Min Outputs: A31:2, D31:0, BE3:0, ADS, BLAST, WAIT, W/R, DT/R, DEN, LOCK, D/C, SUP, DMA Max Max Min 1.5V Valid Valid TIH TIS Min TIH TIS Min Min Min 1.5V HOLD 1.5V 1.5V TOV TOV Min Min Max HOLDA 1.5V 1.5V Max 1.5V TOV TOH - OUTPUT DELAY - The maximum output delay is referred to as the Output Valid Delay (TOV). The minimum output delay is referred to as the Output Hold (TOH). TOF - OUTPUT FLOAT DELAY - The output float condition occurs when the maximum output current becomes less that ILO in magnitude. TIS TIH - INPUT SETUP AND HOLD - The input setup and hold requirements specify the sampling window during which synchronous inputs must be stable for correct processor operation. F_CX014A Figure 13. Hold Acknowledge Timings 31 80960CA-33, -25, -16 1.5V PCLK2:1 TOF Min Outputs: A31:2, D31:0, BE3:0, ADS, BLAST, WAIT, W/R, DT/R, DEN, LOCK, D/C, SUP, DMA Valid TIH BOFF 1.5V 1.5V 1.5V TOV Max Max Min 1.5V 1.5V 1.5V Valid TIS TIS TIH 1.5V 1.5V F_CX015A Figure 14. Bus Backoff (BOFF) Timings 32 80960CA-33, -25, -16 PCLK2:1 ADS 1.5V 1.5V 1.5V 1.5V 1.5V 1.5V TAVSH A31:2, BE3:0, W/R, LOCK, SUP, D/C, DMA 1.5V 1.5V D31:0 TNLQV TDVHN 1.5V WAIT 1.5V 1.5V TEHTV DEN TNHQX TNLNH TAVEL DT/R 1.5V Out TVEL 1.5V 1.5V In D31:0 VIH VIL F_CX016A Figure 15. Relative Timings Waveforms Output Valid Delays (ns) @ 1.5V 4.5.3 Derating Curves nom + 10 All outputs except: LOCK, DMA, SUP, BREQ, DACK3:0, EOP3:0/TC3:0, FAIL nom + 5 LOCK, DMA, SUP, BREQ, DACK3:0, EOP3:0/TC3:0, FAIL nom 50 Note: PCLK Load = 50pF 100 150 CL (pF) F_CX017A Figure 16. Output Delay or Hold vs. Load Capacitance 33 80960CA-33, -25, -16 0.8V to 2.0V 10 8 8 Time (ns) Time (ns) 0.8V to 2.0V 10 6 4 2 6 4 2 50 100 150 50 100 150 CL (pF) CL (pF) a) All outputs except: LOCK, DMA, SUP, HOLDA, BREQ b) LOCK, DMA, SUP, HOLDA, BREQ, DACK3:0, DACK3:0, EOP3:0/TC3:0, FAIL EOP3:0/TC3:0, FAIL F_CX019A Figure 17. Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC 900 ICC (mA) TC = 100° C TC = 0° C 0 0 fPCLK (MHz) 33 I CC - ICC under test conditions Figure 18. ICC vs. Frequency and Temperature 34 F_CX020A 80960CA-33, -25, -16 5.0 RESET, BACKOFF AND HOLD ACKNOWLEDGE Table 20 lists the condition of each processor output pin while HOLDA is asserted (low). Table 20. Hold Acknowledge and Backoff Conditions Table 19 lists the condition of each processor output pin while RESET is asserted (low). Pins Table 19. Reset Conditions A31:2 Pins State During Reset (HOLDA inactive)1 A31:2 Floating D31:0 Floating BE3:0 Driven high (Inactive) W/R Driven low (Read) ADS Driven high (Inactive) WAIT Driven high (Inactive) BLAST Driven low (Active) DT/R Driven low (Receive) DEN Driven high (Inactive) LOCK Driven high (Inactive) BREQ Driven low (Inactive) D/C Floating DMA Floating SUP Floating FAIL Driven low (Active) DACK3:0 Driven high (Inactive) EOP3:0/TC3:0 Floating (Set to input mode) State During HOLDA Floating D31:0 Floating BE3:0 Floating W/R Floating ADS Floating WAIT Floating BLAST Floating DT/R Floating DEN Floating LOCK Floating BREQ Driven (High or low) D/C Floating DMA Floating SUP Floating FAIL Driven high (Inactive) DACK3:0 Driven high (Inactive) EOP3:0/TC3:0 Driven (If output) NOTES: 1. With regard to bus output pin state only, the Hold Acknowledge state takes precedence over the reset state. Although asserting the RESET pin will internally reset the processor, the processor’s bus output pins will not enter the reset state if it has granted Hold Acknowledge to a previous HOLD request (HOLDA is active). Furthermore, the processor will grant new HOLD requests and enter the Hold Acknowledge state even while in reset. For example, if HOLDA is inactive and the processor is in the reset state, then HOLD is asserted, the processor’s bus pins enter the Hold Acknowledge state and HOLDA is granted. The processor will not be able to perform memory accesses until the HOLD request is removed, even if the RESET pin is brought high. This operation is provided to simplify boot-up synchronization among multiple processors sharing the same bus. 35 RESET STEST D31:0, EOP/TC3:0 INST, SUP, DMA, A31:2, D/C, BE3:0 BLAST W/R, DT/R, BREQ, FAIL ADS, LOCK, WAIT, DEN, DACK3:0 Inputs Tdelay 1 PCLK Valid Invalid CLKIN and VCC Stable to RESET high, minimum 32 CLKIN Periods in 2x Mode, 10,000 CLKIN periods in 1x Mode. Tsetup 1PCLK RESET high to First Bus activity, approximately 32 PCLK periods. Thold 1 PCLK ∼ ∼ ∼ ∼ PCLK2:1 ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ VCC and CLKIN Stable to Outputs Valid, maximum 32 CLKIN Periods. ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ VCC - ONCE ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ 36 ∼ ∼ Figure 19. Cold Reset Waveform ∼ ∼ ∼ ∼ F_CX021A 6.0 ∼ ∼ CLKIN 80960CA-33, -25, -16 BUS WAVEFORMS STEST RESET D31:0, EOP/TC3:0 Maximum RESET Low to RESET State 4 PCLK Periods SUP, DMA, A31:2, D/C, BE3:0 BLAST W/R, DT/R, BREQ, FAIL ADS, LOCK, WAIT, DEN, DACK3:0 Tdelay 1PCLK Minimum RESET Low Time 16 PCLK Periods Tsetup 1 PCLK RESET High to First Bus Activity, Approximately 32 PCLK Periods Thold 1 PCLK Valid ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ PCLK2:1 F_CX022A 80960CA-33, -25, -16 Figure 20. Warm Reset Waveform 37 Figure 21. Entering the ONCE State ONCE RESET ADS, BE3:0, A31:2, D31:0, LOCK, WAIT, BLAST,W/R, D/C, DEN, DT/R, HOLD, HOLDA, BLAST, FAIL, SUP,BREQ, DMA, EOP3:0/TC3:0, STEST, XINT7:0, NMI, DACK3:0, DREQ3:0 READY, BTERM PCLK2:1 VCC CLKIN ∼ ∼ ∼ ∼ ∼ ∼ VCC and CLKIN Stable to Outputs Valid, maximum 32 CLKIN Periods. CLKIN and VCC Stable and RESET low and ONCE low to RESET high, minimum 32 CLKIN Periods in 2x Mode, 10,000 CLKIN Periods in 1x Mode. ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ F_CX023A Maximum 32 CLKIN Periods Required after ONCE Mode entered ∼ ∼ ∼∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ 38 ∼ ∼ CLKIN may not float. It must be driven high or low or continue to run 80960CA-33, -25, -16 80960CA-33, -25, -16 1.5V CLKIN TIH RESET 1.5V 1.5V 1.5V TIS 1.5V 1.5V PCLK2:1 (Case 1) 1.5V 1.5V Max Min TCP PCLK2:1 (Case 2) 1.5V Max Min 1.5V Min TCP Max 1.5V TCP 1.5V SYNC Note: Case 1 and Case 2 show two possible polarities of PCLK2:1 F_CX024A Figure 22. Clock Synchronization in the 2-x Clock Mode 2x CLK CLKIN 1.5V 1.5V TIH RESET TIS 1.5V Note: In 1x clock mode, the RESET pin is actually sampled on the falling edge of 2xCLK. 2xCLK is an internal signal generated by the PLL and is not available on an external pin. Therefore, RESET is specified relative to the rising edge of CLKIN. The RESET pin is sampled when PCLK is high. F_CX025A Figure 23. Clock Synchronization in the 1-x Clock Mode 39 Bit Value Byte Order 31-23 22 0 0..0 X x reserved Function reserved 80960CA-33, -25, -16 Bus Width NWDD NWAD N XDA NRDD NRAD 21 20-19 18-17 16-12 11-10 9-8 7-3 2 0 0 X xx X xx 0 00000 0 00 X xx 0 00000 OFF 0 A D A D A PipeLining External Ready Control Burst 1 0 Disabled Disabled 0 0 D PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK Valid Valid Valid Valid Valid W/R BLAST DT/R DEN A3:2 Valid WAIT D31:0 In Out In F_CX026A Figure 24. Non-Burst, Non-Pipelined Requests Without Wait States 40 Bit Value Byte Order 31-23 22 0 0..0 X x reserved Function reserved 80960CA-33, -25, -16 Bus Width NWDD NWAD NXDA NRDD NRAD 21 20-19 18-17 16-12 11-10 9-8 7-3 2 0 0 X xx X xx X xxxxx 1 01 X xx 3 00011 OFF 0 A 3 2 1 D PipeLining External Ready Control Burst 1 0 Disabled Disabled 0 0 1 A PCLK ADS A31:2, BE3:0 Valid W/R BLAST DT/R DEN DMA, D/C, SUP, LOCK Valid WAIT D31:0 In F_CX027A Figure 25. Non-Burst, Non-Pipelined Read Request With Wait States 41 Bit Value Byte Order 31-23 22 0 0..0 X x reserved Function reserved 80960CA-33, -25, -16 Bus Width NWDD NWAD NXDA NRDD NRAD 21 20-19 18-17 16-12 11-10 9-8 7-3 2 0 0 X xx X xx 3 00011 1 01 X xx X xxxxxx OFF 0 A 3 2 1 D PipeLining 1 External Ready Control Burst 1 0 Disabled Disabled 0 0 A PCLK ADS A31:2, BE3:0 Valid W/R BLAST DT/R DEN SUP, DMA, D/C, LOCK Valid WAIT D31:0 Out F_CX028A Figure 26. Non-Burst, Non-Pipelined Write Request With Wait States 42 Bit Value Byte Order reserved Function reserved 80960CA-33, -25, -16 31-23 22 0 0..0 X x PipeLining Bus Width NWDD NWAD NXDA NRDD NRAD 21 20-19 18-17 16-12 11-10 9-8 7-3 2 0 0 32-Bit 10 X xx X xxxxx 0 00 0 00 0 00000 OFF 0 A D D D D External Ready Control Burst 1 0 Disabled Enabled 1 0 A PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK Valid W/R BLAST DT/R DEN A3:2 00 01 10 11 WAIT D31:0 In0 In1 In2 In3 F_CX029A Figure 27. Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus 43 Bit Value Byte Order 31-23 22 0 0..0 X x A reserved Function reserved 80960CA-33, -25, -16 Bus Width NWDD NWAD NXDA NRDD NRAD 21 20-19 18-17 16-12 11-10 9-8 7-3 2 0 0 32-bit 10 X xx X xxxxx 1 01 1 01 2 00010 OFF 0 D 1 2 1 D 1 D 1 PipeLining D External Ready Control Burst 1 0 Disabled Enabled 1 0 1 A PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK Valid W/R BLAST DT/R DEN A3:2 00 01 10 11 WAIT D31:0 In0 In1 In2 In3 F_CX030A Figure 28. Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus 44 Bit Value Byte Order 31-23 22 0 0..0 X x reserved Function reserved 80960CA-33, -25, -16 Bus Width NWDD NWAD NXDA NRDD NRAD 21 20-19 18-17 16-12 11-10 9-8 7-3 2 0 0 32-bit 10 0 00 0 00000 0 00 X xx X xxxxx OFF 0 A D D D PipeLining D External Ready Control Burst 1 0 Disabled Enabled 1 0 A PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK Valid W/R BLAST DT/R DEN A3:2 00 01 10 11 Out2 Out3 WAIT D31:0 Out0 Out1 F_CX031A Figure 29. Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus 45 Bit Value Byte Order 31-23 22 0 0..0 X x A reserved Function reserved 80960CA-33, -25, -16 Bus Width NWDD NWAD NXDA NRDD NRAD 21 20-19 18-17 16-12 11-10 9-8 7-3 2 0 0 32-bit 10 1 01 2 00010 1 01 X xx X xxxxx OFF 0 2 1 D 1 D 1 D 1 PipeLining D 1 External Ready Control Burst 1 0 Disabled Enabled 1 0 A PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK Valid W/R BLAST DT/R DEN A3:2 00 01 10 11 WAIT D31:0 Out0 Out1 Out2 Out3 F_CX032A Figure 30. Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus 46 Bit Value Byte Order 31-23 22 0 0..0 X x reserved Function reserved 80960CA-33, -25, -16 Bus Width NWDD NWAD NXDA NRDD NRAD 21 20-19 18-17 16-12 11-10 9-8 7-3 2 0 0 16-bit 01 X xx X xxxxx 1 01 1 01 2 00010 OFF 0 Disabled Enabled 1 0 D 1 A 2 1 D 1 D 1 D 1 PipeLining External Ready Control Burst 1 0 A PCLK ADS SUP, DMA, D/C, LOCK, A31:4, BE3/BHE, BE0/BLE Valid W/R BLAST DT/R DEN A3:2 A3:2 = 00 or 10 A3:2 = 01 or 11 BE1/A1 WAIT D31:0 D15:0 A1=0 D15:0 A1=1 D15:0 A1=0 D15:0 A1=1 F_CX033A Figure 31. Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus 47 Bit Value Byte Order 31-23 22 0 0..0 X x reserved Function reserved 80960CA-33, -25, -16 Bus Width NWDD NWAD NXDA NRDD NRAD 21 20-19 18-17 16-12 11-10 9-8 7-3 2 0 0 8-bit 00 X xx X xxxxx 1 01 1 01 2 00010 OFF 0 Disabled Enabled 1 0 D 1 A 2 1 D 1 D 1 D 1 PipeLining External Ready Control Burst 1 0 A PCLK ADS SUP, DMA, D/C, LOCK, A31:4 Valid W/R BLAST DT/R DEN A3:2 BE1/A1, BE0/A0 A3:2 = 00, 01, 10 or 11 A1:0 = 00 A1:0 = 01 A1:0 = 10 A1:0 =11 WAIT D31:0 D7:0 Byte 0 D7:0 Byte 1 D7:0 Byte 2 D7:0 Byte 3 F_CX034A Figure 32. Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus 48 Bit Value Byte Order 31-23 22 0 0..0 X x reserved Function reserved 80960CA-33, -25, -16 Bus Width NWDD NWAD NXDA NRDD 21 20-19 18-17 16-12 11-10 9-8 7-3 2 1 0 0 0 X xx X xx X xxxxx X xx X xx 0 00000 ON 1 X x Disabled 0 A A' D A'' D' A''' D'' NRAD A'''' D''' PipeLining External Ready Control Burst D'''' PCLK ADS A31:4, SUP, DMA, D/C, LOCK Valid Valid Valid Valid Valid Invalid W/R A3:2 BE3:0 D31:0 Invalid Valid Valid Valid IN D IN D' Valid IN D'' Valid IN D''' Invalid IN D'''' WAIT BLAST DT/R DEN Non-Pipelined Request Concludes Pipelined Reads Begin. Pipelined Reads Conclude, Non-Pipelined Requests Begin. F_CX035A Figure 33. Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus 49 Bit Value Byte Order 31-23 22 0 0..0 X x reserved Function reserved 80960CA-33, -25, -16 Bus Width NWDD NWAD NXDA NRDD NRAD 21 20-19 18-17 16-12 11-10 9-8 7-3 2 1 0 0 0 X xx X xx X xxxxx X xx X xx 1 00001 ON 1 X x Disabled 1 A 1 A' D 1 PipeLining External Ready Control Burst D' PCLK ADS A31:4, SUP, DMA, D/C, LOCK Valid Valid Invalid W/R A3:2 BE3:0 Invalid Valid Valid IN D D31:0 Invalid IN D' WAIT BLAST DT/R DEN Non-Pipelined Request Concludes Pipelined Reads Begin. Pipelined Reads Conclude, Non-Pipelined Requests Begin. Figure 34. Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus 50 F_CX036A Bit Value Byte Order 31-23 22 0 0..0 X x reserved Function reserved 80960CA-33, -25, -16 Bus Width NWDD NWAD NXDA NRDD NRAD PipeLining External Ready Control Burst 21 20-19 18-17 16-12 11-10 9-8 7-3 2 1 0 0 0 32-bit 10 X xx X xxxxx X xx 0 00 0 00000 ON 1 A D D D A' D D' Disabled Enabled 1 0 D' PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK Valid InValid Valid InValid W/R A3:2 D31:0 00 01 IN D 10 11 IN D IN D Valid Valid IN D IN D InValid IN D WAIT BLAST DT/R DEN Non-pipelined Request Concludes, Pipelined Reads Begin Pipelined Reads Conclude, Non-Pipelined Requests Begin F_CX037A Figure 35. Burst, Pipelined Read Request Without Wait States, 32-Bit Bus 51 Byte Order 31-23 22 0 0..0 X x Function Bit Value A reserved reserved 80960CA-33, -25, -16 Bus Width NWDD NWAD NXDA NRDD NRAD 21 20-19 18-17 16-12 11-10 9-8 7-3 2 0 0 32-bit 10 X xx X xxxxx X xx 1 01 2 00010 ON 1 2 1 D 1 D 1 D 1 PipeLining A' D 2 External Ready Control Burst 1 0 Disabled Enabled 1 0 1 D' PCLK ADS A31:4, SUP, DMA, D/C, BE3:0, LOCK Valid Valid Invalid W/R A3:2 D31:0 Invalid 00 01 IN D 10 IN D 11 IN D Valid IN D Invalid IN D' WAIT BLAST DT/R DEN Non-pipelined request concludes, pipelined reads begin. Pipelined reads conclude, Non-pipelined requests begin. F_CX038A Figure 36. Burst, Pipelined Read Request With Wait States, 32-Bit Bus 52 Byte Order 31-23 22 0 0..0 X x Function Bit Value A reserved reserved 80960CA-33, -25, -16 Bus Width NWDD NWAD NXDA NRDD NRAD 21 20-19 18-17 16-12 11-10 9-8 7-3 2 0 0 16-bit 10 X xx X xxxxx X xx 1 01 2 00010 ON 1 2 1 D 1 D 1 D 1 PipeLining A' D External Ready Control Burst 1 0 Disabled Enabled 1 0 2 1 D' PCLK ADS A31:4, SUP, DMA, D/C, BE0/BLE, BE3/BHE, LOCK Valid Valid Invalid W/R A3:2 A3:2 = 00 or 10 A3:2 = 01 or 11 BE1/A1 D31:0 Invalid D15:0 A1=0 D15:0 A1=1 D15:0 A1=0 Valid Invalid Valid Invalid D15:0 A1=1 D15:0 D' WAIT BLAST DT/R DEN Non-pipelined request concludes, pipelined reads begin. Pipelined reads conclude, Non-pipelined requests begin. F_CX040A Figure 37. Burst, Pipelined Read Request With Wait States, 16-Bit Bus 53 Byte Order 31-23 22 0 0..0 X x Function Bit Value A reserved reserved 80960CA-33, -25, -16 Bus Width NWDD NWAD NXDA NRDD NRAD 21 20-19 18-17 16-12 11-10 9-8 7-3 2 0 0 8-bit 10 X xx X xxxxx X xx 1 01 2 00010 ON 1 2 1 D 1 D 1 D 1 A' D PipeLining External Ready Control Burst 1 0 Disabled Enabled 1 0 2 1 D' PCLK ADS A31:4, SUP, Valid DMA, D/C, LOCK Valid Invalid W/R A3:2 BE1/A1, BE0/A0 D31:0 Invalid A3:2 = 00, 01, 10, or 11 A1:0 = 00 Valid A1:0 = 01 A1:0 = 10 A1:0 = 11 D7:0 Byte 0 D7:0 Byte 1 D7:0 Byte 2 Valid D7:0 Byte 3 Invalid Invalid D7:0 D' WAIT BLAST DT/R DEN Non-pipelined request concludes, pipelined reads begin. Pipelined reads conclude, Non-pipelined requests begin. F_CX039A Figure 38. Burst, Pipelined Read Request With Wait States, 8-Bit Bus 54 80960CA-33, -25, -16 Quad-Word Write Request NWAD = 1, NWDD = 0, NWDA = 0 Ready Enabled Quad-Word Read Request NRAD = 0, NRDD = 0, NXDA = 0 Ready Enabled PCLK ADS A31:4, SUP, DMA, INST, D/C, BE3:0, LOCK Valid Valid W/R BLAST DT/R DEN READY BTERM A3:2 00 01 10 11 00 01 10 11 D1 D2 D3 WAIT D31:0 D0 D1 D2 D3 D0 F_CX041A Figure 39. Using External READY 55 80960CA-33, -25, -16 Quad-Word Write Request NWAD = 0, NWDD = 0, NWDA = 0 Ready Enabled PCLK ADS A31:4, SUP, DMA, INST, D/C, BE3:0, LOCK Valid W/R BLAST DT/R DEN READY See Note BTERM A3:2 00 01 10 11 WAIT D31:0 D0 D1 D2 D3 Note: READY adds memory access time to data transfers, whether or not the bus access is a burst access. BTERM interrupts a bus access, whether or not the bus access has more data transfers pending. Either the READY signal or the BTERM signal will terminate a bus access if the signal is asserted during the last (or only) data transfer of the bus access. Figure 40. Terminating a Burst with BTERM 56 F_CX042A 80960CA-33, -25, -16 NON-BURST A31:2, SUP, DMA, D/C, BE3:0, WAIT, DEN, DT/R D31:0, (WRITES) RESUME REQUEST ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ SUSPEND REQUEST ∼ ∼ MAY CHANGE READY BOFF ∼ ∼ ∼ ∼ ∼ ∼ BLAST BURST ∼ ∼ ∼ ∼ ∼ ∼ ∼ ∼ BURST ∼ ∼ ∼ ∼ ADS ∼ ∼ ∼ ∼ ∼ ∼ Regenerate ADS Begin Request BOFF May be asserted to suspend request BOFF may not be asserted Note: READY/BTERM must be enabled; NRAD, NRDD, NWAD, NWDD= 0 End Request BOFF may not be asserted F_CX043A Figure 41. BOFF Functional Timing 57 80960CA-33, -25, -16 Word Read Request NRAD=1, NXDA=1 Hold State Word Read Request NRAD=0, NXDA=0 Hold State PCLK2:1 ADS A31:2, SUP, DMA, D/C, BE3:0, WAIT, DEN, DT/R Valid Valid BLAST HOLD HOLDA F_CX044A Figure 42. HOLD Functional Timing 58 ∼ ∼ 80960CA-33, -25, -16 System Clock ∼ ∼ Start DMA Bus Request ∼ ∼ PCLK2:1 End of DMA Bus Request (See Note) DMA Acknowledge ADS ! (BLAST & READY & !WAIT) ∼ ∼∼ ∼∼ ∼∼ ∼∼ ∼ DACKx (All Modes) DREQx (Case 1) DREQx (Case 2) High To Prevent Next Bus Cycle tIS5 tIH5 High To Prevent Next Bus Cycle tIS5 DMA Request tIH5 Note: 1. Case 1: DREQ must deassert before DACK deasserts. Applications are Fly-By and some packing and unpacking modes in which loads are followed by loads or stores are followed by stores. 2. Case 2: DREQ must be deasserted by the second clock (rising edge) after DACK is driven high. Applications are non Fly-By transfers and adjacent load-stores or store-loads. 3. DACKx is asserted for the duration of a DMA bus request. The request may consist of multiple bus accesses (defined by ADS and BLAST. Refer to i960 Cx Microprocessor User’s Manual for “access”, “request” definitions. F_CX018A Figure 43. DREQ and DACK Functional Timing ∼ ∼ ∼ ∼ ∼ ∼ PCLK2:1 EOP 2 CLKs Min 15 CLKs Max Note: EOP has the same AC Timing Requirements as DREQ to prevent unwanted DMA requests. EOP is NOT edge triggered. EOP must be held for a minimum of 2 clock cycles then deasserted within 15 clock cycles. F_CX045A Figure 44. EOP Functional Timing 59 80960CA-33, -25, -16 PCLK2 DREQ ADS DACK TC Note: Terminal Count becomes active during the last bus request of a buffer transfer. If the last LOAD/STORE bus request is executed as multiple bus accesses, the TC will be active for the entire bus request. Refer to the i960® Cx Microprocessor User’s Manual for further information. F_CX046A ∼ ∼ ∼ ∼ Figure 45. Terminal Count Functional Timing RESET (Bus Test) Pass ~65,000 Cycles Fail 5 Cycles ∼ ∼ FAIL ∼ ∼ (Internal Self-Test) Pass Fail 102 Cycles F_CX047A Figure 46. FAIL Functional Timing 60 80960CA-33, -25, -16 0 4 8 12 16 20 24 Word Offset 0 1 2 3 4 5 6 Byte Offset Short Request (Aligned) Byte, Byte Requests Short-Word Load/Store Short Request (Aligned) Byte, Byte Requests Word Request (Aligned) Byte, Short, Byte, Requests Word Load/Store Short, Short Requests Byte, Short, Byte Requests One Double-Word Burst (Aligned) Byte, Short, Word, Byte Requests Short, Word, Short Requests Double-Word Load/Store Byte, Word, Short, Byte Requests Word, Word Requests One Double-Word Request (Aligned) F_CX048A Figure 47. A Summary of Aligned and Unaligned Transfers for Little Endian Regions 61 80960CA-33, -25, -16 0 4 8 12 16 20 24 1 2 3 4 5 6 Byte Offset Word Offset 0 One Three-Word Request (Aligned) Byte, Short, Word, Word, Byte Requests Triple-Word Load/Store Short, Word, Word, Short Requests Byte, Word, Word, Short, Byte Requests Word, Word, Word Requests Word, Word, Word Requests Word, Word, Word Requests One Four-Word Request (Aligned) Byte, Short, Word, Word, Word, Byte Requests Quad-Word Load/Store Short, Word, Word, Word, Short Requests Byte, Word, Word, Word, Short, Byte Requests Word, Word, Word, Word Requests DoubleWord, DoubleWord, Requests F_CX049A Figure 48. A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued) 62 80960CA-33, -25, -16 Write Request NWAD=2, NXDA = 0 Ready Disabled Idle Bus (not in Hold Acknowledge state) Read Request NWAD=2, NXDA = 0 Ready Disabled PCLK ADS A31:4, SUP, DMA, INST, D/C, BE3:0 Valid Valid LOCK Valid Valid W/R BLAST DT/R DEN A3:2 Valid Valid WAIT D31:0 Out In READY, BTERM F_CX050A Figure 49. Idle Bus Operation 63 80960CA-33, -25, -16 7.0 REVISION HISTORY This data sheet supersedes data sheet 270727-005. Specification changes in the 80960CA data sheet are a result of design changes. The sections significantly changed since the previous revision are: Section Last Rev. Description Table 11. 80960CA PGA Package Thermal Characteristics -005 Removed references and notes pertaining to θJ-CAP and θJ-PIN. Table 12. 80960CA PQFP package Thermal Characteristics -005 Removed references and notes pertaining to θJL and θJB. 3.3 80960CA Mechanical Data -005 Removed section containing information on Package Dimensions. Moved section header to encompass Pinout tables and diagrams. 3.7 Suggested Sources for 80960CA Accessories -005 Removed entire section containing information about 80960CA accessories. Tables 16, 17 and18 80960CA AC Characteristics (33-, 25- and 16MHz, respectively) -005 All TTVEL maximum deleted. TNHQX and TEHTV minimums changed: -005 WAS: IS: TNHQX (N+1)*T-6 (N+1)*T-8 TEHTV T/2 - 6 T/2 - 7 All timing diagrams and waveforms have been redrawn to conform to consistent format. Data sheet formatting has been changed to conform to corporate standards. Specific formatting changes are not itemized in this revision history. 64