INTEL 83C51FB

8XC51FX
CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLERS
Commercial/Express
87C51FA/83C51FA/80C51FA/87C51FB/83C51FB/87C51FC/83C51FC
*See Table 1 for Proliferation Options
Y
Y
Y
Y
High Performance CHMOS
EPROM/ROM/CPU
Y
32 Programmable I/O Lines
Y
7 Interrupt Sources
12/24/33 MHz Operation
Y
Four Level Interrupt Priority
Three 16-Bit Timer/Counters
Y
Programmable Serial Channel with:
Ð Framing Error Detection
Ð Automatic Address Recognition
Y
TTL Compatible Logic Levels
Y
64K External Program Memory Space
64K External Data Memory Space
Programmable Counter Array with:
Ð High Speed Output,
Ð Compare/Capture,
Ð Pulse Width Modulator,
Ð Watchdog Timer Capabilities
Y
Up/Down Timer/Counter
Y
Y
Three Level Program Lock System
Y
Y
8K/16K/32K On-Chip Program Memory
MCSÉ 51 Controller Compatible
Instruction Set
Y
Y
256 Bytes of On-Chip Data RAM
Power Saving Idle and Power Down
Modes
Y
Improved Quick Pulse Programming
Algorithm
Y
ONCE (On-Circuit Emulation) Mode
Y
Extended Temperature Range Except
for 33 MHz Offering ( b 40§ C to a 85§ C)
Y
Boolean Processor
MEMORY ORGANIZATION
ROM/
EPROM
Bytes
RAM
Bytes
80C51FA
8K
256
80C51FA
16K
256
80C51FA
32K
256
ROM
Device
EPROM
Version
ROMLESS
Version
83C51FA
87C51FA
83C51FB
87C51FB
83C51FC
87C51FC
These devices can address up to 64 Kbytes of external program/data memory.
The Intel 87C51FA/8XC51FB/8XC51FC is a single-chip control oriented microcontroller which is fabricated on
Intel’s reliable CHMOS III-E technology. The Intel 83C51FA/80C51FA is fabricated on CHMOS III technology.
Being a member of the MCSÉ 51 controller family, the 8XC51FA/8XC51FB/8XC51FC uses the same powerful
instruction set, has the same architecture, and is pin-for-pin compatible with the existing MCS 51 controller
products. The 8XC51FA/8XC51FB/8XC51FC is an enhanced version of the 8XC52/8XC54/8XC58. Its added
features make it an even more powerful microcontroller for applications that require Pulse Width Modulation,
High Speed I/O and up/down counting capabilities such as motor control.
For the remainder of this document, the 8XC51FA, 8XC51FB, 8XC51FC will be referred to as the 8XC51FX,
unless information applies to a specific device.
*Other brands and names are the property of their respective owners.
Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or
copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make
changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata.
COPYRIGHT © INTEL CORPORATION, 1996
April 1996
Order Number: 272322-004
8XC51FX
Table 1. Proliferation Options
Standard*1
-1
-2
-24
-33
80C51FA
X
X
X
X
X
83C51FA
X
X
X
X
X
87C51FA
X
X
X
X
X
83C51FB
X
X
X
X
X
87C51FB
X
X
X
X
X
83C51FC
X
X
X
X
X
87C51FC
X
X
X
X
X
NOTES:
*1
3.5
-1
3.5
-2
0.5
-24
3.5
-33
3.5
MHz
MHz
MHz
MHz
MHz
to
to
to
to
to
12
16
12
24
33
MHz;
MHz;
MHz;
MHz;
MHz;
5V
5V
5V
5V
5V
g 20%
g 20%
g 20%
g 20%
g 10%
272322 – 1
Figure 1. 8XC51FX Block Diagram
2
8XC51FX
PROCESS INFORMATION
PACKAGES
The 87C51FA/8XC51FB/8XC51FC is manufactured
on P629.0, a CHMOS III-E process. Additional process and reliability information is available in Intel’s
Components Quality and Reliability Handbook, Order No. 210997.
Part
Prefix
Package Type
8XC51FX
P
D
N
S
40-Pin Plastic DIP
40-Pin CERDIP
44-Pin PLCC
44-Pin QFP
272322 – 23
PLCC
272322 – 2
DIP
272322 – 24
*Do not connect Reserved Pins.
QFP
Figure 2. Pin Connections
3
8XC51FX
PIN DESCRIPTIONS
In addition, Port 1 serves the functions of the following special features of the 8XC51FX:
VCC: Supply voltage.
Port Pin
VSS: Circuit ground.
VSS1: Secondary ground (not on DIP devices or any
83C51FA/80C51FA device). Provided to reduce
ground bounce and improve power supply by-passing.
NOTE:
This pin is not a substitution for the VSS pin. (Connection not necessary for proper operation.)
Port 0: Port 0 is an 8-bit, open drain, bidirectional
I/O port. As an output port each pin can sink several
LS TTL inputs. Port 0 pins that have 1’s written to
them float, and in that state can be used as high-impedance inputs.
P1.0
T2 (External Count Input to Timer/
Counter 2), Clock Out
P1.1
T2EX (Timer/Counter 2 Capture/
Reload Trigger and Direction Control)
ECI (External Count Input to the PCA)
P1.2
P1.3
CEX0 (External I/O for Compare/
Capture Module 0)
P1.4
CEX1 (External I/O for Compare/
Capture Module 1)
CEX2 (External I/O for Compare/
Capture Module 2)
CEX3 (External I/O for Compare/
Capture Module 3)
CEX4 (External I/O for Compare/
Capture Module 4)
P1.5
P1.6
P1.7
Port 0 is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emitting 1’s, and can source and
sink several LS TTL inputs.
Port 0 also receives the code bytes during EPROM
programming, and outputs the code bytes during
program verification. External pullup resistors are required during program verification.
Port 1: Port 1 is an 8-bit bidirectional I/O port with
internal pullups. The Port 1 output buffers can drive
LS TTL inputs. Port 1 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 1
pins that are externally pulled low will source current
(IIL, on the data sheet) because of the internal pullups.
Alternate Function
Port 1 receives the low-order address bytes during
EPROM programming and verifying.
Port 2: Port 2 is an 8-bit bidirectional I/O port with
internal pullups. The Port 2 output buffers can drive
LS TTL inputs. Port 2 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 2
pins that are externally pulled low will source current
(IIL, on the data sheet) because of the internal pullups.
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @ DPTR). In this application it
uses strong internal pullups when emitting 1’s. During accesses to external Data Memory that use 8-bit
addresses (MOVX @ Ri), Port 2 emits the contents of
the P2 Special Function Register.
Some Port 2 pins receive the high-order address bits
during EPROM programming and program verification.
Port 3: Port 3 is an 8-bit bidirectional I/O port with
internal pullups. The Port 3 output buffers can drive
LS TTL inputs. Port 3 pins that have 1’s written to
them are pulled high by the internal pullups, and in
that state can be used as inputs. As inputs, Port 3
pins that are externally pulled low will source current
(IIL, on the data sheet) because of the pullups.
4
8XC51FX
Port 3 also serves the functions of various special
features of the MCS-51 Family, as listed below:
Port Pin
Alternate Function
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
RXD (serial input port)
TXD (serial output port)
INT0 (external interrupt 0)
INT1 (external interrupt 1)
T0 (Timer 0 external input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
RD (external data memory read strobe)
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device. The port pins will be driven to their reset condition when a minimum VIH1 voltage is applied whether the oscillator is running or not. An internal pulldown resistor permits a power-on reset with only a
capacitor connected to VCC.
ALE: Address Latch Enable output pulse for latching
the low byte of the address during accesses to external memory. This pin (ALE/PROG) is also the
program pulse input during EPROM programming for
the 87C51FX.
In normal operation ALE is emitted at a constant
rate of (/6 the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
When the 8XC51FX is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external Data Memory.
EA/VPP: External Access enable. EA must be
strapped to VSS in order to enable the device to
fetch code from external Program Memory locations
0000H to 0FFFH. Note, however, that if either of the
Program Lock bits are programmed, EA will be internally latched on reset.
EA should be strapped to VCC for internal program
executions.
This pin also receives the programming supply voltage (VPP) during EPROM programming.
XTAL1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of a inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Application Note AP-155, ‘‘Oscillators for Microcontrollers.’’
If desired, ALE operation can be disabled by setting
bit 0 of SFR location 8EH. With this bit set, the pin is
weakly pulled high. However, the ALE disable feature will be suspended during a MOVX or MOVC instruction, idle mode, power down mode and ICE
mode. The ALE disable feature will be terminated by
reset. When the ALE disable feature is suspended or
terminated, the ALE pin will no longer be pulled up
weakly. Setting the ALE-disable bit has no affect if
the microcontroller is in external execution mode.
To drive the device from an external clock source,
XTAL1 should be driven, while XTAL2 floats, as
shown in Figure 4. There are no requirements on the
duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
Throughout the remainder of this data sheet, ALE
will refer to the signal coming out of the ALE/PROG
pin, and the pin will be referred to as the ALE/PROG
pin.
An external oscillator may encounter as much as a
100 pF load at XTAL1 when it starts up. This is due
to interaction between the amplifier and its feedback
capacitance. Once the external signal meets the VIL
and VIH specifications the capacitance will not exceed 20 pF.
PSEN: Program Store Enable is the read strobe to
external Program Memory.
5
8XC51FX
Down is the last instruction executed. The on-chip
RAM and Special Function Registers retain their values until the Power Down mode is terminated.
On the 8XC51FX either hardware reset or external
interrupt can cause an exit from Power Down. Reset
redefines all the SFRs but does not change the onchip RAM. An external interrupt allows both the
SFRs and the on-chip RAM to retain their values.
272322 – 3
C1, C2 e 30 pF g 10 pF for Crystals
For Ceramic Resonators, contact resonator manufacturer.
To properly terminate Power Down the reset or external interrupt should not be executed before VCC is
restored to its normal operating level and must be
held active long enough for the oscillator to restart
and stabilize (normally less than 10 ms).
Figure 3. Oscillator Connections
272322 – 4
Figure 4. External Clock Drive Configuration
With an external interrupt, INT0 or INT1 must be enabled and configured as level-sensitive. Holding the
pin low restarts the oscillator but bringing the pin
back high completes the exit. Once the interrupt is
serviced, the next instruction to be executed after
RETI will be the one following the instruction that put
the device into Power Down.
DESIGN CONSIDERATION
# Ambient light is known to affect the internal RAM
IDLE MODE
The user’s software can invoke the Idle Mode. When
the microcontroller is in this mode, power consumption is reduced. The Special Function Registers and
the onboard RAM retain their values during Idle, but
the processor stops executing instructions. Idle
Mode will be exited if the chip is reset or if an enabled interrupt occurs. The PCA timer/counter can
optionally be left running or paused during Idle
Mode.
POWER DOWN MODE
contents during operation. If the 87C51FX application requires the part to be run under ambient
lighting, an opaque label should be placed over
the window to exclude light.
# When the idle mode is terminated by a hardware
reset, the device normally resumes program execution, from where it left off, up to two machine
cycles before the internal reset algorithm takes
control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins
is not inhibited. To eliminate the possibility of an
unexpected write when Idle is terminated by reset, the instruction following the one that invokes
Idle should not be one that writes to a port pin or
to external memory.
To save even more power, a Power Down mode can
be invoked by software. In this mode, the oscillator
is stopped and the instruction that invoked Power
Table 2. Status of the External Pins during Idle and Power Down
Program
Memory
ALE
PSEN
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power Down
Internal
0
0
Data
Data
Data
Data
Power Down
External
0
0
Float
Data
Data
Data
Mode
PORT0
PORT1
PORT2
PORT3
NOTE:
For more detailed information on the reduced power modes refer to current Embedded Microcontrollers and Processors
Handbook Volume I, and Application Note AP-252 (Embedded Applications Handbook), ‘‘Designing with the 80C51BH.’’
6
8XC51FX
ONCE MODE
The ONCE (‘‘On-Circuit Emulation’’) Mode facilitates
testing and debugging of systems using the
8XC51FX without the 8XC51FX having to be removed from the circuit. The ONCE Mode is invoked
by:
1) Pull ALE low while the device is in reset and
PSEN is high;
2) Hold ALE low as RST is deactivated.
While the device is in ONCE Mode, the Port 0 pins
float, and the other port pins and ALE and PSEN are
weakly pulled high. The oscillator circuit remains active. While the 8XC51FX is in this mode, an emulator
or test CPU can be used to drive the circuit. Normal
operation is restored when a normal reset is applied.
8XC51FX EXPRESS
The Intel EXPRESS system offers enhancements to
the operational specifications of the MCS-51 family
of microcontrollers. These EXPRESS products are
designed to meet the needs of those applications
whose operating requirements exceed commercial
standards.
The EXPRESS program includes the commercial
standard temperature range with burn-in and an extended temperature range with or without burn-in.
With the commercial standard temperature range,
operational characteristics are guaranteed over the
temperature range of 0§ C to 70§ C. With the extended temperature range option, operational characteristics are guaranteed over the range of b 40§ C to
a 85§ C.
The optional burn-in is dynamic for a minimum time
of 168 hours at 125§ C with VCC e 6.9V g 0.25V,
following guidelines in MlL-STD-883, Method 1015.
Package types and EXPRESS versions are identified
by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 3.
For the extended temperature range option, this
data sheet specifies the parameters which deviate
from their commercial temperature range limits.
NOTE:
Intel offers Express Temperature specifications for all 8XC51FX speed options except
for 33 MHz.
Table 3. Prefix Identification
Prefix
Package Type
Temperature Range
Burn-In
D
Cerdip
Commercial
No
N
PLCC
Commercial
No
P
Plastic
Commercial
No
S
QFP
Commercial
No
LD
Cerdip
Extended
Yes
LN
PLCC
Extended
Yes
LP
Plastic
Extended
Yes
LS
QFP
Extended
Yes
TD
Cerdip
Extended
No
TN
PLCC
Extended
No
TP
Plastic
Extended
No
TS
QFP
Extended
No
NOTE:
Contact distributor or local sales office to match EXPRESS prefix with proper device.
EXAMPLES:
P87C51FC indicates 87C51FC in a plastic package and specified for commercial temperature range, without burn-in.
LD87C51FC indicates 87C51FC in a cerdip package and specified for extended temperature range with burn-in.
7
8XC51FX
ABSOLUTE MAXIMUM RATINGS*
NOTICE: This data sheet contains preliminary information on new products in production. It is valid for
the devices indicated in the revision history. The
specifications are subject to change without notice.
Ambient Temperature Under Bias À b 40§ C to a 85§ C
Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 65§ C to a 150§ C
Voltage on EA/VPP Pin to VSS ÀÀÀÀÀÀÀ0V to a 13.0V
Voltage on Any Other Pin to VSS ÀÀ b 0.5V to a 6.5V
IOL per I/O Pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA
*WARNING: Stressing the device beyond the ‘‘Absolute
Maximum Ratings’’ may cause permanent damage.
These are stress ratings only. Operation beyond the
‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’
may affect device reliability.
Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W
(based on PACKAGE heat transfer limitations, not
device power consumption)
OPERATING CONDITIONS
Symbol
TA
VCC
fOSC
Description
Min
Max
Units
Ambient Temperature Under Bias
Commercial
Express
0
b 40
a 70
a 85
§C
Supply Voltage
8XC51FX-33
All Others
4.5
4.0
5.5
6.0
V
Oscillator Frequency
8XC51FX
8XC51FX-1
8XC51FX-2
8XC51FX-24
8XC51FX-33
3.5
3.5
0.5
3.5
3.5
12
16
12
24
33
MHz
DC CHARACTERISTICS
(Over Operating Conditions)
All parameter values apply to all devices unless otherwise indicated.
Symbol
Parameter
Min
Typical
(Note 4)
Max
Units
b 0.5
0.2 VCC b 0.1
V
Test Conditions
VIL
Input Low Voltage
VIL1
Input Low Voltage EA
0
0.2 VCC b 0.3
V
VIH
Input High Voltage
(Except XTAL1, RST)
0.2 VCC a 0.9
VCC a 0.5
V
VIH1
Input High Voltage
(XTAL1, RST)
0.7 VCC
VCC a 0.5
V
VOL
Output Low Voltage (Note 5)
(Ports 1, 2 and 3)
0.3
0.45
1.0
V
IOL e 100 mA
IOL e 1.6 mA (Note 1)
IOL e 3.5 mA
Output Low Voltage (Note 5)
(Port 0, ALE/PROG, PSEN)
0.3
0.45
1.0
V
IOL e 200 mA
IOL e 3.2 mA (Note 1)
IOL e 7.0 mA
IOH e b 10 mA
IOH e b 30 mA (Note 2)
IOH e b 60 mA
VOL1
VOH
VOH1
Output High Voltage
(Ports 1, 2 and 3
ALE/PROG and PSEN)
VCC b 0.3
VCC b 0.7
VCC b 1.5
V
Output High Voltage
(Port 0 in External Bus Mode)
VCC b 0.3
VCC b 0.7
VCC b 1.5
V
83C51FA/80C51FA (Express)
IIL
8
Logical 0 Input Current
(Ports 1, 2 and 3)
b 50
mA
IOH
IOH
IOH
IOH
e
e
e
e
b 200 mA
b 3.2 mA (Note 2)
b 7.0 mA
b 6.0 mA
VIN e 0.45V
8XC51FX
DC CHARACTERISTICS
(Over Operating Conditions)
All parameter values apply to all devices unless otherwise indicated. (Continued)
Symbol
Parameter
ILI
Input leakage Current (Port 0)
ITL
Logical 1 to 0 Transition Current
(Ports 1, 2 and 3)
Express
Commercial
RRST
RST Pulldown Resistor
CIO
Pin Capacitance
ICC
Power Supply Current:
Active Mode
At 12 MHz (Figure 5)
At 16 MHz
At 24 MHz
At 33 MHz
Idle Mode
At 12 MHz (Figure 5)
At 16 MHz
At 24 MHz
At 33 MHz
Power Down Mode
Min
Typical
(Note 4)
Max
Units
Test Conditions
g 10
mA
VIN e VIL or VIH
VIN e 2V
40
b 750
b 650
mA
225
KX
10
pF
@ 1MHz,
25§ C
(Note 3)
15
20
28
35
30
38
56
56
mA
mA
mA
mA
5
6
7
7
5
7.5
9.5
13.5
15
75
mA
mA
mA
mA
mA
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause noise pulses above 0.4V to be superimposed on the VOLs of ALE and
Ports 1, 2 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins
change from 1 to 0. In applications where capacitance loading exceeds 100 pF, the noise pulses on these signals may
exceed 0.8V. It may be desirable to qualify ALE or other signals with a Schmitt Trigger, or CMOS-level input logic.
2. Capacitive loading on Ports 0 and 2 cause the VOH on ALE and PSEN to drop below the 0.9 VCC specification when the
address lines are stabilizing.
3. See Figures 6–9 for test conditions. Minimum VCC for power down is 2V.
4. Typicals are based on limited number of samples, and are not guaranteed. The values listed are at room temperature and 5V.
5. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
10 mA
Maximum IOL per port pin:
Maximum IOL per 8-bit port Port 0:
26 mA
Ports 1, 2, and 3:
15 mA
71 mA
Maximum total IOL for all output pins:
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
272322 – 5
Note:
ICC max at 33 MHz is at 5V g 10% VCC, while ICC max at 24 MHz and below is at 5V g 20% VCC.
Figure 5. 8XC51FA/FB/FC ICC vs Frequency
9
8XC51FX
272322 – 6
All other pins disconnected
TCLCH e TCHCL e 5 ns
272322 – 7
All other pins disconnected
TCLCH e TCHCL e 5 ns
Figure 6. ICC Test Condition, Active Mode
Figure 7. ICC Test Condition Idle Mode
272322 – 8
All other pins disconnected
Figure 8. ICC Test Condition, Power Down Mode.
VCC e 2.0V to 6.0V.
272322 – 19
Figure 9. Clock Signal Waveform for ICC Tests in Active and Idle Modes. TCLCH e TCHCL e 5 ns.
10
8XC51FX
L: Logic level LOW, or ALE
EXPLANATION OF THE AC SYMBOLS
P: PSEN
Q: Output Data
Each timing symbol has 5 characters. The first character is always a ‘T’ (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
R: RD signal
T: Time
V: Valid
W: WR signal
A: Address
X: No longer a valid logic level
Z: Float
C: Clock
D: Input Data
H: Logic level HIGH
For example,
I: Instruction (program memory contents)
TAVLL e Time from Address Valid to ALE Low
TLLPL e Time from ALE Low to PSEN Low
AC CHARACTERISTICS
(Over Operating Conditions, Load Capacitance for Port 0, ALE/PROG and
PSEN e 100 pF, Load Capacitance for All Other Outputs e 80 pF)
EXTERNAL MEMORY CHARACTERISTICS
All parameter values apply to all devices unless otherwise indicated. In this table, 8XC51FX refers to
8XC51FX, 8XC51FX-1 and 8XC51FX-2.
Oscillator
Symbol
Parameter
12 MHz
24 MHz
33 MHz
Min Max Min Max Min Max
1/TCLCL Oscillator Frequency
8XC51FX
8XC51FX-1
8XC51FX-2
8XC51FX-24
8XC51FX-33
TLHLL
ALE Pulse Width
TAVLL
Address Valid to ALE Low
8XC51FX
8XC51FX-24
8XC51FX-33
TLLAX
TLLIV
TLLPL
127
ALE Low to Valid Instr In
8XC51FX
8XC51FX-24
8XC51FX-33
3.5
3.5
0.5
3.5
3.5
12
16
12
24
33
5
TCLCL b 40
TCLCL b 30
TCLCL b 25
ns
ns
ns
5
TCLCL b 30
TCLCL b 25
ns
ns
12
4TCLCL b 100
4TCLCL b 75
4TCLCL b 65
91
56
TPLPH
PSEN Pulse Width
205
TPLIV
PSEN Low to Valid Instr In
8XC51FX
8XC51FX-24
8XC51FX-33
12
80
5
TCLCL b 30
TCLCL b 25
46
3TCLCL b 45
35
35
0
0
0
ns
ns
ns
ns
ns
3TCLCL b 105
3TCLCL b 90
3TCLCL b 55
145
0
MHz
ns
234
53
Input Instr Hold after PSEN
Max
2TCLCL b 40
12
Address Hold After ALE Low
8XC51FX/-24
53
8XC51FX-33
Min
21
43
ALE Low to PSEN Low
8XC51FX/-24
8XC51FX-33
TPXIX
43
Units
Variable
ns
ns
ns
ns
11
8XC51FX
EXTERNAL MEMORY CHARACTERISTICS (Continued)
All parameter values apply to all devices unless otherwise indicated
Oscillator
Symbol
Parameter
12 MHz
24 MHz
33 MHz
Min Max Min Max Min Max
TPXIZ
TAVIV
TPLAZ
Input Instr Float After PSEN
8XC51FX
8XC51FX-24
8XC51FX-33
Min
59
312
PSEN Low to Address Float
5
ns
ns
ns
71
5TCLCL b 105
5TCLCL b 80
ns
ns
10
ns
103
10
10
Max
TCLCL-25
TCLCL-20
TCLCL-25
21
Address to Valid Instr In
8XC51FX/-24
8XC51FX-33
Units
Variable
10
TRLRH RD Pulse Width
400
150
82
6TCLCL b 100
ns
TWLWH WR Pulse Width
400
150
82
6TCLCL b 100
ns
TRLDV RD Low to Valid Data In
8XC51FX
8XC51FX-24
8XC51FX-33
TRHDX Data Hold After RD
113
61
0
TRHDZ Data Float After RD
8XC51FX/24
8XC51FX-33
TLLDV
TQVWX Data Valid to WR Transition
8XC51FX
8XC51FX-24/33
TWHQX Data Hold After WR
8XC51FX
8XC51FX-24
8XC51FX-33
TQVWH Data Valid to WR High
8XC51FX
8XC51FX-24/33
0
23
200 300
75
ns
ns
243
150
8TCLCL b 150
8TCLCL b 90
ns
ns
285
180
9TCLCL b 165
9TCLCL b 90
ns
ns
140 3TCLCL b 50 3TCLCL a 50
ns
175
41
46
4TCLCL b 130
4TCLCL b 90
4TCLCL b 75
ns
ns
ns
0
TCLCL b 50
TCLCL b 30
ns
ns
3
TCLCL b 50
TCLCL b 35
TCLCL b 27
ns
ns
ns
142
7TCLCL b 150
7TCLCL b 70
ns
ns
77
33
12
33
7
433
222
0
0
0
123
12
ns
2TCLCL b 60
2TCLCL b 25
203
TWHLH RD or WR High to ALE High
8XC51FX
43
8XC51FX-24
8XC51FX-33
ns
ns
ns
35
585
TRLAZ RD Low to Address Float
12
0
517
TAVDV Address to Valid Data In
8XC51FX
8XC51FX-24/33
TAVWL Address to RD or WR Low
8XC51FX
8XC51FX-24
8XC51FX-33
0
107
ALE Low to Valid Data In
8XC51FX
8XC51FX-24/33
TLLWL ALE Low to RD or WR Low
5TCLCL b 165
5TCLCL b 95
5TCLCL b 90
252
71
5
55
TCLCL b 40
TCLCL b 30
TCLCL b 25
0
ns
TCLCL a 40
TCLCL a 30
TCLCL a 25
ns
ns
ns
8XC51FX
EXTERNAL PROGRAM MEMORY READ CYCLE
272322 – 9
EXTERNAL DATA MEMORY READ CYCLE
272322 – 10
EXTERNAL DATA MEMORY WRITE CYCLE
272322 – 11
13
8XC51FX
SERIAL PORT TIMINGÐSHIFT REGISTER MODE
Test Conditions:
Over Operating Conditions; Load Capacitance e 80 pF
Oscillator
Symbol
Parameter
12 MHz
Min
TXLXL
Serial Port
Clock
Cycle Time
TQVXH Output Data
Setup to Clock
Rising Edge
TXHQX
Output Data
Hold After Clock
Rising Edge
8XC51FX
8XC51FX-24/33
TXHDX
Input Data Hold
After Clock
Rising Edge
TXHDV
Clock Rising
Edge to Input
Data Valid
Max
24 MHz
Min
Max
33 MHz
Min
Max
Units
Variable
Min
Max
1
0.50
0.36
12TCLCL
ms
700
284
167
10TCLCL b 133
ns
34
10
2TCLCL b 117
2TCLCL b 50
ns
ns
0
ns
50
0
700
0
0
283
167
10TCLCL b 133
ns
SHIFT REGISTER MODE TIMING WAVEFORMS
272322 – 12
14
8XC51FX
EXTERNAL CLOCK DRIVE
Symbol
Parameter
Min
Max
Units
1/TCLCL
Oscillator Frequency
8XC51FX
8XC51FX-1
8XC51FX-2
8XC51FX-24
8XC51FX-33
3.5
3.5
0.5
3.5
3.5
12
16
12
24
33
MHz
MHz
MHz
MHz
MHz
MHz
High Time
8XC51FX-24/33
20
0.35 TOSC
0.65 TOSC
ns
ns
Low Time
8XC51FX-24/33
20
0.35 TOSC
0.65 TOSC
ns
ns
TCHCX
TCLCX
TCLCH
Rise Time
8XC51FX-24
8XC51FX-33
20
10
5
ns
ns
ns
TCHCL
Fall Time
8XC51FX-24
8XC51FX-33
20
10
5
ns
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORM
272322 – 13
AC TESTING INPUT, OUTPUT WAVEFORMS
272322 – 14
AC Inputs during testing are driven at VCC b 0.5V for a Logic ‘‘1’’
and 0.45V for a Logic ‘‘0’’. Timing measurements are made at VIH
min for a Logic ‘‘1’’ and VOL max for a Logic ‘‘0’’.
FLOAT WAVEFORMS
272322 – 15
For timing purposes a port pin is no longer floating when a
100 mV change from load voltage occurs, and begins to float
when a 100 mV change from the loaded VOH/VOL level occurs.
IOL/IOH e g 20 mA.
15
8XC51FX
PROGRAMMING THE EPROM/OTP
To be programmed, the part must be running with a
4 to 6 MHz oscillator. (The reason the oscillator
needs to be running is that the internal bus is being
used to transfer address and program data to appropriate internal EPROM locations.) The address of an
EPROM location to be programmed is applied to
Port 1 and pins P2.0 - P2.4 of Port 2, while the code
byte to be programmed into that location is applied
to Port 0. The other Port 2 and 3 pins, RST PSEN,
and EA/VPP should be held at the ‘‘Program’’ levels
indicated in Table 4. ALE/PROG is pulsed low to
program the code byte into the addressed EPROM
location. The setup is shown in Figure 10.
Normally EA/VPP is held at logic high until just before ALE/PROG is to be pulsed. Then EA/VPP is
raised to VPP, ALE/PROG is pulsed low, and then
EA/VPP is returned to a valid high voltage. The voltage on the EA/VPP pin must be at the valid EA/VPP
high level before a verify is attempted. Waveforms
and detailed timing specifications are shown in later
sections of this data sheet.
NOTE:
# EA/VPP pin must not be allowed to go above the
maximum specified VPP level for any amount of
time. Even a narrow glitch above that voltage level can cause permanent damage to the device.
The VPP source should be well regulated and free
of glitches.
Table 4. EPROM Programming Modes
RST
PSEN
ALE/
PROG
EA/
VPP
Program Code Data
H
L
ß
Verify Code Data
H
L
H
Program Encryption
Array Address 0–3FH
H
L
Program Lock
Bits
Bit 1
H
Bit 2
H
Mode
Bit 3
Read Signature Byte
P2.6
P2.7
P3.3
P3.6
P3.7
12.75V
L
H
H
H
H
H
L
L
L
H
H
ß
12.75V
L
H
H
L
H
L
ß
12.75V
H
H
H
H
H
L
ß
12.75V
H
H
H
L
L
H
L
ß
12.75V
H
L
H
H
L
H
L
H
H
L
L
L
L
L
272322 – 20
*See Table 4 for proper input on these pins
Figure 10. Programming the EPROM
16
8XC51FX
PROGRAMMING ALGORITHM
Refer to Table 4 and Figures 10 and 11 for address,
data, and control signals set up. To program the
87C51FX the following sequence must be exercised.
1. Input the valid address on the address lines.
2. Input the appropriate data byte on the data
lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP from VCC to 12.75V g 0.25V.
5. Pulse, ALE/PROG 5 times for the EPROM array, and 25 times for the encryption table and
the lock bits.
Repeat 1 through 5 changing the address and data
for the entire array or until the end of the object file is
reached.
PROGRAM VERIFY
Program verify may be done after each byte or block
of bytes is programmed. In either case a complete
verify of the programmed array will ensure reliable
programming of the 87C51FX.
The lock bits cannot be directly verified. Verification
of the lock bits is done by observing that their features are enabled.
272322 – 21
Figure 11. Programming Signals Waveforms
The 87C51FX program lock system, when programmed, protects the onboard program against
software piracy.
lock-bit and encryption array are programmed by the
factory. The encryption array is not available without
the lock bit. For the lock bit to be programmed, the
user must submit an encryption table. The 83C51FA
does not have protection features.
The 83C51FX has a one-level program lock system
and a 64-byte encryption table. See line 2 of Table
5. If program protection is desired, the user submits
the encryption table with their code, and both the
The 87C51FX has a 3-level program lock system
and a 64-byte encryption array. Since this is an
EPROM device, all locations are user-programmable. See Table 5.
ROM and EPROM Lock System
Table 5. Program Lock Bits and the Features
Program Lock Bits
ProtectIon Type
LB1
LB2
LB3
1
U
U
U
No Program Lock features enabled. (Code verify will still be encrypted by the
Encryption Array if programmed.)
2
P
U
U
MOVC instructions executed from external program memory are disabled from
fetching code bytes from internal memory, EA is sampled and latched on Reset, and
further programming of the EPROM is disabled.
3
P
P
U
Same as 2, also verify is disabled.
4
P
P
P
Same as 3, also external execution is disabled.
Any other combination of the lock bits is not defined.
17
8XC51FX
Encryption Array
Within the EPROM array are 64 bytes of Encryption
Array that are initially unprogrammed (all 1’s). Every
time that a byte is addressed during a verify, 6 address lines are used to select a byte of the Encryption Array. This byte is then exclusive-NOR’ed
(XNOR) with the code byte, creating an Encryption
Verify byte. The algorithm, with the array in the unprogrammed state (all 1’s), will return the code in its
original, unmodified form. For programming the Encryption Array, refer to Table 4 (Programming the
EPROM).
When using the encryption array, one important factor needs to be considered. If a code byte has the
value 0FFH, verifying the byte will produce the encryption byte value. lf a large block ( l 64 bytes) of
code is left unprogrammed, a verification routine will
display the contents of the encryption array. For this
reason all unused code bytes should be programmed with some value other than 0FFH, and not
all of them the same value. This will ensure maximum program protection.
Program Lock Bits
The 87C51FX has 3 programmable lock bits that
when programmed according to Table 5 will provide
different levels of protection for the on-chip code
and data.
Erasing the EPROM also erases the encryption array and the program lock bits, returning the part to
full functionality.
Reading the Signature Bytes
The 87C51FX has 3 signature bytes in locations
30H, 31H, and 60H. The 83C51FA has 2 signature
18
bytes in locations 30H and 31H. To read these bytes
follow the procedure for EPROM verify, but activate
the control lines provided in Table 4 for Read Signature Byte.
Location
Device
Contents
30H
All
89H
31H
All
58H
60H
83C51FA
7AH/FAH
87C51FA
FAH
83C51FB
7BH/FBH
87C51FB
FBH
83C51FC
7CH/FCH
87C51FC
FCH
Erasure Characteristics (Windowed
Packages Only)
Erasure of the EPROM begins to occur when the
chip is exposed to light with wavelength shorter than
approximately 4,000 Angstroms. Since sunlight and
fluorescent lighting have wavelengths in this range,
exposure to these light sources over an extended
time (about 1 week in sunlight, or 3 years in roomlevel fluorescent lighting) could cause inadvertent
erasure. If an application subjects the device to this
type of exposure, it is suggested that an opaque label be placed over the window.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm. Exposing the
EPROM to an ultraviolet lamp of 12,000 mW/cm rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure leaves all the EPROM Cells in a 1’s state.
8XC51FX
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(TA e 21§ C to 27§ C; VCC e 5V g 20%; VSS e 0V)
Symbol
Parameter
Min
Max
VPP
Programming Supply Voltage
12.5
13.0
V
IPP
Programming Supply Current
75
mA
6
MHz
4
Units
1/TCLCL
Oscillator Frequency
TAVGL
Address Setup to PROG Low
TGHAX
Address Hold after PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold after PROG
48TCLCL
TEHSH
P2.7 (ENABLE) High to VPP
48TCLCL
TSHGL
VPP Setup to PROG Low
10
ms
TGHSL
VPP Hold after PROG
10
ms
TGLGH
PROG Width
90
TAVQV
Address to Data Valid
TELQV
ENABLE Low to Data Valid
TEHQZ
Data Float after ENABLE
0
TGHGL
PROG High to PROG Low
10
48TCLCL
110
ms
48TCLCL
48TCLCL
48TCLCL
ms
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
272322 – 18
NOTE:
*5 pulses for the EPROM array, 25 pulses for the encryption table and lock bits.
19
8XC51FX
Thermal Impedance
Package
All thermal impedance data is approximate for static
air conditions at 1W of power dissipation. Values will
change depending on operating conditions and applications. See the Intel Packaging Handbook (Order
No. 240800) for a description of Intel’s thermal impedance test methodology.
P
D
N
S
iJA
iJC
Device
45§ C/W 16§ C/W All
36§ C/W 13§ C/W 80C51FA, 83C51FA,
8XC51FC
45§ C/W 15§ C/W 87C51FA, 8XC51FB
46§ C/W 16§ C/W All
97§ C/W 24§ C/W FA
96§ C/W 24§ C/W FB
87§ C/W 18§ C/W FC
DATA SHEET REVISION HISTORY
Data sheets are changed as new device information becomes available. Verify with your local Intel sales office
that you have the latest version before finalizing a design or ordering devices.
The following differences exist between this datasheet (272322-003) and the previous version (272322-002):
1. Removed 8XC51FX-3 and 8XC51FX-20, replaced with 8XC51FX-24.
2. Included 8XC51FX-24 and 8XC51FX-33 devices.
3. 80C51FA and 83C51FA now have the same features as 87C51FA, 8XC51FB and 8XC51FC; same DC spec
used for all devices.
The following differences exist between the ‘‘-002’’ and ‘‘-001’’ version of 8XC51FX datasheet:
1. Removed 8XC51FX-L from datasheet.
2. Include VOH1 for 83C51FA (Express)/80C51FA (Express).
This 8XC51FX datasheet (272322-001) replaces the following datasheets:
87C51FA/83C51FA/80C51FA
83C51FA/80C51FA EXPRESS
270258-007
270620-001
87C51FA EXPRESS
87C51FA-20/-3
87C51FB/83C51FB
270619-001
272081-002
270563-005
87C51FB-20/-3 83C51FB-20/-3
87C51FB/83C51FB EXPRESS
87C51FC/83C51FC
272080-002
270767-002
270789-004
87C51FC/83C51FC EXPRESS
87C51FC-20/-3 83C51FC-20/-3
270903-001
272028-002
20