■
mu @
MCS@51
8-BIT CONTROL-ORIENTED MICROCONTROLLERS
Commercial/Express
8031AH18051AH18051AHP
8032N+18052N-I
8751W8751H-8
8751BW8752BI-I
■ High Performance HMOS Process
■ Boolean Processor
■ Internal Timers/Event Counters
■ Bit-Addressable RAM
■ 2-Level interrupt Priority Structure
■ Programmable Full Duplex Serial
Channel
■ 32 1/0 Lines (Four 8-Bit Ports)
■ 111 Instructions (64 Single-Cycle)
■ 64K External Program Memory Space
■ Security Feature Protects EPROM Parts
Against Software Piracy
64K External Data Memory Space
■
■ Extended Temperature Range
(–40”C to +85”C)
The MCS@51 controllers are optimized for control applications. Byte-processing and numerical operations on
small data structures are facilitated by a variety of fast addressing modes for accessing the internal RAM. The
instruction set provides a convenient menu of 8-bit arithmetic instructions, including multiply and divide instructions. Extensive on-chip support is provided for one-bit variables as a separate data type, allowing direct bit
manipulation and testing in control and logic systems that require Boolean processing.
The 8751H is an EPROM version of the 8051AH. It has 4 Kbytes of electrically programmable ROM which can
be erased with ultraviolet light. His fully compatible with the 8051AH but incorporates one additional feature: a
Program Memory Security bit that can be used to protect the EPROM against unauthorized readout. The
8751 H-8 is identical to the 8751 H but only operates up to 8 MHz.
The 8051AHP is identical to the 8051AH with the exception of the Protection Feature. To incorporate this
Protection Feature, program verification has been disabled and external memory accesses have been limited
to 4K.
The 8052AH is an enhanced version of the 8051AH. It is backwards compatible with the 8051AH and is
fabricated with HMOS II technology. The 8052AH enhancements are listed in the table below. Also refer to this
table for the ROM, ROMless and-EPROM versions of each product.
Device
8031AH
8051AH
6051AHP
8751 H
8751 H-8
6751 BH
8032AH
6052AH
8752BH
I
Data
Timera/
Event Counters
Interrupts
Program
Intsrnal Memory
none
4K X 8 ROM
4K X 6 ROM
4K X 8 EPROM
4K X 8 EPROM
4K X 8 EPROM
none
8K X 8 ROM
8K X 8 EPROM
128 X 8 RAM
128 X 8 RAM
128 X 8 RAM
128 X 8 RAM
128 X 6 RAM
128 X 8 RAM
256 X 6 RAM
256 X 8 RAM
256 X 8 RAM
2 x 18-Bit
2 x 16-Bit
2 x 16-Bit
2 x 16-Bit
2 x 16-Bit
2 x 16-Bit
3 x 16-Bit
3 x 16-Bit
3 x 16-Bit
5
5
5
5
5
5
6
6
6
Intel Corporationassumes no responsibilityfor the use of any circuit~ other than circuitryembodied in an Intel product.No other circuitpatent
licenses are implied.Informationcontained herein supersedes previouslypublishedspecificationson theaa davices from Intel.
O INTEL CORPORATION, 1994
October 1994
Order Numben 272318-002
MCS” 51 CONTROLLER
MO-M
-
P2.&P2 7
7
I
I
i
fl
13 I I
II
,,
b
,
JK2U
1==4
~M‘f2#fi+-oN,TMoD,TJ
STACK
POINTER
Acc
I
L-J
L“
+1
<>1
I
ml ... ,, I,
1
7’7
‘% “
I
PSEN
TyG
ALE
g~
1
.
.
E
RST-+
‘*
h-+ T
i-
n
,,(-1
———————————
--% =2
w
PI O*1 7
.. .
9
I
P0nT3
II
119
LATCH
5
7
W
Pm 3
LHvI!RS
—————
I
—..
J
P] O-P3 7
x
=
272318-1
Figure 1. MCSI@51 Controller Block Diagram
PROCESS INFORMATION
The 8031AH/8051AH and 8032AH/8052AH devices are manufactured on P414.1, an HMOS II process. The 8751H/8751 H-8 devices are manufactured on P421.X, an HMOS-E process. The 8751BH
and 8752BH devices are manufactured on P422.
Additional process and reliability information is availQuality and Reliability
able in Intel’s Components
Handbook, Order No, 210997.
MCS@ 51 CONTROLLER
PACKAGES
Part
Prefix
Package Type
8051AH
8031AH
8052AH
8032AH
6752BH*
P
D
N
40-Pin Plastic DIP
40-Pin CERDIP
44-Pin PLCC
45°chV
4!5”CIW
46°C/W
16“C/W
15“CAIV
18°CfW
8751H
8751 H-8
D
40-Pin CERDIP
45”CIW
45“CIW
8051AHP
P
D
40-Pin Plastic DIP
40-Pin CERDIP
45”CIW
45°c/w
16°CfW
15“cf w
8751 BH
P
N
40-Pin Plastic DIP
44-Pin PLCC
36”CIW
47”C1W
12°cf w
16”Cf W
‘ja
Ojc
NOTE:
*8752BHis 36”/10” for D, and 38”/22” for N.
All thermal impedance data is approximate for static air conditions at IW of power dissipation. Values will
change depending on operating conditions and application. See the Intel Pac/raging Handbook (Order Number
240800) for a description of Intel’s thermal impedance test methodology.
~“52’80320NL’
L{
PI.’
P1.1
P1.2
P1.3
P1.4
P1.5
P1,6
P1.7
RST
RU2 P3.O
TXD P3.1
INTO P3.2
INT1 P3,3
TOP3 4
11 P3.5
~ P3.6
t% P3.7
XTAL2
XTAL1
T2
T2EX
~
I’__”ll
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
6
9
10
11
12
13
14
15
16
17
16
19
‘1
29
26
27
26
25
24
23
22
21
‘ss+!--
Vcc
P’,’ ADO
PO.1 AD1
PO.2 A02
PO.3 A03
PO.4 AD4
PO.5 AD5
P06 AD’
3 PO.7A07
3 EIJvpp”
Z ALEIPROG”
3%FFI
3 P2.7 A15
2 P2.6A14
3 P2.5 A13
I P2.4 A12
1 P2.3 Al 1
> P2.2 AlO
3 P2 1 A9
X P20 A8
PI.6 ::8:;
P*,7 .:,.:
RST io;
(Rxo) P3.O :ji:
neaslvsd**
fTXD) P3.1
(INTo) P3.2
(INT1) P3.3
.1:;
:ji;
:!;;
:j:;
fTo) P3.4 :>!:
8X5X
272318-2
●EPROM only
“*Do not connect
DIP
reserved
PLCC
pins.
Figure 2. MCS@51 Controller Connections
3
MCS” 51 CONTROLLER
w
Port 2 emits the high-order address byte during
fetches from external Program Memory and during
accesses to external Data Memory that use 16-bit
addresses (MOVX @DPTR). In this application it
uses strong internal pullups when emitting 1‘s. During accesses to external Data Memory that use 8-bit
addresses (MOVX @Ri),Port 2 emits the contents of
the P2 Special Function Register.
PIN DESCRIPTIONS
Vcc: Supply voltage.
Vss: Circuit ground.
Port O:Port O is an 8-bit open drain bidirectional 1/0
port. As an output port each pin can sink 8 LS TTL
inputs.
Port Opins that have 1‘s written to them float, and in
that state can be used as high-impedance inputs.
The protection feature of the 8051AHP causes bits
P2.4 through P2.7 to be forced to O,effectively limiting external Data and Code space to 4K each during
external accesses.
Port O is also the multiplexed low-order address and
data bus during accesses to external Program and
Data Memory. In this application it uses strong internal pullups when emitting 1‘s and can source and
sink 8 LS TTL inputs.
Port O also receives the code bytes during programming of the EPROM parts, and outputs the code
bytes during program verification of the ROM and
EPROM parts. External pullups are required during
program verification.
Port 1: Port 1 is an 8-bit bidirectional 1/0 port with
internal pullups, The Port 1 output buffers can sink/
source 4 LS TTL inputs. Port 1 pins that have 1‘s
written to them are pulled high by the internal pullUPS,and in that state can be used as inputs. As
inputs, Port 1 pins that are externally pulled low will
source current (IIL on the data sheet) because of the
internal pullups.
Port 1 also receives the low-order address bytes
during programming of the EPROM parts and during
program verification of the ROM and EPROM parts.
In the 8032AH, 8052AH and 8752BH, Port 1 pins
P1.O and P1.1 also serve the T2 and T2EX functions, respectively.
I
Port
Pin
P1.0
P1.1
I
Alternative Function
Port 2 also receives the high-order address bits during programming of the EPROM parts and during
program verification of the ROM and EPROM parts.
I
T2 (Timer/Counter 2 External Input)
T2EX (Timer/Counter 2
Capture/Reload Trigger)
Port 2: Port 2 is an 8-bit bidirectional l/O port with
internal pullups. The Port 2 output buffers can sink/
source 4 LS TTL inputs. Porl 2 pins that have 1‘s
written to them are pulled high by the internal pullUPS,and in that state can be used as inputs. As
inputs, Port 2 pins that are externally pulled low will
source current (IIL on the data sheet) because of the
internal pullups.
Port 3: Port 3 is an 8-bit bidirectional l/O port with
internal pullups. The Port 3 output buffers can sink/
source 4 LS TTL inputs. Port 3 pins that have 1‘s
written to them are pulled high by the internal pullUPS,and in that state can be used as inputs. As
inputs, Port 3 pins that are externally pulled low will
source current (IIL on the data sheet) because of the
pullups.
Port 3 also serves the functions of various special
features of the MCS 51 Family, as listed below:
Port
Pin
Alternative Function
P3,0
P3.1
P3.2
P3,3
P3.4
P3.5
P3.6
P3.7
RXD (serial input port)
TXD (serial output port)
INTO(external interrupt O)
INT1 (external interrupt 1)
TO(Timer Oexternal input)
T1 (Timer 1 external input)
WR (external data memory write strobe)
~ (external data memory read strobe)
RST: Reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device,
ALE/PROG: Address Latch Enable output pulse for
latching the low byte of the address during accesses
to external memory. This pin is also the program
pulse input (PROG) during programming of the
EPROM parts.
In normal operation ALE is emitted at a constant
rate of 1/6the oscillator frequency, and may be used
for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.
MCS” 51 CONTROLLER
w
PSEN: Program Store Enable is the read strobe to
external Program Memory.
When the device is executing code from external
Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are
skipped during each access to external Data Memory
~/Vpp:
External Access enable ~
must be
strapped to VSS in order to enable any MCS 51 device to fetch code from external Program memory
locations starting at OOOOHup to FFFFH. ~ must
be strapped to VCCfor internal program execution.
To drive the device from an external clock source,
XTAL1 should be grounded, while XTAL2 is driven,
as shown in Figure 4. There are no requirements on
the duty cycle of the external clock signal, since the
input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum
high and low times specified on the data sheet must
be observed.
EXTERNAL
OSCILLATOR
SIGNAL
XTAL2
Note, however, that if the Security Bit in the EPROM
devices is programmed, the device will not fetch
code from any location in external Program Memory.
XTAL1
This pin also receives the programming supply voltage (VPP) during programming of the EPROM parts.
Vss
C2
I
El
272318-4
XTAL2
n
XTAL1
cl
Vss
=
272318-3
Cl, C2 = 30 PF +10 PF for Crystals
For Ceramic Resonators contact resonatormanufacturer.
Figure 3. Oscillator Connections
XTAL1: Input to the inverting oscillator amplifier.
XTAL2: Output from the inverting oscillator amplifier,
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in
Figure 3. Either a quartz crystal or ceramic resonator
may be used. More detailed information concerning
the use of the on-chip oscillator is available in Application Note AP-155; “Oscillators for MicrocontrolIers,” Order No, 230659.
I
Figure 4. External Drive Configuration
EXPRESS Version
The Intel EXPRESS system offers enhancements to
the operational specifications of the MCS 51 family
of microcontrollers. These EXPRESS products are
designed to meet the needs of those applications
whose operating requirements exceed commercial
standards.
The EXPRESS program includes the commercial
standard temperature range with burn-in, and an extended temperature range with or without burn-in.
With the commercial standard temperature range,
operational characteristics are guaranteed over the
temperature range of O“C to + 70”C. With the extended temperature range option, operational characteristics are guaranteed over a range of –40”C to
+ 85”C.
The optional burn-in is dynamic, for a minimum time
of 160 hours at 125°C with VCC = 5.5V * 0.25V,
following guidelines in MIL-STD-883, Method 1015.
Package types and EXPRESSversions are identified
by a one- or two-letter prefix to the part number. The
prefixes are listed in Table 1.
For the extended temperature range option, this
data sheet specifies the parameters which deviate
from their commercial temperature range limits.
5
MCS@51 CONTROLLER
Table 1. EXPRESS Prefix Identification
Prefix
Package Type
Temperature Range
Burn-In
P
Plastic
Commercial
No
D
Cerdip
Commercial
No
N
PLCC
Commercial
No
TD
Cerdip
Extended
No
TP
Plastic
Extended
No
TN
PLCC
Extended
No
LD
Cerdip
Extended
Yes
LP
Plastic
Extended
Yes
NOTE:
Contactdistributoror localsalesofficeto matchEXPRESSprefixwith properdevice.
DESIGN CONSIDERATIONS
If an 8751 BH or 8752BH is replacing an 8751 H in
a future design, the user should carefully compare both data sheets for DC or AC Characteristic differences. Note that the VIH and IIH specifications for the ~ pin differ significantly between
the devices.
Exposure to light when the EPROM device is in
operation may cause logic errors. For this reason,
it is suggested that an opaque label be placed
over the window when the die is exposed to ambient light.
●
The 8051AHP cannot access external Program
or Data memory above 4K. This means that the
following instructions that use the Data Pointer
only read/write data at address locations below
OFFFH:
MOVX A,@DPTR
MOVX (6JDPTR,
A
When the Data Pointer contains an address
above the 4K limit, those locations will not be accessed.
To access Data Memory above 4K, the
MOVX @Ri,A or MOVX A,@Ri instructions must
be used.
6
MCS” 51 CONTROLLER
ABSOLUTE MAXIMUM RATINGS*
NOTICE:This is a productiondata sheet. It is valid for
the devices indicated in the revision history. The
specificationsare subject to change without notice.
Ambient Temperature Under Bias –40”C to + 85°C
Storage Temperature
.
Voltage on EA/Vpp Pin to Vss
–65°C to + 150°C
8751 H . . . . . . . . . . . . . . . . .
–0.5V to + 21.5V
8751 BH/6752BH
–0.5V
Voltage on Any Other Pinto Vss
Power Dissipation.
.
13.OV
tO +
–0.5V to + 7V
. . ...
1.5W
*WARNING:Stressing the device beyond the “Absolute
Maximum Ratings” may cause permanent damage.
These are stress ratings orr~. Operation beyond the
“Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions”
may affect device reliabili~.
OPERATING CONDITIONS
Symbol
TA
Ambient
Description
Vcc
Fosc
Commercial
Express
SupplyVoltage
OscillatorFrequency
Temperature
Min
Msx
Units
o
–40
4.5
3.5
+70
+65
5.5
12
“c
“c
v
MHz
Under Bias
DC CHARACTERISTICS (Over Operating Conditions)
All parameter values apply to all devices unless otherwise indicated
Symbol
Parameter
Min
Max
Units
–0.5
0.8
v
o
0.7
v
Input High Voltage (Except XTAL2, RST)
2.0
Vcc + 0.5
v
VIH1
Input High Voltage to XTAL2, RST
2.5
Vcc + 0.5
v
XTAL1 = Vss
VIH2
Input High Voltage to ~ pin
of 6751BH and 8752BH
4.5
5.5V
0.45
v
loL = 1.6 mA
0.60
0.45
0.45
v
v
v
ioL = 3.2 mA
!OL = 2.4 mA
IOL = 3.2 mA
VIL
Input Low Voltage (Except ~
6751H and 8751H-8)
VIL1
Input Low Voltage to ~ Pin of
6751H and 8751H-8
VIH
Pin of
VoL
Output Low Voltage (Ports 1,2, 3)*
VoLl
Output Low Voltage (Port O,ALE, PSEN)*
8751 H, 8751 H-8
All Others
Test Conditions
VOH
Output High Voltage (Ports 1,2,3, ALE, PSEN)
2.4
v
IOH = –80 PA
VOH1
Output High Voltage (Port Oin
External Bus Mode)
2.4
v
IOH = –400 pA
IIL
Logical O Input Current (Ports 1,2,3, and RST)
–500
pA
VIN = 0.45V
IILI
Logical O Input Current (~)
8751H and 8751H-8
8751BH
8752BH
–15
–lo
mA
mA
mA
mA
VIN = 0.45V
VIN = Vss
VIN = Vss
–lo
0.5
7
MCS” 51 CONTROLLER
DC CHARACTERISTICS
(Over Operating Conditions)
All oarameter
values armlv
to.-.
all devices unless otherwise indicated (Continued)
~—.-...—.—.
r.,
_r
Symbol
Max
Units
11L2
Logical OInput Current (XTAL2)
–3.2
mA
VIN = 0.45V
ILI
Input Leakage Current (Porf O)
8751 H and 8751 H-8
All Others
* 1or)
t 10
pA
pA
0.45< VIN < VCC
0.45< VIN < VCC
500
1
pA
VIN= 2.4V
mA
4.5V < VIN < 5.5V
IIH
Parameter
Logical 1 Input Current (~)
8751H and 8751H-8
8751BH/8752BH
Min
Teat Conditions
IIH1
Input Current to RST to Activate Reset
500
pA
VIN < (Vcc – 1.5V)
Icc
Power Supply Current:
8031AH/8051 AH/8051AHP
8032AH/8052AH/8751 BH/8752BH
8751H/8751 H-8
125
175
250
mA
mA
mA
All Outputs
Disconnected;
m = Vcc
10
pF
Test freq = 1 MHz
Clo
Pin Capacitance
NOTES:
1. Capacitive loading on PortsO and 2 may csuse spurious noise pulses to be superimposed on the VOLS of ALE/PROG
and Ports 1 and 3. The noise is dueto externalbuscapacitancedischarginginto the PortOand Port2 pinswhenthesepins
make 1-to-Otransitionsduringbus operations.In the worst cases(capacitiveloading > 100 pF), the noise pulse on the
ALE/PROGpin mayexceed0.8V.In suchcasesit maybe desirableto qualifyALEwitha SchmittTrigger,or usean address
latchwith a Schmi~TriggerSTROBEinput.
2, ALE/PROGrefersto a pin on the 8751BH.ALErefersto a timingsignalthat is outputon the ALE/PROGpin.
3. Understeadystate(non-transient)conditions,loL mustbe externallylimitedas follows:
10 mA
MaximumloL per port pin:
MaximumloL per 8-bitpori 26 mA
Porto:
15 mA
Ports1, 2, and 3:
Maximumtotal toL for all outputpins:
71 mA
If loL exceedsthe test condition,VOLmayexceedthe relatedspecification.Pinsare not guaranteedto sinkcurrentgreater
than the listedtest conditions.
8
MCS@51 CONTROLLER
L: ~level
LOW, or ALE
P: PSEN
Q: Output data
R: ~ signal
T: Time
V: Valid
W: WR signal
X: No longer a valid logic level
Z: Float
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has 5 characters. The first character is always a ‘T’ (stands for time). The other
characters, depending on their positions, stand for
the name of a signal or the logical status of that
signal. The following is a list of all the characters and
what they stand for.
A: Address
C: Clock
D: Input Data
H: Logic level HIGH
1:Instruction (program memory contents)
For example,
TAVLL = Time from Address Valid to ALE Low.
TLLPL = Time from ALE Low to PSEN Low.
AC CHARACTERISTICS (Under Operating Conditions; Load Capacitance for Port O,ALE/PROG, and
PSEN = 100 pF; Load Capacitance for All Other Outputs = 80 pF)
EXTERNAL PROGRAM MEMORY CHARACTERISTICS
1/TCLCL
TLHLL
Oscillator Frequency
ALE Pulse Width
TAVLL
Address Valid to ALE Low
Address Hold after ALE Low
TLLAX
TLLIV
12 MHz Oscillator
Max
Min
Parameter
Symbol
Variable Oscillator
Max
12.0
3.5
Units
Min
MHz
127
2TCLCL–40
ns
43
TCLCL–40
48
TCLCL–35
ns
ns
ALE Low to Valid Instr In
8751 H
All Others
4TCLCL– 150
4TCLCL– 100
TLLPL
ALE LOW to PSEN LOW
58
TCLCL–25
ns
ns
ns
TPLPH
PSEN Pulse Width
8751H
All Others
190
215
3TCLCL–60
3TCLCL–35
ns
ns
TPLIV
TPXIX
TPXIZ
TPXAV
TAVIV
183
233
PSEN Low to Valid Instr In
8751H
All Others
100
125
o
Input Instr Hold after PSEN
Input Instr Float after PSEN
PSEN to Address Valid
3TCLCL– 150
3TCLCL– 125
ns
ns
ns
TCLCL–20
ns
ns
5TCLCL–1 50
5TCLCL–1 15
20
ns
ns
ns
0
63
75
TCLCL–8
Address to Valid Instr In
8751 H
All Others
287
302
TPLAZ
PSEN Low to Address Float
TRLRH
~
Pulse Width
400
6TCLCL– 100
ns
TWLWH
TRLDV
WR Pulse Width
400
6TCLCL– 100
ns
~
TRHDX
Data Hold after ~
TRHDZ
TLLDV
-.. .. . .
I AVUV
20
252
Low to Valid Data In
ns
ns
97
2TCLCL–70
ns
517
.,. DUD
I
8TCLCL–1 50
nl-n,
n,
.ec
103
Y I ~LUL—
0
Data Float after ~
ALE Low to Valid Data In
. ,,
. ,–,. , -—.—,.–
I Aaaress 10valla Ua[a m
5TCLCL– 165
o
I
I
I
I
ns
--
rm
9
MCS@51 CONTROLLER
EXTERNAL
Symbol
PROGRAM MEMORY CHARACTERISTICS
cillator
Max
‘arame’erI---%#
(Continued)
VariableOscillator
Min
Max
3TCLCL+ 50
Units
TLLWL
ALE Low to RD or WR Low
200
TAVWL
TQVWX
Address to ~
203
3TCLCL–50
4TCLCL– 130
13
23
TCLCL–70
TCLCL–60
ns
ns
433
7TCLCL– 150
TCLCL–50
ns
or WR Low
Data Valid to WR Transition
8751H
All Others
TQVWH
Data Valid to WR High
TWHQX
Data Hold after WR
TRLAZ
RD Low to Address Float
RD or WR High to ALE High
8751H
All Others
TWHLH
I
300
33
20
33
43
133
123
I
ns
I
TCLCL–50
TCLCL–40
ns
ns
20
TCLCL+ 50
TCLCL+40
I ns
I
ns
ns
NOTE:
“The 8751H-8 is identicalto the 8751Hbut only o~eratesutI to 8 MHz.Whencalculatingthe AC Characteristicsfor the
8751 H-8, use the 8751 H formula for variable oscillators.
10
MCS@51 CONTROLLER
EXTERNAL PROGRAM MEMORY READ CYCLE
w---
TLHLL _
ALE
\ ,
PSEN
\
/
TLLPL- ~
-TAVLL+
+
TPLPH
TLLIV
/
TLLAX
PORTO
AO
1
x
PORT 2
x
-A15
A8 -A15
272318-5
EXTERNAL DATA MEMORY READ CYCLE
ALE
/
\
Y
TWHLH
+TLHLL+
PSEN
‘LLOv ~
—
m
+
TRLRH –—
TLLWL
TAVLL +
b
—TRLDV4
_TLLAX
TRHOX+
AO-A7 FROM RI OR OPL
PORTO
.
.
PORT2
i ‘
OATA IN
TAVOV
P2.O-P2.7
x r
b
OR A8-A15
x
FROMDPH
A8-A15
FROMPCH
272318-6
EXTERNAL DATA MEMORY WRITE CYCLE
ALE
\ ,
/
\
TWHLH
TLHLL—
m
/
*
‘TLLwL~TwLwH
WT
1
TAVLL
PORTO
TQVWX
7t=-
+TLLAX
II
AO-A7
FROMRIOR OPL
1 ‘
k
TWHQX
I
M
TQVWH
x
P2.O-P2.7
OR A8-A15
r
1
OATAOUT
xx
FROMOPH
x
I
PORT2
:
AO-A7 FROMFCL
A8-A15
FROMPCH
272318-7
11
M=”
51 CONTROLLER
SERIAL PORT TIMING—SHIFT
Test Conditions: Over ODeratina Conditions: Load Capacitance = 80 rJF
12 MHz Oscillator
Parameter
Symbol
Min
VariableOscillator
Min
Max
Unite
Max
TXLXL
Serial Port Clock Cycle Time
1.0
12TCLCL
ps
TQVXH
Output Data Setup to Clock Rising
Edge
700
1OTCLCL– 133
ns
TXHQX
Output Data Hold after Clock
Rising Edge
50
2TCLCL–1 17
ns
TXHDX
Input Data Hold after Clock Rising
Edge
o
0
ns
TXHDV
Clock Rising Edge to Input Data
Valid
10TCLCL– 133
700
ns
;HI17REGISTERMODETIMINGWAVEFORMS
INSTRUCTION I
ALE
O
I
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
I
n n n n n n n n n n n n n n n n n n I
I-TXLXL-7
CLOCK
I
WI-TXHQX
OUTPUT OATA
o
1)(
1
2
x
3
x
4
x
5
x
6
x
7
/
+
,
SET TI
INPUT DATA
~
4
SET RI
272318-8
12
MCS@51 CONTROLLER
EXTERNAL CLOCK DRIVE
I
Symbol
Parameter
Min
Max
Units
1/TCLCL
Oscillator Frequency (except 8751H-8)
8751H-8
3.5
3.5
12
8
MHz
MHz
TCHCX
High Time
20
ns
TCLCX
Low Time
20
ns
TCLCH
I
I
Rise Time
I
20
Fall Time
TCHCL
I
20
ns
ns
EXTERNAL CLOCK DRIVE WAVEFORM
—
2.5
TCLCH _
TCHCX —
t
a
—
t 2.5
-—
+
—
~
TCliCL
A
TCLCX —
TCLCL
w
272318-9
AC TESTING INPUT, OUTPUT WAVEFORM
2.4
2.0
2.0
TEST POINTS
><
0.s
0.8
0.45
272318-10
AC Testing: Inputs are driven at 2.4V for a Logic “1” and 0.45V
for a Logic “O”. Timing measurements ara made at 2.OV for a
Logic “1” and 0.8V for a Logic“O”.
1
I
MCS@51 CONTROLLER
EPROM CHARACTERISTICS
Table3. EPROMProgramming
Modea
ALE
m
P2.7
PSEN
Mode
RST
P2.6
P2.5
P2.4
Program
1
0
o*
VPP
1
0
x
x
Verify
1
0
1
0
x
0
o*
0
1
x
1
Security Set
NOTE:
“1” = logichighfor that pin
“O” = logiclowfor that pin
“X” = “don’t care”
1
VPP
x
x
1
“VPP” = +21V *0.5V
*ALEis pulsedlowfor 50 ms
PROGRAMMING THE 8751H
To be programmed, the part must be running with a
4 to 6 MHz oscillator. (The reason the oscillator
needs to be running is that the internal bus is being
used to transfer address and program data to appropriate internal registers.) The address of an EPROM
location to be programmed is applied to Port 1 and
pins P2.O-P2.3 of Port 2, while the code byte to be
programmed into that location is applied to Port O.
The other Porl 2 pins, and RST, PSEN, and ~/Vpp
should be held at the “Program” levels indicated in
Table 3. ALE/PROG is pulsed low for 50 ms to program the code byte into the addressed EPROM location. The setup is shown in Figure 5.
Normally ~~is
held at a logic highflntil just
before ALE/PROG is to be pulsed. Then EA/Vpp is
raised to +21 V, ALE/PROG is pulsed, and then
~/Vpp is returned to a logic high. Waveforms and
detailed timing specifications are shown in later sections of this data sheet.
+5V
Note that the ~/VPP pin must not be allowed to go
above the maximum specified VPP level of 21.5V for
any amount of time. Even a narrow glitch above that
voltage Ievei can cause permanent damage to the
device. The VPP source should be well regulated
and free of glitches.
Program Verification
If the Security Bit has not been programmed, the onchip Program Memory can be read out for verification purposes, if desired, either during or after the
programming operation. The address of the Program
Memory location to be read is appiied to Port 1 and
pins P2.O-P2.3. The other pins should be held at the
“Verify” Ieveis indicated in Tabie 3. The contents of
the addressed location will come out on Port O. External pullups are required on Port O for this operation.
The setup, which is shown in Figure 6, is the same
as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an activeIow read strobe
+5V
Vcc
AOOR
A&b?
p?
U–All
P2.3
—FFH
?
a
PGM DATA
w
P2.0–
8751H
Vcc
w +
—FFH
‘=’’-”TCAREJ=E
‘LEl=$=-
mu
DATA
(USE 10K
PULLUPS]
W51H
~ . ,,W,,
U
Vlli
P2.7
XTAU
4-SUN*
5
XTAL1
.
VIH1
P2.5
ALE
VIH
P2.S
.
ENAS4E
RST
~~b
VIL d
F&vPP
n
Vss
CARE,. x X-9
P2 7
G
XTAU
J4-6 MHZm
RST h
PSEN
VIH1
XTAL1
Vss
.
27231 a-1 I
Figure5. Programming
Configuration
PSEN
.
27231S-12
Figure6. ProgramVerification
14
MCS@51 CONTROLLER
EPROM Security
+5V
X = OGN’T CARE”
The security feature consists of a ‘locking” bit which
when programmed denies electrical access by any
external means to the on-chip Program Memory.
The bit is programmed as shown in Figure 7. The
setup and procedure are the same as for normal
EPROM programming, except that P2.6 is held at a
logic high, Porl O,Port 1 and pins P2.O–P2.3 may be
in any state. The other pins should be held at the
“Security” levels indicated in Table 3.
Vcc
PI
m
P2.0X
P2.3
P2.4
8751H
ALE
{:
VIM
P2,7
‘x
ALE/PROO
50 ma PULSE TO GND
P2.5
P2.6
Once the Security Bit has been programmed, it can
be cleared only by full erasure of the Program Memory. While it is programmed, the internal Program
Memory can not be read out, the device can not be
further programmed, and it cannot executeout of
externalprogrammemory.Erasing the EPROM,
thus clearing the Security Bit, restores the device’s
full functionality. It can then be reprogrammed.
o
f
fi
+
EAYPP
—
WH1
XTAU
RST
m
XTAL1
Vss
PSEN
*
7*
272318-13
Figure7. Programming
the SecurityBit
Erasure Characteristics
Erasure of the EPROM begins to occur when the
device is exposed to light with wavelengths shorter
than approximately 4,000 Angstroms. Since sunlight
and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in
room-level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to
this type of exposure, it is suggested that an opaque
label be placed over the window.
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at least 15 W-sec/cm2. Exposing the
EPROM to an ultraviolet lamp of 12,000 pW/cm2
rating for 20 to 30 minutes, at a distance of about
1 inch, should be sufficient.
Erasure leaves the array in an all 1‘s state.
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
TA = 21°C to 27”C; VCC = 5V + 10%; VSS = OV
Symbol
Parameter
Min
Max
Unita
20.5
21.5
30
v
mA
6
MHz
10
ps
10
45
55
ps
ms
VPP
Programming Supply Voltage
IPP
Programming Supply Current
1/TCLCL
TAVGL
TGHAX
Oscillator Frequency
Address Setup to PROG Low
Address Hold after PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold after~
48TCLCL
TEHSH
TSHGL
P2.7 (ENABLE) High to VPP
48TCLCL
TGHSL
VPP Setup to PROG Low
VPP Hold after PROG
TGLGH
PROG Width
TAVQV
Address to Data Valid
TELQV
ENABLE Low to Data Valid
TEHQZ
Data Float after ENABLE
4
46TCLCL
48TCLCL
48TCLCL
o
48TCLCL
15
MCS” 51 CONTROLLER
GI-”
”nl r“””
”mrnmrlmn.
w
I-8. ”
,Lrl..
.“4-s
.
m“..
..-.
b.
“..8.,”
PROGRAMMING
P1.O-PI.7
P3,0-P3,3
$
VERIFICATION
ADDRESS
(
J
—
PORTO
DATAIN
{ ,
TOVGL —
—TGHOX
—
TAVGL
—
TGHAX
kLE/PROG
\
TSHGL —
~
‘
—
—
TGLGH
21V * .5V
TGHSL
r
Fi.vPP
m
HIGH
TSHSN
—
P3.7
(ENABLE)
\
TTL HIGH
TTL HIGH
TELOV
\
1 ‘
272318-14
For programmingconditionssee Figure 5.
16
For verificationconditionssee Figure 6.
inlA
MCS” 51 CONTROLLER
Normally ~&is
held at a logic high until just
before ALE/PROG is to be pulsed. Then ~/Vpp is
raised to Vpp, ALE/PROG is pulsed low, and then
~/Vpp is returned to a valid high voltage. The voltage on the ~/Vpp pin must be at the valid EA/Vpp
high level before a verify is attempted. Waveforms
and detailed timing specifications are shown in later
sections of this data sheet.
Programming the 8751BH/8752BH
To be programmed, the 875XBH must be running
with a 4 to 6 MHz oscillator. (The reason the oscillator needs to be running is that the internal bus is
being used to transfer address and program data to
appropriate internal registers.) The address of an
EPROM location to be programmed is applied to
Porl 1 and pins P2.O- P2.4 of Port 2, while the code
byte to be programmed into that location is applied
to Port O. The other Port 2 and 3 pins, and RST,
PSEN, and ~/Vpp should be held at the “Program”
levels indicated in Table 1. ALE/PROG is pulsed low
to croaram the code bvte into the addressed
EPROfl location. The setu’p is shown in Figure 8.
Note that the ~/Vpp pin must not be allowed to go
above the maximum specified Vpp level for any
amount of time. Even a narrow glitch above that voltage level can cause permanent damage to the device. The Vpp source should be well regulated and
free of glitches.
+5V
Vcc
Po
1~
RST
1~
P3.6
E/vpp
P3.7
XTAL2
+12.75V
ALE/PROG ~25
875X,,
1~
~
~
100 p, PULSESTO GND
~“
P2.7 ~1
P2.6 ~o
lJ-
4-6 MHz
❑
T=
;
XTAL1
P2.O
-P2,4
‘ks
=
—.
272318-15
—
Figure8. Programming
the EPROM
Table4. EPROMProgramming
Modeafor 875XBH
MODE
RST
PSEN
ALE/
—
PROG
ml
Vpp
P2.7
P2.6
P3.6
P3.7
Program Code Data
1
0
o*
Vpp
1
0
1
1
Verify Code Data
1
0
1
1
0
0
1
1
Program Encryption Tabie
Use Addresses O-1FH
~= 1
Program Lock
1
0
o*
Vpp
1
0
0
1
1
1
0
0
o*
o*
Vpp
Vpp
1
1
1
1
1
0
1
0
1
0
1
1
0
0
0
0
Bits (LBx)
Read Signature
x=2
NOTES:
“1” = Validhighfor that pin
“O” = Validlowfor that pin
“vpp” = + 12.75V+ 0.25V
*ALE/PROGis pulsedlowfor 100USfor programming.(Quick-PulseProgramming)
17
MCS@51 CONTROLLER
PROGRAM VERIFICATION
QUICK-PULSE PROGRAMMING
ALGORITHM
If the Lock Bits have not been programmed, the onchip Program Memory can be read out for verification purposes, if desired, either during or after the
programming operation. The address of the Program
Memory location to be read is applied to Port 1 and
pins P2.O - P2.4. The other pins should be held at
the “Verify” levels indicated in Table 1. The contents of the addressed location will come out on Port
O. External pullups are required on Port O for this
operation. (If the Encryption Array in the EPROM
has been programmed, the data present at Port O
will be Code Data XNOR Encryption Data. The user
must know the Encryption Array contents to manually “unencrypt” the data during verify.)
The 875XBH can be programmed using the QuickPulse Programming Algorithm for microcontrollers.
The features of the new programming method are a
lower Vpp (12.75 volts as compared to 21 volts) and
a shorter programming pulse. For example, it is possible to program the entire 8 Kbytes of 875XBH
EPROM memory in less than 25 seconds with this
algorithm!
To program the part using the new~rithm,
Vpp
must be 12,75 f 0.25 Volts. ALE/PROG is pulsed
low for 100 pseconds, 25 times as shown in
Figure 9, Then, the byte just programmed may be
verified. After programming, the entire array should
be verified. The Program Lock features are programmed using the same method, but with the setup
as shown in Table 4. The only difference in programming Lock features is that the Lock features cannot
be directly verified. Instead, verification of programming is by observing that their features are enabled.
,
The setup, which is shown in Figure 10, is the same
as for programming the EPROM except that pin P2.7
is held at a logic low, or may be used as an active
low read strob~.
~25p”LsEs ~
ALEM
n-------100JM
*lops
10 P,MIN
I
“
1
ALE/PROG:
0
272318-16
Figure9. PROGWaveforma
+~v
h
AO-A7
P!
P3.6
rmpp
P3.7
=
0
P2.7
0
XTAL2
P2.6
0
XTAL1
P2.O
-P2.4
A8-A12
L
❑
1
ALE/PRW
B75xBH
1
PGM
DATA
Po
RST
4-6 MHz
10kJl
X8
‘r-F’
Vcc
(i-mm
Vss
=
F
Figure10.Verifyingthe EPROM
18
272318-17
MCS@51 CONTROLLER
Table5. LockBitsandtheirFeatures
PROGRAM MEMORY LOCK
The two-level Program Lock system consists of 2
Lock bits and a 32-byte Encryption Array which are
used to protect the program memory against software piracy.
LogicEnabled
LB1
Minimum Program Lock features
enabled. (Code Verify WIIIstill be
u
=
ENCRYPTION ARRAY
Within the EPROM array are 32 bytes of Encryption
Array that are initially unprogrammed (all 1s). Every
time that a byte is addressed during a verify, 5 address lines are used to select a byte of the Encryption Array. This byte is then exclusive-NORed
(XNOR) with the code byte, creating an Encrypted
Verify byte. The algorithm, with the array in the unprogrammed state (all 1s), will return the code in its
original, unmodified form.
It is recommended that whenever the Encryption Array is used, at least one of the Lock Bits be programmed as well.
P
P
U
I
I
u
MOVC instructions executed from
external program memory are
disabled from fetching code bytes
from internal memory, EA is
sampled and latched on reset,
and further programming of the
EPROM is disabled
P
Same as above, but Verify is also
disabled
P
IReservedfor Future Definition
I
= Programmed
= Unprogrammed
LOCK BITS
READING THE SIGNATURE BYTES
Also included in the EPROM Program Lock scheme
are two Lock Bits which function as shown in Table
5.
The signature bytes are read by the same procedure
as a normal verification of locations 030H and 031H,
except that P3.6 and P3.7 need to be pulled to a
logic low. The values returned are:
Erasing the EPROM also erases the Encryption Array and the Lock Bits, returning the part to full unlocked functionality.
(030H) = 89H indicates manufactured by Intel
(031H) = 51H indicates 8751BH
52H indicates 8752BH
To ensure proper functionality of the chip, the internally latched value of the ~ pin must agree with its
external state.
19
MCS” 51 CONTROLLER
ERASURE CHARACTERISTICS
this type of exposure, it is suggested that an opaque
label be placed over the window.
Erasure of the EPROM begins to occur when the
8752BH is exposed to light with wavelengths shorter
than approximately 4,000 Angstroms. Since sunlight
and fluorescent lighting have wavelengths in this
range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in
room-level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to
The recommended erasure procedure is exposure
to ultraviolet light (at 2537 Angstroms) to an integrated dose of at lease 15 W-see/cm. Exposing the
EPROM to an ultraviolet lamp of 12,000 pW/cm rating for 30 minutes, at a distance of about 1 inch,
should be sufficient.
Erasure leaves the array in an all Is state.
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
(T,4 = 21°C to 27”C, Vcc = 5.OV + 10%, Vss = OV)
Parameter
Symbol
Vpp
Programming
Supply
Voltage
Ipp
Programming
Supply
Current
Min
Max
12.5
13.0
v
50
mA
8
MHz
4
1/TCLCL
Oscillator Frequency
TAVGL
Address Setup to PROG Low
TGHAX
Address Hold After PROG
48TCLCL
TDVGL
Data Setup to PROG Low
48TCLCL
TGHDX
Data Hold After PROG
48TCLCL
TEHSH
P2.7 (ENABLE) High to Vpp
48TCLCL
TSHGL
Vpp Setup to PROG Low
10
TGHSL
Vpp Hold After PROG
10
TGLGH
PROG Width
90
Units
48TCLCL
ps
ps
110
TAVQV
Address to Data Valid
48TCLCL
TELQV
ENABLE Low to Data Valid
48TCLCL
TEHQZ
Data Float After ENABLE
o
TGHGL
PROG High to PROG Low
10
ps
48TCLCL
ps
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
VERIFICATION
PROGRAMMING
ADDRFSS
ADDRESS
TAvQV
DATAOUT
DATAIN
‘::=&z
TAVGL
TSHGL
TGLGH
~wpp
.~TGHDX
~
TDVGL
Pu&
}
TGHAX
d
TGHGL
TGHsL
t
[A/HIGH
TELQV
L
TEHQZ
P2.7
272318-18
20
MCS@51 CONTROLLER
DATA SHEET REVISION HISTORY
Datasheets are changed as new device information becomes available. Verify with your local Intel sales office
that you have the latest version before finalizing a design or ordering devices.
The following differences exist between this datasheet (272318-002) and the previous version (272318-001):
1. Removed QP and QD (commercial with extended burn-in) from Table 1. EXPRESS Prefix Identification.
This datasheet (272318-001) replaces the following datasheets:
MCS@51 Controllers (270048-007)
8051AHP (270279-004)
8751BH (270248-005)
8751 BH EXPRESS (270708-001)
8752BH (270429-004)
8752BH EXPRESS (270650-002)
21