ADVANCE INFORMATION 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Commercial/Express ■ Real-time and Programmed Wait State Bus Operation ■ Binary-code Compatible with MCS® 51 ■ Pin Compatible with 44-pin PLCC and 40-pin PDIP MCS 51 Sockets ■ Register-based MCS® 251 Architecture — 40-byte Register File — Registers Accessible as Bytes, Words, or Double Words ■ Enriched MCS 51 Instruction Set — 16-bit and 32-bit Arithmetic and Logic Instructions — Compare and Conditional Jump Instructions — Expanded Set of Move Instructions ■ Linear Addressing ■ 256-Kbyte Expanded External Code/Data Memory Space ■ ROM Options: 16 Kbytes (TB/TQ), 8 Kbytes (TA/TP), or without ROM ■ 16-bit Internal Code Fetch 1-Kbyte (TA/TB) or 512-Byte (TP/TQ) ■ 8-bit, 2-clock External Code Fetch in © INTEL CORPORATION, 1997 ■ Eight Maskable Interrupt Sources with Four Programmable Priority Levels ■ Three Flexible 16-bit Timer/counters ■ Hardware Watchdog Timer ■ Programmable Counter Array — High-speed Output — Compare/Capture Operation — Pulse Width Modulator — Watchdog Timer ■ Two Programmable Serial I/O Ports — Framing Error Detection — Automatic Address Recognition ■ High-performance CHMOS Technology ■ Complete System Development ■ On-chip Data RAM Options: ■ Fast MCS 251 Instruction Pipeline — External Wait States (0-3 wait states) — Address Range & Memory Mapping — Page Mode — Extended Data Float Timings or 8xC251Sx Compatible AC Timings ■ 32 Programmable I/O Lines ■ Static Standby to 24-MHz Operation ■ 64-Kbyte Extended Stack Space Page Mode ■ User-selectable Configurations: Support — Compatible with Existing Tools — MCS 251 Tools Available: Compiler, Assembler, Debugger, ICE ■ Package Options (PDIP and PLCC) November, 1997 Order Number: 273129-001 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 8xC251TA/TB/TP/TQ may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver CO 80217-9808 or call 1-800-548-4725. Many documents are available for download from Intel’s website at http://www.intel.com. Copyright © Intel Corporation 1997. *Third party brands and names are the property of their respective owners. Contents 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS Microcontroller Commercial/Express 1.0 INTRODUCTION ......................................................................................................................................... 1 2.0 NOMENCLATURE ...................................................................................................................................... 2 3.0 PINOUT ....................................................................................................................................................... 4 4.0 SIGNALS ..................................................................................................................................................... 8 5.0 ADDRESS MAP ........................................................................................................................................ 11 6.0 ELECTRICAL CHARACTERISTICS ......................................................................................................... 12 6.1 D.C. Characteristics ........................................................................................................................... 12 6.2 Definition of AC Symbols ................................................................................................................... 14 6.3 A.C. Characteristics ........................................................................................................................... 14 6.3.1 External Bus Cycles, Nonpage Mode ..................................................................................... 18 6.3.2 External Bus Cycles, Page Mode ........................................................................................... 21 6.3.3 Definition of Real-Time Wait Symbols .................................................................................... 24 6.3.4 External Bus Cycles, Real-Time Wait States .......................................................................... 24 6.4 AC Characteristics — Serial Port, Shift Register Mode ..................................................................... 28 6.5 External Clock Drive .......................................................................................................................... 29 7.0 THERMAL CHARACTERISTICS .............................................................................................................. 30 ADVANCE INFORMATION iii Contents FIGURES Figure 1. 8xC251TA/TB/TP/TQ Block Diagram ........................................................................................ 1 Figure 2. The 8xC251TA/TB/TP/TQ Family Nomenclature....................................................................... 2 Figure 3. 8xC251TA/TB/TP/TQ 44-pin PLCC Package ............................................................................ 4 Figure 4. 8xC251TA/TB/TP/TQ 40-pin PDIP Packages............................................................................ 5 Figure 5. External Bus Cycle: Code Fetch (Nonpage Mode) .................................................................. 18 Figure 6. External Bus Cycle: Data Read (Nonpage Mode) ................................................................... 19 Figure 7. External Bus Cycle: Data Write (Nonpage Mode).................................................................... 20 Figure 8. External Bus Cycle: Code Fetch (Page Mode) ........................................................................ 21 Figure 9. External Bus Cycle: Data Read (Page Mode).......................................................................... 22 Figure 10. External Bus Cycle: Data Write (Page Mode).......................................................................... 23 Figure 11. External Bus Cycle: Code Fetch/Data Read (Nonpage Mode)................................................ 24 Figure 12. External Bus Cycle: Data Write (Nonpage Mode).................................................................... 25 Figure 13. External Bus Cycle: Code Fetch/Data Read (Page Mode) ...................................................... 26 Figure 14. External Bus Cycle: Data Write (Page Mode).......................................................................... 27 Figure 15. Serial Port Waveform — Shift Register Mode.......................................................................... 28 Figure 16. External Clock Drive Waveforms ............................................................................................. 29 Figure 17. AC Testing Input, Output Waveforms ...................................................................................... 29 Figure 18. Float Waveforms...................................................................................................................... 30 TABLES Table 1. Description of Product Nomenclature ........................................................................................ 2 Table 2. Proliferation Options .................................................................................................................. 3 Table 3. Package Information .................................................................................................................. 3 Table 4. 8xC251TA/TB/TP/TQ Pin Assignment ....................................................................................... 6 Table 5. 8xC251TA/TB/TP/TQ PLCC/DIP Pin Assignments Arranged by Functional Category .............. 7 Table 6. Signal Descriptions .................................................................................................................... 8 Table 7. Memory Signal Selections (RD1:0) .......................................................................................... 10 Table 8. 8xC251TA/TB/TP/TQ Address Map ......................................................................................... 11 Table 9. DC Characteristics at VCC = 4.5 – 5.5 V .................................................................................. 12 Table 10. AC Timing Symbol Definitions ................................................................................................. 14 Table 11. AC Characteristics ................................................................................................................... 14 Table 12. Real-time Wait Timing Symbol Definitions ............................................................................... 24 Table 13. Real-Time Wait AC Timing ...................................................................................................... 27 Table 14. Serial Port Timing — Shift Register Mode ............................................................................... 28 Table 15. External Clock Drive ................................................................................................................ 29 Table 16. Thermal Characteristics ........................................................................................................... 30 iv ADVANCE INFORMATION 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 1.0 feature an enriched instruction set, linear addressing, and efficient C-language support. The 8xC251TA/TB/TP/TQ has 512 bytes or 1 Kbyte of on-chip RAM and is available with 8 Kbytes or 16 Kbytes of on-chip ROM, or without ROM. A variety of features can be selected by new user-programmable configurations. INTRODUCTION A member of the Intel family of 8-bit MCS 251 microcontrollers, the 8xC251TA/TB/TP/TQ is binary-code compatible with MCS 51 microcontrollers and pin compatible with 40-pin PDIP and 44-pin PLCC MCS 51 microcontrollers. MCS 251 microcontrollers I/O Ports and Peripheral Signals System Bus and I/O Ports P0.7:0 P2.7:0 Port 0 Drivers Port 2 Drivers Code OTPROM/ROM 8 Kbytes or 16 Kbytes Data RAM 512 Bytes or 1024 Bytes P1.7:0 P3.7:0 Port 1 Drivers Port 3 Drivers Memory Data (16) Watchdog Timer Memory Address (16) Peripheral Interface Bus Interface Code Bus (16) Interrupt Handler Data Bus (8) SRC2 (8) ALU Register File Data Address (24) Instruction Sequencer SRC1 (8) IB Bus (8) Code Address (24) Data Memory Interface Timer/ Counters PCA Two Serial I/O Ports Clock & Reset Peripherals DST (16) MCS® 251 Microcontroller Core Clock & Reset 8XC251TA/TB/TP/TQ Microcontroller A4530-01 Figure 1. 8xC251TA/TB/TP/TQ Block Diagram ADVANCE INFORMATION 1 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 2.0 NOMENCLATURE X XX 8 X X XXXXX XX ic e ily or ns tio Op s -in on rn pti n tio yO ma ed m Fa or Bu ns nd tio em In f -m Op a re e Sp ct ss du ce am ing atu er ag gr v De o Pr o Pr o Pr ck mp Pa Te A2815-01 Figure 2. The 8xC251TA/TB/TP/TQ Family Nomenclature Table 1. Description of Product Nomenclature Parameter Temperature and Burn-in Options Packaging Options Program Memory Options Process Information Product Family Device Memory Options Device Speed 2 Options Description no mark Commercial operating temperature range (0°C to 70°C) with Intel standard burn-in. T Express operating temperature range (-40°C to 85°C) without Intel standard burn-in. N 44-pin Plastic Leaded Chip Carrier (PLCC) P 40-pin Plastic Dual In-line Package (PDIP) C 40-pin Ceramic Dual In-line Package (Ceramic DIP) 0 Without ROM 3 ROM C 251 CHMOS 8-bit control architecture TA 1-Kbyte RAM/8-Kbyte ROM TB 1-Kbyte RAM/16-Kbyte ROM or without ROM TP 512-byte RAM/8-Kbyte ROM TQ 512-byte RAM/16-Kbyte ROM or without ROM 24 External clock frequency ADVANCE INFORMATION 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 2 lists the proliferation options. See Figure 2 for the 8xC251TA/TB/TP/TQ family nomenclature. Table 2. Proliferation Options 8xC251TA/TB/TP/TQ (0 – 24 MHz; 5 V ±10%) 80C251TB24 CPU-only 80C251TQ24 CPU-only 83C251TA24 ROM 83C251TB24 ROM 83C251TP24 ROM 83C251TQ24 ROM Table lists the 8xC251TA/TB/TP/TQ package definitions. Table 3. Package Information Pkg. Definition Temperature N 44 ld. PLCC P 40 ld. Plastic DIP TN 44 ld. PLCC -40°C to +85°C TP 40 ld. Plastic DIP -40°C to +85°C ADVANCE INFORMATION 0°C to +70°C 0°C to +70°C 3 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER PINOUT 6 5 4 3 2 1 44 43 42 41 40 P1.4 / CEX1 P1.3 / CEX0 / TXD1 P1.2 / ECI / RXD1 P1.1 / T2EX P1.0 / T2 VSS1 VCC AD0 / P0.0 AD1 / P0.1 AD2 / P0.2 AD3 / P0.3 3.0 7 8 9 10 11 12 13 14 15 16 17 8XC251TA 8XC251TB 8XC251TP 8XC251TQ View of component as mounted on PC board 39 38 37 36 35 34 33 32 31 30 29 AD4 / P0.4 AD5 / P0.5 AD6 / P0.6 AD7 / P0.7 EA# VSS2 ALE PSEN# A15 / P2.7 A14 / P2.6 A13 / P2.5 P3.6 / WR# P3.7 / RD# / A16 XTAL2 XTAL1 VSS VSS2 A8 / P2.0 A9 / P2.1 A10 / P2.2 A11 / P2.3 A12 / P2.4 18 19 20 21 22 23 24 25 26 27 28 P1.5 / CEX2 P1.6 / CEX3 / WAIT# P1.7 / CEX4 / A17 / WCLK RST P3.0 / RXD VCC2 P3.1 / TXD P3.2 / INT0# P3.3 / INT1# P3.4 / T0 P3.5 / T1 A4538-01 Figure 3. 8xC251TA/TB/TP/TQ 44-pin PLCC Package 4 ADVANCE INFORMATION 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER P1.0 / T2 1 40 VCC P1.1 / T2EX 2 39 AD0 / P0.0 P1.2 / ECI / RXD1 3 38 AD1 / P0.1 P1.3 / CEX0 / TXD1 4 37 AD2 / P0.2 P1.4 / CEX1 5 36 AD3 / P0.3 P1.5 / CEX2 6 35 AD4 / P0.4 P1.6 / CEX3 / WAIT# 7 34 AD5 / P0.5 P1.7 / CEX4 / A17 / WCLK 8 33 AD6 / P0.6 RST 9 32 AD7 / P0.7 P3.0 / RXD 10 31 EA# P3.1 / TXD 11 30 ALE P3.2 / INT0# 12 29 PSEN# P3.3 / INT1# 13 28 A15 / P2.7 P3.4 / T0 14 27 A14 / P2.6 P3.5 / T1 15 26 A13 / P2.5 P3.6 / WR# 16 25 A12 / P2.4 P3.7 / RD# / A16 17 24 A11 / P2.3 XTAL2 18 23 A10 / P2.2 XTAL1 VSS 19 22 A9 / P2.1 20 21 A8 / P2.0 8XC251TA 8XC251TB 8XC251TP 8XC251TQ View of component as mounted on PC board A4532-02 Figure 4. 8xC251TA/TB/TP/TQ 40-pin PDIP Packages ADVANCE INFORMATION 5 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 4. 8xC251TA/TB/TP/TQ Pin Assignment PLCC DIP 1 PLCC DIP 23 Name VSS2 2 1 P1.0/T2 24 21 A8/P2.0 3 2 P1.1/T2EX 25 22 A9/P2.1 4 3 P1.2/ECI/RXD1 26 23 A10/P2.2 5 4 P1.3/CEX0/TXD1 27 24 A11/P2.3 6 5 P1.4/CEX1 28 25 A12/P2.4 7 6 P1.5/CEX2 29 26 A13/P2.5 8 7 P1.6/CEX3/WAIT# 30 27 A14/P2.6 9 8 P1.7/CEX4/A17/WCLK 31 28 A15/P2.7 10 9 RST 32 29 PSEN# 11 10 P3.0/RXD 33 30 VCC2 34 12 6 Name VSS1 ALE VSS2 13 11 P3.1/TXD 35 31 EA# 14 12 P3.2/INT0# 36 32 AD7/P0.7 15 13 P3.3/INT1# 37 33 AD6/P0.6 16 14 P3.4/T0 38 34 AD5/P0.5 17 15 P3.5/T1 39 35 AD4/P0.4 18 16 P3.6/WR# 40 36 AD3/P0.3 19 17 P3.7/RD#/A16 41 37 AD2/P0.2 20 18 XTAL2 42 38 AD1/P0.1 21 19 XTAL1 43 39 AD0/P0.0 22 20 VSS 44 40 VCC ADVANCE INFORMATION 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 5. 8xC251TA/TB/TP/TQ PLCC/DIP Pin Assignments Arranged by Functional Category Address & Data Name Input/Output PLCC DIP AD0/P0.0 43 39 P1.0/T2 2 1 AD1/P0.1 42 38 P1.1/T2EX 3 2 AD2/P0.2 41 37 P1.2/ECI/RXD1 4 3 AD3/P0.3 40 36 P1.3/CEX0/TXD1 5 4 AD4/P0.4 39 35 P1.4/CEX1 6 5 AD5/P0.5 38 34 P1.5/CEX2 7 6 AD6/P0.6 37 33 P1.6/CEX3/WAIT# 8 7 AD7/P0.7 36 32 P1.7/CEX4/A17/WCLK 9 8 A8/P2.0 24 21 P3.0/RXD 11 10 A9/P2.1 25 22 P3.1/TXD 13 11 A10/P2.2 26 23 P3.4/T0 16 14 A11/P2.3 27 24 P3.5/T1 17 15 A12/P2.4 28 25 A13/P2.5 29 26 A14/P2.6 30 27 PLCC DIP A15/P2.7 31 28 VCC 44 40 P3.7/RD#/A16 19 17 VCC2 12 P1.7/CEX4/A17/WCLK 9 8 Processor Control Name Name PLCC DIP Power & Ground Name VSS 22 VSS1 1 VSS2 23, 34 EA# 35 PLCC DIP P3.2/INT0# 14 12 Bus Control & Status P3.3/INT1# 15 13 Name EA# 35 31 RST 10 9 PLCC 20 31 DIP P3.6/WR# 18 16 P3.7/RD#/A16 19 17 XTAL1 21 18 ALE 33 30 XTAL2 20 19 PSEN# 32 29 ADVANCE INFORMATION 7 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 4.0 SIGNALS Table 6. Signal Descriptions (Sheet 1 of 3) Signal Name A17 Alternate Function Type Description O 18th Address Bit (A17). Output to memory as 18th external address bit (A17) in extended bus applications, depending on the values of bits RD0 and RD1 in configuration byte UCONFIG0. See also RD# and PSEN#. P1.7/CEX4/ WCLK RD# A16 O Address Line 16. See RD#. A15:81 O Address Lines. Upper address lines for the external bus. P2.7:0 AD7:01 I/O Address/Data Lines. Multiplexed lower address lines and data lines for external memory. P0.7:0 ALE CEX4:0 EA# O Address Latch Enable. ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A15:8 and AD7:0. An external latch can use ALE to demultiplex the address from the address/data bus. I/O Programmable Counter Array (PCA) Input/Output Pins. These are input signals for the PCA capture mode and output signals for the PCA compare mode and PCA PWM mode. P1.6:4 P1.7/A17/ WAIT# P1.3/TXD1 I External Access. Directs program memory accesses to on-chip or offchip code memory. For EA# = 0, all program memory accesses are offchip. For EA# = 1, an access is to on-chip ROM if the address is within the range of the on-chip ROM; otherwise the access is off-chip. The value of EA# is latched at reset. For devices without on-chip ROM, EA# must be strapped to ground. ECI I PCA External Clock Input. External clock input to the 16-bit PCA timer. P1.2/RXD1 INT1:0# I External Interrupts 0 and 1. These inputs set bits IE1:0 in the TCON register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If bits INT1:0 are clear, bits IE1:0 are set by a low level on INT1:0#. P3.3:2 P0.7:0 I/O Port 0. This is an 8-bit, open-drain, bidirectional I/O port. AD7:0 P1.0 P1.1 P1.2 P1.7:3 I/O Port 1. This is an 8-bit, bidirectional I/O port with internal pullups. T2 T2EX ECI/RXD1 CEX3:1 CEX4/A17/ WAIT#/ WCLK CEX0/TXD1 P2.7:0 I/O Port 2. This is an 8-bit, bidirectional I/O port with internal pullups. A15:8 P3.0 P3.1 P3.3:2 P3.5:4 P3.6 P3.7 I/O Port 3. This is an 8-bit, bidirectional I/O port with internal pullups. RXD TXD INT1:0# T1:0 WR# RD#/A16 PSEN# O Program Store Enable. Read signal output. This output is asserted for a memory address range that depends on bits RD0 and RD1 in configuration byte UCONFIG0 (see RD#). — 8 ADVANCE INFORMATION 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 6. Signal Descriptions (Sheet 2 of 3) Signal Name Type Description Alternate Function RD# O Read or 17th Address Bit (A16). Read signal output to external data memory or 17th external address bit (A16), depending on the values of bits RD0 and RD1 in configuration byte UCONFIG0. (See PSEN#). P3.7/A16 RST I Reset. Reset input to the chip. Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The port pins are driven to their reset conditions when a voltage greater than VIH1 is applied, whether or not the oscillator is running. This pin has an internal pulldown resistor, which allows the device to be reset by connecting a capacitor between this pin and VCC . — Asserting RST when the chip is in idle mode or powerdown mode returns the chip to normal operation. RXD I/O Receive Serial Data. RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2, and 3. P3.0 RXD1 I/O Receive Serial Data 1. RXD1 sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2, and 3 for the 2nd serial port. P1.2/ECI I Timer 1:0 External Clock Inputs. When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count. P3.5:4 I/O Timer 2 Clock Input/Output. For the timer 2 capture mode, this signal is the external clock input. For the clock-out mode, it is the timer 2 clock output. P1.0 T2EX I Timer 2 External Input. In timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. In auto-reload mode, a falling edge causes the timer 2 registers to be reloaded. In the up-down counter mode, this signal determines the count direction: 1 = up, 0 = down. P1.1 TXD O Transmit Serial Data. TXD outputs the shift clock in serial I/O mode 0 and transmits serial data in serial I/O modes 1, 2, and 3. P3.1 TXD1 O Transmit Serial Data 1. TXD1 outputs the shift clock in serial I/O mode 0 and transmits serial data in serial I/O modes 1, 2, and 3 for the 2nd serial port. P1.3/CEX0 T1:0 T2 VCC PWR Supply Voltage. Connect this pin to the +5V supply voltage. — VCC2 PWR Secondary Supply Voltage 2. This supply voltage connection is provided to reduce power supply noise. Connection of this pin to the +5V supply voltage is recommended. However, when using the 8XC251SB as a pin-for-pin replacement for the 8XC51FX, VSS 2 can be unconnected without loss of compatibility. (Not available on DIP) — VSS GND Circuit Ground. Connect this pin to ground. — VSS1 GND Secondary Ground. This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the 8xC251TA/TB/TP/TQ as a pinfor-pin replacement for the 8XC51BH, VSS1 can be unconnected without loss of compatibility. (Not available on DIP) — VSS2 GND Secondary Ground 2. This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the 8xC251TA/TB/TP/TQ as a pinfor-pin replacement for the 8XC51FX, VSS2 can be unconnected without loss of compatibility. (Not available on DIP) — ADVANCE INFORMATION 9 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 6. Signal Descriptions (Sheet 3 of 3) Signal Name Type Alternate Function Description WAIT# I Real-time Wait State Input. The real-time WAIT# input is enabled by writing a logical ‘1’ to the WCON.0 (RTWE) bit at S:A7H. During bus cycles, the external memory system can signal ‘system ready’ to the microcontroller in real time by controlling the WAIT# input signal on the port 1.6 input. P1.6/CEX3 WCLK O Wait Clock Output. The real-time WCLK output is driven at port 1.7 (WCLK) by writing a logical ‘1’ to the WCON.1 (RTWCE) bit at S:A7H. When enabled, the WCLK output produces a square wave signal with a period of one-half the oscillator frequency. P1.7/CEX4/ A17 WR# O Write. Write signal output to external memory. P3.6 XTAL1 I Input to the On-chip, Inverting, Oscillator Amplifier. To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. XTAL1 is the clock source for internal timing. — XTAL2 O Output of the On-chip, Inverting, Oscillator Amplifier. To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave XTAL2 unconnected. — NOTE: The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (compatible with 44-pin PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0). Table 7. Memory Signal Selections (RD1:0) RD1:0 10 P1.7/CEX/ A17/WCLK P3.7/RD#/A16 PSEN# WR# Features 0 0 A17 A16 Asserted for all addresses Asserted for writes to all memory locations 256-Kbyte external memory 0 1 P1.7/CEX4/ WCLK A16 Asserted for all addresses Asserted for writes to all memory locations 128-Kbyte external memory 1 0 P1.7/CEX4/ WCLK P3.7 only Asserted for all addresses Asserted for writes to all memory locations 64-Kbyte external memory. One additional port pin. 1 1 P1.7/CEX4/ WCLK RD# asserted for addresses ≤ 7F:FFFFH Asserted for ≥ 80:0000H Asserted only for writes to MCS 51 microcontroller data memory locations. 64-Kbyte external memory. Compatible with MCS 51 microcontrollers. ADVANCE INFORMATION 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 5.0 ADDRESS MAP Table 8. 8xC251TA/TB/TP/TQ Address Map Internal Address) Description Notes FF:FFFFH FF:4000H External Memory except the top eight bytes (FF:FFF8H–FF:FFFFH) which are reserved for the configuration array. 1, 3, 10 FF:3FFFH FF:0000H External memory or on-chip nonvolatile memory (8Kbytes FF:0000H - FF:1FFFH, 16Kbytes FF:0000H - FF:3FFFH). 3, 4, 5 FE:FFFFH FE:0000H External Memory FD:FFFFH 02:0000H Reserved 01:FFFFH 01:0000H External Memory 00:FFFFH 00:E000H External memory or with configuration bit EMAP# = 0, addresses in this range access on-chip code memory in region FF: (16 Kbyte devices only). 00:DFFFH 00:0420H External Memory 00:041FH 00:0080H On-chip RAM (512 bytes 00:0020H - 00:021FH, 1024 bytes 00:0020H - 00:041FH) 00:007FH 00:0020H On-chip RAM 00:001FH 00:0000H Storage for R0–R7 of Register File 3 6 3 5, 7 7 7 8 2, 9 NOTES: 1. 18 address lines are bonded out (A15:0, A16:0, or A17:0 selected during chip configuration). 2. The special function registers (SFRs) and the register file have separate internal address spaces. 3. Data in this area is accessible by indirect addressing only. 4. Devices reset into internal or external starting locations depending on the state of EA# and configuration byte information See EA#. 5. The 16-Kbyte ROM devices allow internal locations FF:2000H–FF:3FFFH to map into region 00:. In this case, if EA# = 1, a data read to 00:E000H–00:FFFFH is redirected to internal ROM (see bit 1 in UCONFIG0). This is not available for 8Kbyte ROM devices. 6. This reserved area returns indeterminate values. 7. Data is accessible by direct and indirect addressing. 8. Data is accessible by direct, indirect, and bit addressing. 9. Data is accessible by direct, indirect, and register addressing. 10. Eight addresses at the top of all external memory maps are reserved for current and future device configuration byte information. ADVANCE INFORMATION 11 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 6.0 ELECTRICAL CHARACTERISTICS NOTICE:This document contains information on products being sampled or in the initial production phase of development. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. ABSOLUTE MAXIMUM RATINGS Storage Temperature .................................. -65°C to +150°C Voltage: EA# Pin with respect to VSS ............. 0 V to +13.0 V Voltage: Any other Pin with respect to VSS... -0.5 V to +6.5 V IOL per I/O Pin............................................................... 15 mA Power Dissipation ......................................................... 1.5 W WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. OPERATING CONDITIONS TA (Ambient Temperature Under Bias): Commercial ................................................. 0°C to +70°C Express........................................................... -40°C to +85°C VCC (Digital Supply Voltage) ............................ 4.5 V to 5.5 V VSS ................................................................................... 0 V NOTE:Maximum power dissipation is based on package heat-transfer limitations, not device power consumption. 6.1 D.C. Characteristics Parameter values apply to all devices unless otherwise indicated. Table 9. DC Characteristics at VCC = 4.5 – 5.5 V (Sheet 1 of 2) Max Units VIL Symbol Input Low Voltage (except EA#) Parameter Min -0.5 Typical 0.2 VCC – 0.1 V VIL1 Input Low Voltage (EA#) 0 0.2 VCC – 0.3 V VIH Input High Voltage (except XTAL1, RST) 0.2 VCC + 0.9 VCC + 0.5 V VIH1 Input High Voltage (XTAL1, RST) 0.7 VCC VCC + 0.5 V VOL Output Low Voltage (Port 1, 2, 3) 0.3 V Test Conditions IOL = 100 µA 0.45 IOL = 1.6 mA 1.0 IOL = 3.5 mA (Note 1, Note 2) VOL1 Output Low Voltage (Port 0, ALE, PSEN#) 0.3 V IOL = 200 µA 0.45 IOL = 3.2 mA 1.0 IOL = 7.0 mA (Note 1, Note 2) VOH 12 Output High Voltage (Port 1, 2, 3, ALE, PSEN#) V CC – 0.3 V IOH = -10 µA VCC – 0.7 IOH = -30 µA VCC – 1.5 IOH = -60 µA (Note 3) ADVANCE INFORMATION 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 9. DC Characteristics at VCC = 4.5 – 5.5 V (Sheet 2 of 2) Symbol VOH1 VOH2 Parameter Output High Voltage (Port 0 in External Address) Output High Voltage (Port 2 in External Address during Page Mode) IIL Logical 0 Input Current (Port 1, 2, 3) ILI Min Typical Max VCC – 0.3 Units V Test Conditions IOH = -200 µA VCC – 0.7 IOH = -3.2 mA VCC – 1.5 IOH = -7.0 mA VCC – 0.3 V IOH = -200 µA VCC – 0.7 IOH = -3.2 mA VCC – 1.5 IOH = -7.0 mA -50 µA VIN = 0.45 V Input Leakage Current (Port 0) +/-10 µA 0.45 < VIN < VCC ITL Logical 1-to-0 Transition Current (Port 1, 2, 3) -650 µA VIN = 2.0 V RRST RST Pulldown Resistor 225 kΩ CIO Pin Capacitance 10 (Note 4) IPD Powerdown Current 10 (Note 4) 20 µA IDL Idle Mode Current 35 (Note 4) 44 mA FOSC = 24 MHz ICC Operating Current 70 (Note 4) 83 mA FOSC = 24 MHz 40 pF FOSC = 24 MHz TA = 25 °C NOTES: 1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows: • Maximum I OL per port pin:10 mA • Maximum I OL per 8-bit port: port 0 26 mA ports 1–3 15 mA • Maximum Total IOL for all output pins 71 mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4 V on the low-level outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8 V. It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic. 3. Capacitive loading on ports 0 and 2 causes the V OH on ALE and PSEN# to drop below the specification when the address lines are stabilizing. Typical values are obtained using VCC = 5.0, TA = 25°C and are not guaranteed. ADVANCE INFORMATION 13 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 6.2 Definition of AC Symbols 6.3 Test Conditions: Capacitive load on all pins = 50 pF. Table 10. AC Timing Symbol Definitions Signals A.C. Characteristics Table 11 lists AC timing parameters for the with no wait states. External wait states can be added by extending PSEN#/RD#/WR# and/or by extending ALE. In the table, Notes 2 and 3 mark parameters affected by an Conditions A Address H High D Data In L Low L ALE V Valid Q Data Out X No Longer Valid R RD#/PSEN# Z Floating W WR# ALE wait state, and Notes 4 and 5 mark parameters affected by a PSEN#/RD#/WR# wait state. Figure 6 through Figure 8 show the bus cycles with the timing parameters. Table 11. AC Characteristics (Sheet 1 of 4) Symbol Parameter @ Max FOSC (1) FOSC Variable Min Max Min Max 0 24 FOSC XTAL1 Frequency N/A N/A TOSC 1/FOSC @ 16MHz @ 24MHz N/A N/A TLHLL ALE Pulse Width @ 16MHz @ 24MHz 55.5 34.7 (0.5+M) 2TOSC -7 TAVLL Address Valid to ALE Low @ 16MHz @ 24MHz 49.5 28.7 (0.5+M) 2TOSC-13 MHz ns 62.5 41.7 ns (3) ns (3) TLLAX Address Hold after ALE Low @ 16MHz @ 24MHz 10 10 10 TLLAXA Address Hold after ALE Low @ 16MHz @ 24MHz 20 20 20 TRLRH RD# or PSEN# Pulse Width @ 16MHz @ 24MHz 115 73.4 (1+N) 2TOSC-10 TRLRHA RD# or PSEN# Pulse Width @ 16MHz @ 24MHz 93 51.4 (1+N) 2TOSC-32 TWLWH WR# Pulse Width @ 16MHz @ 24MHz 115 73.4 (1+N) 2TOSC-10 TWLWHA WR# Pulse Width @ 16MHz @ 24MHz 93 51.4 (1+N) 2TOSC-32 14 Units ns (4) ns (5) ns (3,4) ns (3,5) ns (3,4) ns (3,5) ADVANCE INFORMATION 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 11. AC Characteristics (Sheet 2 of 4) Symbol TLLRL TLLRLA Parameter ALE Low to RD# or PSEN# Low @ 16MHz @ 24MHz @ Max FOSC (1) Min Max FOSC Variable Min 10 10 10 20 20 20 TLHAX ALE High to Address Hold @ 16MHz @ 24MHz 98 56.4 (1+M) 2TOSC-27 TLHAXA ALE High to Address Hold @ 16MHz @ 24MHz 77.5 56.7 (0.5+M) 2TOSC +15 TRLDV RD# or PSEN# Low to Valid Data/Instruction In @ 16MHz @ 24MHz TRHDX TRLAZ TRHDZ1 TRHDZ1A TRHDZ2 TRHDZ2A ns (5) ns (3,4) ns (3,5) ns (3,4) 95 53.4 RD#/PSEN# Low to Address Float @ 16MHz @ 24MHz Instruction Float after PSEN# or RD# high @ 16MHz @ 24MHz Instruction Float after PSEN# or RD# high @ 16MHz @ 24MHz Data Float after PSEN# or RD# high @ 16MHz @ 24MHz Data Float after PSEN# or RD# high @ 16MHz @ 24MHz ADVANCE INFORMATION (1+N) 2TOSC-30 ns (3,5) RD# or PSEN# Low to Valid Data/Instruction In @ 16MHz @ 24MHz Data/Instruction Hold after RD# or PSEN# High @ 16MHz @ 24MHz Units ns (4) ALE Low to RD# or PSEN# Low @ 16MHz @ 24MHz TRLDVA Max 75 33.4 (1+N) 2TOSC-50 ns 0 0 0 ns 10 10 10 ns (4) 10 10 10 ns (5) 57.5 36.7 TOSC-5 ns (4) 135 93.4 2TOSC +10 ns (5) 182.5 120.1 3TOSC-5 15 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 11. AC Characteristics (Sheet 3 of 4) Symbol TRHLH2 TRHLH2A TRHLH1 TRHLH1A Parameter RD# or PSEN# High to ALE High (data) @ 16MHz @ 24MHz RD# or PSEN# High to ALE High (data) @ 16MHz @ 24MHz RD# or PSEN# High to ALE High (Instruction) @ 16MHz @ 24MHz RD# or PSEN# High to ALE High (Instruction) @ 16MHz @ 24MHz @ Max FOSC (1) Min FOSC Variable Max Min 135 93.4 2TOSC+10 ns (5) 180.5 118.1 3TOSC -7 ns (4) 10 10 10 ns (5) 55.5 34.7 TOSC-7 ns (4) WR# High to ALE Low @ 16MHz @ 24MHz 135 93.4 2TOSC+10 TWHLHA WR# High to ALE Low @ 16MHz @ 24MHz 180.5 118.1 3TOSC -7 TAVDV1 Address (mux’d) valid to Valid Data/ Instruction In @ 16MHz @ 24MHz TAVDV2 TAVDV3 TAVRL TAVRLA 16 ns (5) ns (3,4) 190 106.8 Address (mux’d) valid to Valid Data/ Instruction In @ 16MHz @ 24MHz 159.5 97.1 (1.5+M+N) 2TOSC-28 ns (3) 212 128.8 (2+M+N) 2TOSC-38 ns (3) Address (P0)Valid to Valid Instruction In @ 16MHz @ 24MHz Address Valid to RD# or PSEN# Low @ 16MHz @ 24MHz (2+M+N) 2TOSC-60 ns (3,4) Address (demux’d) valid to Valid Data/Instruction In @ 16MHz @ 24MHz Address Valid to RD# or PSEN# Low @ 16MHz @ 24MHz Units ns (4) TWHLH TAVDV1A Max 65 23.4 (1+N) 2TOSC-60 ns (3,4) 85 43.4 (1+M) 2TOSC-40 ns (3,5) 72.5 51.7 (0.5+M) 2TOSC+10 ADVANCE INFORMATION 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 11. AC Characteristics (Sheet 4 of 4) Symbol TAVWL1 TAVWL1A TAVWL2 TAVWL2A Parameter Address (mux’d) Valid to WR# Low @ 16MHz @ 24MHz Address (mux’d) Valid to WR# Low @ 16MHz @ 24MHz Address (demux’d) Valid to WR# Low @ 16MHz @ 24MHz @ Max FOSC (1) Min Max FOSC Variable Min Max Units ns (3,4) 85 43.4 (1+M) 2TOSC-40 ns (3,5) 72.5 51.7 (0.5+M) 2TOSC +10 ns (3,4) 108 66.4 (1+M) 2TOSC-17 ns (3,5) Address (demux’d) Valid to WR# Low @ 16MHz @ 24MHz 135 93.4 (1+M) 2TOSC +10 TWHQX Data Hold after WR# High @ 16MHz @ 24MHz 49.5 28.7 TOSC-13 TQVWH Data Valid to WR# High @ 16MHz @ 24MHz 110 68.4 (1+N) 2TOSC-15 TWHAX WR# High to Address Hold @ 16MHz @ 24MHz 112 70.4 2TOSC-13 ns ns (3) ns NOTES: 1. 24 MHz XTAL Frequency. 2. Specifications for PSEN# are identical to those for RD#. 3. In the formula, M = number of wait states (0 or 1) for ALE and N = Number of wait states (0,1,2 or 3) for RD#/PSEN#/WR#. 4. Device configured with the default data float timing for fast memory interface (EDF# = 1). 5. Device configured with extended data float timing for slow memory interface (EDF# = 0). ADVANCE INFORMATION 17 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 6.3.1 External Bus Cycles, Nonpage Mode TOSC XTAL1 ALE TLHLL† TRLRH† TRHLH1 † TLLRL RD#/PSEN# TRLDV† TRLAZ TLHAX† TAVLL P0 † TLLAX A7:0 TAVRL† TRHDZ1 TRHDX D7:0 Instruction In TAVDV1† TAVDV2† P2/A16/A17 A15:8/A16/A17 † The value of this parameter depends on wait states. See the table of AC characteristics. A4211-03 Figure 5. External Bus Cycle: Code Fetch (Nonpage Mode) 18 ADVANCE INFORMATION 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER TOSC XTAL1 ALE TLHLL† TRLRH† TLLRL† TRHLH2 RD#/PSEN# TRLDV† TRLAZ TLHAX† TRHDZ2 TAVLL† P0 TLLAX A7:0 TAVRL† TRHDX D7:0 Data In TAVDV1† TAVDV2† P2/A16/A17 A15:8/A16/A17 † The value of this parameter depends on wait states. See the table of AC characteristics. A4210-03 Figure 6. External Bus Cycle: Data Read (Nonpage Mode) ADVANCE INFORMATION 19 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER TOSC XTAL1 ALE TLHLL† TWLWH† TWHLH WR# TLHAX† TAVLL† TLLAX P0 P2/A16/A17 TQVWH TWHQX A7:0 TAVWL1† TAVWL2† D7:0 Data Out TWHAX A15:8/A16/A17 † The value of this parameter depends on wait states. See the table of AC characteristics. A4179-01 Figure 7. External Bus Cycle: Data Write (Nonpage Mode) 20 ADVANCE INFORMATION 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 6.3.2 External Bus Cycles, Page Mode TOSC XTAL1 ALE TLHLL† TLLRL† ††† RD#/PSEN# TRLDV† TRLAZ TRHDZ1 TLHAX† TAVLL† P2 TRHDX TLLAX A15:8 TAVRL† D7:0 TAVDV1† TAVDV2† P0/A16/A17 D7:0 Instruction In Instruction In A7:0/A16/A17 Page Miss†† TAVDV3 A7:0/A16/A17 Page Hit†† † The value of this parameter depends on wait states. See the table of AC characteristics. †† A page hit (i.e., a code fetch to the same 256-byte "page" as the previous code fetch) requires one state (2TOSC); a page miss requires two states (4TOSC). ††† During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle. A4213-02 Figure 8. External Bus Cycle: Code Fetch (Page Mode) ADVANCE INFORMATION 21 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER TOSC XTAL1 ALE TLHLL† TRLRH† † TRHLH2 TLLRL RD#/PSEN# TRLDV† TRLAZ TLHAX† TRHDZ2 TAVLL† P2 TLLAX A15:8 TAVRL† TRHDX D7:0 Data In TAVDV1† TAVDV2† P0/A16/A17 A7:0/A16/A17 † The value of this parameter depends on wait states. See the table of AC characteristics. A4212-03 Figure 9. External Bus Cycle: Data Read (Page Mode) 22 ADVANCE INFORMATION 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER TOSC XTAL1 ALE TLHLL† TWLWH† TWHLH WR# TLHAX† TAVLL† TLLAX P2 TQVWH TWHQX A15:8 TAVWL1† TAVWL2† P0/A16/A17 D7:0 Data Out TWHAX A7:0/A16/A17 † The value of this parameter depends on wait states. See the table of AC characteristics. A4182-01 Figure 10. External Bus Cycle: Data Write (Page Mode) ADVANCE INFORMATION 23 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 6.3.3 Definition of Real-Time Wait Symbols Table 12. Real-time Wait Timing Symbol Definitions Signals 6.3.4 Conditions A Address L Low D Data X Hold C WCLK V Setup Y WAIT# W WR# R RD#/PSEN# External Bus Cycles, Real-Time Wait States State 1 State 2 State 3 State 1 (next cycle) WCLK TCLYX min TCLYX max ALE TCLYV RD#/PSEN# RD#/PSEN# stretched TRLYX max TRLYX min TRLYV WAIT# P0 P2 A7:0 D7:0 A15:8 stretched stretched A7:0 A15:8 A5000-02 Figure 11. External Bus Cycle: Code Fetch/Data Read (Nonpage Mode) 24 ADVANCE INFORMATION 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER State 1 State 2 State 3 State 4 WCLK TCLYX min TCLYX max ALE TCLYV WR# WR# stretched TWLYX max TWLYX min TWLYV WAIT# P0 D7:0 A7:0 P2 A15:8 stretched stretched A5002-02 Figure 12. External Bus Cycle: Data Write (Nonpage Mode) ADVANCE INFORMATION 25 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER State 1 State 2 State 3 State 1 (next cycle) WCLK TCLYX min TCLYX max ALE TCLYV RD#/PSEN# RD#/PSEN# stretched TRLYX max TRLYX min TRLYV WAIT# P2 P0 A15:8 D7:0 A7:0 stretched A15:8 stretched A7:0 A5001-02 Figure 13. External Bus Cycle: Code Fetch/Data Read (Page Mode) 26 ADVANCE INFORMATION 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER State 1 State 2 State 3 State 4 WCLK TCLYX min TCLYX max ALE TCLYV WR# WR# stretched TWLYX max TWLYX min TWLYV WAIT# P2 A15:8 D7:0 P0 stretched A7:0 stretched A5003-02 Figure 14. External Bus Cycle: Data Write (Page Mode) Table 13. Real-Time Wait AC Timing Min Max TCLYV Symbol Wait Clock Low to Wait Set-up Parameter 0 TOSC – 13 Units ns TCLYX Wait Hold after Wait Clock Low (2W)TOSC + 5 (1+2W)TOSC – 20 ns (1) TRLYV PSEN#/RD# Low to Wait Set-up 0 TOSC – 13 ns TRLYVA PSEN#/RD# Low to Wait Set-up 0 TOSC – 35 ns (2) TRLYX Wait Hold after PSEN#/RD# Low (2W)TOSC + 5 (1+2W)TOSC – 20 ns (1) TWLYV WR# Low to Wait Set-up 0 TOSC – 13 ns TWLYVA WR# Low to Wait Set-up 0 TOSC – 35 ns (2) TWLYX Wait Hold after WR# Low (2W)TOSC + 5 (1+2W)TOSC – 20 ns (1) NOTES: 1. W = 0, 1, 2 — is the number of real time wait states. 2. Device configured with the extended data float timing. ADVANCE INFORMATION 27 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 6.4 AC Characteristics — Serial Port, Shift Register Mode Table 14. Serial Port Timing — Shift Register Mode Symbol Parameter TXLXL Serial Port Clock Cycle Time TQVSH Min Max Units 12TOSC ns Output Data Setup to Clock Rising Edge 10TOSC – 133 ns 2TOSC – 117 ns TXHQX Output Data hold after Clock Rising Edge TXHDX Input Data Hold after Clock Rising Edge TXHDV Clock Rising Edge to Input Data Valid 0 ns 10TOSC – 133 ns TXLXL TXD TXHQX Set TI† TQVXH RXD (Out) 0 1 2 Valid 7 6 5 TAV† TXHDV RXD (In) 4 3 Set RI† TXHDX Valid Valid Valid Valid Valid Valid Valid †TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit. A2592-02 Figure 15. Serial Port Waveform — Shift Register Mode 28 ADVANCE INFORMATION 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER 6.5 External Clock Drive Table 15. External Clock Drive Symbol Parameter 1/TCLCL Oscillator Frequency (FOSC) Min TCHCX High Time 20 TCLCX Low Time 20 TCLCH Rise Time 10 ns TCHCL Fall Time 10 ns Units 24 MHz ns ns TCLCH VCC – 0.5 Max TCHCX 0.7 VCC TCLCX 0.45 V 0.2 VCC – 0.1 TCHCL TCLCL A4119-01 Figure 16. External Clock Drive Waveforms Outputs Inputs VCC – 0.5 0.2 VCC + 0.9 VIH MIN 0.45 V 0.2 VCC – 0.1 VOL MAX AC inputs during testing are driven at VCC – 0.5V for a logic 1 and 0.45 V for a logic 0. Timing measurements are made at a min of VIH for a logic 1 and VOL for a logic 0. A4118-01 Figure 17. AC Testing Input, Output Waveforms ADVANCE INFORMATION 29 8xC251TA/TB/TP/TQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER VLOAD + 0.1 V VOH – 0.1 V Timing Reference Points VLOAD VOL + 0.1 V VLOAD – 0.1 V For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH/VOL level occurs with IOL/IOH = ± 20 mA. A4117-01 Figure 18. Float Waveforms 7.0 THERMAL CHARACTERISTICS All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. Values change depending on operating conditions and application requirements. The Intel Packaging Handbook (order number 240800) describes Intel’s thermal impedance test methodology. Table 16. Thermal Characteristics ΘJA ΘJC 44-pin PLCC 46°C/W 16°C/W 40-pin PDIP 45°C/W 16°C/W Package Type 30 ADVANCE INFORMATION