8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER TEMPERATURE RANGE PROCESS INFORMATION With the commercial (standard) temperature option, the device operates over the temperature range 0§ C to a 70§ C. The express temperature option provides b 40§ C to a 85§ C device operation. This device is manufactured on a complimentary high-performance metal-oxide semiconductor (CHMOS) process. Additional process and reliability information is available in Intel’s Components Quality and Reliability Handbook (order number 210997). PROLIFERATION OPTIONS All thermal impedance data is approximate for static air conditions at 1 watt of power dissipation. Values change depending on operating conditions and application requirements. The Intel Packaging Handbook (order number 240800) describes Intel’s thermal impedance test methodology. Table 1 lists the proliferation options. See Figure 2 for the 8XC151SA/SB family nomenclature. Table 1. Proliferation Options 8XC151SA/SB (0 MHz–16 MHz; 5V g 10%) Table 2. Thermal Characteristics CPU-only Package Type iJA iJC 83C151SA 8K ROM 44-Lead PLCC 46§ C/W 16§ C/W 83C151SB 16K ROM 40-Pin PDIP 45§ C/W 16§ C/W 87C151SA 8K OTPROM 87C151SB 16K OTPROM 80C151SB PACKAGE OPTIONS Table 3 lists the 8XC151SA/SB packages. Table 3. Package Information Pkg. Definition Temperature N 44-Lead PLCC 0§ C to a 70§ C P 40-Pin Plastic DIP 0§ C to a 70§ C TN 44-Lead PLCC b 40§ C to a 85§ C TP 40-Pin Plastic DIP b 40§ C to a 85§ C 3 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 272814 – 2 Figure 2. The 8XC151SA/SB Family Nomenclature Table 4. Description of Product Nomenclature Parameter Options Temperature and Burn-in Options no mark Commercial operating temperature range (0§ C to 70§ C) with Intel standard burn-in. T Express operating temperature range ( b 40§ C to 85§ C) with Intel standard burn-in. N 44-lead Plastic Leaded Chip Carrier (PLCC) Packaging Options Program Memory Options Process Information Product Family Device Memory Options Device Speed 4 Description P 40-pin Plastic Dual In-line Package (PDIP) 0 Without ROM/OTPROM 3 ROM 7 User programmable OTPROM C CHMOS 151 SA/SB 16 8-bit controller architecture 256 bytes RAM/8/16 Kbyte ROM/OTPROM or without ROM/ OTPROM External clock frequency 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 272814 – 3 Figure 3. 8XC151SA/SB 44-Lead PLCC Package 5 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 272814 – 4 Figure 4. 8XC151SA/SB 40-Pin PDIP and Ceramic DIP Packages 6 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 5. PLCC/DIP Signal Assignment Arranged by Functional Categories Address & Data Input/Output Name PLCC DIP Name PLCC DIP AD0/P0.0 43 39 P1.0/T2 2 1 AD1/P0.1 42 38 P1.1/T2EX 3 2 AD2/P0.2 41 37 P1.2/ECI 4 3 AD3/P0.3 40 36 P1.3/CEX0 5 4 AD4/P0.4 39 35 P1.4/CEX1 6 5 AD5/P0.5 38 34 P1.5/CEX2 7 6 AD6/P0.6 37 33 P1.6/CEX3 8 7 AD7/P0.7 36 32 P1.7/CEX4 9 8 A8/P2.0 24 21 P3.0/RXD 11 10 A9/P2.1 25 22 P3.1/TXD 13 11 A10/P2.2 26 23 P3.4/T0 16 14 A11/P2.3 27 24 P3.5/T1 17 15 A12/P2.4 28 25 A13/P2.5 29 26 A14/P2.6 30 27 A15/P2.7 31 28 Power & Ground Name PLCC DIP VCC 44 40 VCC2 12 Ð VSS 22 20 Name PLCC DIP VSS1 1 Ð P3.2/INT0Ý 14 12 VSS2 23, 34 Ð P3.3/INT1Ý 15 13 EAÝ/VPP 35 31 EAÝ/VPP 35 31 RST 10 9 Processsor Control XTAL1 21 18 XTAL2 20 19 Bus Control & Status Name PLCC DIP P3.6/WRÝ 18 16 P3.7/RDÝ 19 17 ALE/PROGÝ 33 30 PSENÝ 32 29 7 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 6. Signal Assignments Arranged by Package Number 8 PLCC DIP Name PLCC DIP Name 1 Ð VSS1 23 Ð VSS2 2 1 P1.0/T2 24 21 A8/P2.0 3 2 P1.1/T2EX 25 22 A9/P2.1 4 3 P1.2/ECI 26 23 A10/P2.2 5 4 P1.3/CEX0 27 24 A11/P2.3 6 5 P1.4/CEX1 28 25 A12/P2.4 7 6 P1.5/CEX2 29 26 A13/P2.5 8 7 P1.6/CEX3 30 27 A14/P2.6 9 8 P1.7/CEX4 31 28 A15/P2.7 10 9 RST 32 29 PSENÝ 11 10 P3.0/RXD 33 30 ALE/PROGÝ 12 Ð VCC2 34 Ð VSS2 13 11 P3.1/TXD 35 31 EAÝ/Vpp 14 12 P3.2/INT0Ý 36 32 AD7/P0.7 15 13 P3.3/INT1Ý 37 33 AD6/P0.6 16 14 P3.4/T0 38 34 AD5/P0.5 17 15 P3.5/T1 39 35 AD4/P0.4 18 16 P3.6/WRÝ 40 36 AD3/P0.3 19 17 P3.7/RDÝ 41 37 AD2/P0.2 20 18 XTAL2 42 38 AD1/P0.1 21 19 XTAL1 43 39 AD0/P0.0 22 20 VSS 44 40 VCC 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER SIGNAL DESCRIPTIONS Table 7. Signal Descriptions Signal Name Type Description Multiplexed With A15:8 ² O Address Lines. Upper address lines for the external bus. P2.7:0 AD7:0 ² I/O Address/Data Lines. Multiplexed lower address lines and data lines for external memory. P0.7:0 O Address Latch Enable. ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A15:8 and AD7:0. An external latch can use ALE to demultiplex the address from the address/data bus. PROGÝ I/O Programmable Counter Array (PCA) Input/Output Pins. These are input signals for the PCA capture mode and output signals for the PCA compare mode and PCA PWM mode. P1.6:3 P1.7 EAÝ I External Access. Directs program memory accesses to on-chip or off-chip code memory. For EAÝ e 0, all program memory accesses are off-chip. For EAÝ e 1, an access is to on-chip ROM/OTPROM if the address is within the range of the on-chip ROM/OTPROM; otherwise the access is off-chip. The value of EAÝ is latched at reset. For devices without on-chip ROM/OTPROM, EAÝ must be strapped to ground. VPP ECI I PCA External Clock Input. External clock input to the 16-bit PCA timer. P1.2 INT1:0Ý I External Interrupts 0 and 1. These inputs set bits IE1:0 in the TCON register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by a falling edge on INT1Ý/INT0Ý. If bits INT1:0 are clear, bits IE1:0 are set by a low level on INT1:0Ý. PROGÝ I Programming Pulse. The programming pulse is applied to this pin for programming the on-chip OTPROM. ALE CEX4:0 P3.3:2 ALE P0.7:0 I/O Port 0. This is an 8-bit, open-drain, bidirectional I/O port. AD7:0 P1.0 P1.1 P1.2 P1.7:3 I/O Port 1. This is an 8-bit, bidirectional I/O port with internal pullups. T2 T2EX ECI CEX3:0 CEX4 P2.7:0 I/O Port 2. This is an 8-bit, bidirectional I/O port with internal pullups. A15:8 ² The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (compatible with 44-lead PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0). 9 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 7. Signal Descriptions (Continued) Signal Name P3.0 P3.1 P3.3:2 P3.5:4 P3.6 P3.7 Type I/O Description Port 3. This is an 8-bit, bidirectional I/O port with internal pullups. PSENÝ O Program Store Enable. Read signal output. This output is asserted for a memory address range that depends on bits RD0 and RD1 in configuration byte UCONFIG0. RDÝ O Read. Read signal output to external data memory. RST I Reset. Reset input to the chip. Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The port pins are driven to their reset conditions when a voltage greater than VIH1 is applied, whether or not the oscillator is running. This pin has an internal pulldown resistor, which allows the device to be reset by connecting a capacitor between this pin and VCC. Multiplexed With RXD TXD INT1:0Ý T1:0 WRÝ RDÝ Ð P3.7 Ð Asserting RST when the chip is in idle mode or powerdown mode returns the chip to normal operation. RXD I/O Receive Serial Data. RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2, and 3. P3.0 T1:0 I Timer 1:0 External Clock Inputs. When timer 1:0 operates as a counter, a falling edge on the T1:0 pin increments the count. P3.5:4 I/O Timer 2 Clock Input/Output. For the timer 2 capture mode, this signal is the external clock input. For the clock-out mode, it is the timer 2 clock output. P1.0 T2EX I Timer 2 External Input. In timer 2 capture mode, a falling edge initiates a capture of the timer 2 registers. In auto-reload mode, a falling edge causes the timer 2 registers to be reloaded. In the updown counter mode, this signal determines the count direction: 1 e up, 0 e down. P1.1 TXD O Transmit Serial Data. TXD outputs the shift clock in serial I/O mode 0 and transmits serial data in serial I/O modes 1, 2, and 3. P3.1 VCC PWR Supply Voltage. Connect this pin to the a 5V supply voltage. Ð VCC2 PWR Secondary Supply Voltage 2. This supply voltage connection is provided to reduce power supply noise. Connection of this pin to the a 5V supply voltage is recommended. However, when using the 8XC151SA/SB as a pin-for-pin replacement for the 8XC51FX, VSS2 can be unconnected without loss of compatibility. (Not available on DIP) Ð VPP I Programming Supply Voltage. The programming supply voltage is applied to this pin for programming the on-chip OTPROM. EAÝ T2 ² The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (compatible with 44-lead PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0). 10 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 7. Signal Descriptions (Continued) Signal Name Type VSS GND Circuit Ground. Connect this pin to ground. VSS1 GND Secondary Ground. This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the 8XC151SA/SB as a pinfor-pin replacement for the 8XC51BH, VSS1 can be unconnected without loss of compatibility. (Not available on DIP) VSS2 GND Secondary Ground 2. This ground is provided to reduce ground bounce and improve power supply bypassing. Connection of this pin to ground is recommended. However, when using the 8XC151SA/SB as a pin-for-pin replacement for the 8XC51FX, VSS2 can be unconnected without loss of compatibility. (Not available on DIP) WRÝ O Write. Write signal output to external memory. XTAL1 I Input to the On-chip, Inverting, Oscillator Amplifier. To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. XTAL1 is the clock source for internal timing. XTAL2 O Output of the On-chip, Inverting, Oscillator Amplifier. To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave XTAL2 unconnected. Description Multiplexed With Ð P3.6 Ð ² The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for the nonpage-mode chip configuration (compatible with 44-lead PLCC and 40-pin DIP MCS 51 microcontrollers). If the chip is configured for page-mode operation, port 0 carries the lower address bits (A7:0), and port 2 carries the upper address bits (A15:8) and the data (D7:0). 11 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS* Ambient Temperature under Bias: Commercial ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0§ C to a 70§ C Express ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 40§ C to a 85§ C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 65§ C to a 150§ C Voltage on EAÝ/VPP Pin to VSS ÀÀÀÀÀ0V to a 13.0V Voltage on Any other Pin to VSS ÀÀÀ b 0.5V to a 6.5V IOL per I/O Pin ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ15 mA Power DissipationÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1.5W NOTE: Maximum power dissipation is based on package heat-transfer limitations, not device power consumption. OPERATING CONDITIONS* TA (Ambient Temperature Under Bias): Commercial ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0§ C to a 70§ C Express ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 40§ C to a 85§ C VCC (Digital Supply Voltage) ÀÀÀÀÀÀÀÀÀÀ4.5V to 5.5V VSS ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0V 12 NOTICE: This document contains information on products in the design phase of development. Do not finalize a design with this information. Revised information will be published when the product is available. Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER DC CHARACTERISTICS Parameter values apply to all devices unless otherwise indicated. Table 8. DC Characteristics at VCC e 4.5V b 5.5V Max Units VIL Symbol Input Low Voltage (except EAÝ) Parameter b 0.5 Min Typical 0.2VCC b 0.1 V VIL1 Input Low Voltage (EAÝ) 0 0.2VCC b 0.3 V VIH Input High Voltage (except XTAL1, RST) 0.2VCC a 0.9 VCC a 0.5 V VIH1 Input High Voltage (XTAL1, RST) 0.7VCC VCC a 0.5 V VOL Output Low Voltage (Port 1, 2, 3) 0.3 0.45 1.0 V IOL e 100 mA IOL e 1.6 mA IOL e 3.5 mA (Note 1, Note 2) VOL1 Output Low Voltage (Port 0, ALE, PSENÝ) 0.3 0.45 1.0 V IOL e 200 mA IOL e 3.2 mA IOL e 7.0 mA (Note 1, Note 2) VOH Output High Voltage (Port 1, 2, 3, ALE, PSENÝ) V IOH e b 10 mA IOH e b 30 mA IOH e b 60 mA (Note 3) VCC b 0.3 VCC b 0.7 VCC b 1.5 Test Conditions NOTES: 1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: port 0 26 mA ports 1–3 15 mA Maximum Total IOL for all output pins 71 mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4V on the low-level outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8V. It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic. 3. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSENÝ to drop below the specification when the address lines are stabilizing. 4. Typical values are obtained using VCC e 5.0, TA e 25§ C and are not guaranteed. 13 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 8. DC Characteristics at VCC e 4.5V b 5.5V (Continued) Symbol Parameter Min Typical Max Units Test Conditions VOH1 Output High Voltage (Port 0 in External Address) VCC b 0.3 VCC b 0.7 VCC b 1.5 V IOH e b 200 mA IOH e b 3.2 mA IOH e b 7.0 mA VOH2 Output High Voltage (Port 2 in External Address during Page Mode) VCC b 0.3 VCC b 0.7 VCC b 1.5 V IOH e b 200 mA IOH e b 3.2 mA IOH e b 7.0 mA IIL Logical 0 Input Current (Port 1, 2, 3) b 50 mA VIN e 0.45V ILI Input Leakage Current (Port 0) g 10 mA 0.45 k VIN k VCC ITL Logical 1-to-0 Transition Current (Port 1, 2, 3) b 650 mA VIN e 2.0V RRST RST Pulldown Resistor 225 kX CIO Pin Capacitance 10 (Note 4) IPD Powerdown Current 10 (Note 4) k 20 mA IDL Idle Mode Current 13 (Note 4) 20 mA FOSC e 16 MHz ICC Operating Current 71 (Note 4) 85 mA FOSC e 16 MHz 40 pF FOSC e 16 MHz TA e 25§ C NOTES: 1. Under steady-state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: port 0 26 mA ports 1–3 15 mA Maximum Total IOL for all output pins 71 mA If IOL exceeds the test conditions, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Capacitive loading on ports 0 and 2 may cause spurious noise pulses above 0.4V on the low-level outputs of ALE and ports 1, 2, and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins change from high to low. In applications where capacitive loading exceeds 100 pF, the noise pulses on these signals may exceed 0.8V. It may be desirable to qualify ALE or other signals with a Schmitt trigger or CMOS-level input logic. 3. Capacitive loading on ports 0 and 2 causes the VOH on ALE and PSENÝ to drop below the specification when the address lines are stabilizing. 4. Typical values are obtained using VCC e 5.0, TA e 25§ C and are not guaranteed. 14 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 272814 – 5 All other 8XC151SA/SB pins are unconnected. Figure 5. IPD Test Condition, Powerdown Mode, VCC e 2.0V b 5.5V 15 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER state, and Notes 4 and 5 mark parameters affected by a PSENÝ/RDÝ/WRÝ wait state. AC Characteristics Table 8 lists AC timing parameters for the 8XC151SA/SB with no wait states. External wait states can be added by extending PSENÝ/RDÝ/ WRÝ and/or by extending ALE. In the table, Notes 3 and 5 mark parameters affected by an ALE wait Figures 5 – 11 show the bus cycles with the timing parameters. Table 9. AC Characteristics (Capacitive Loading e 50 pF) Symbol Parameter @ Max FOSC (1) Max Min Max 0 16 FOSC XTAL1 Frequency N/A N/A TOSC 1/FOSC N/A N/A @ @ TLHLL TAVLL TLLAX TRLRH (2) TWLWH TLLRL (2) TLHAX 12 MHz 16 MHz Units MHz ns 83.3 62.5 ALE Pulse Width @ 12 MHz @ 16 MHz 68.3 47.5 Address Valid to ALE Low @ 12 MHz @ 16 MHz 58.3 37.5 Address Hold after ALE Low @ 12 MHz @ 16 MHz 10 10 RDÝ or PSENÝ Pulse Width @ 12 MHz @ 16 MHz 151.6 110 WRÝ Pulse Width @ 12 MHz @ 16 MHz 151.6 110 ALE Low to RDÝ or PSENÝ Low @ 12 MHz @ 16 MHz 58.3 37.5 ALE High to Address Hold @ 12 MHz @ 16 MHz 83.3 62.5 ns (3) (1 a 2M) TOSC b 15 ns (3) (1 a 2M) TOSC b 25 ns 10 ns (4) 2(1 a N) TOSC b 15 ns (4) 2(1 a N) TOSC b 15 ns NOTES: 1. 16 MHz. 2. Specifications for PSENÝ are identical to those for RDÝ. 3. In the formula, M e Number of wait states (0 or 1) for ALE. 4. In the formula, N e Number of wait states (0, 1, 2, or 3) for RDÝ/PSENÝ/WRÝ. 5. ‘‘Typical’’ specifications are untested and not guaranteed. 16 FOSC Variable Min Tosc b 25 ns (3) (1 a 2M) TOSC 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 9. AC Characteristics (Capacitive Loading e 50 pF) (Continued) Symbol Parameter @ Max FOSC (1) Min TRLDV (2) RDÝ/PSENÝ Low to valid Data/Instruction In @ 12 MHz @ 16 MHz TRHDX (2) RDÝ/PSENÝ Data/Instruction Hold after RDÝ and PSENÝ High TRLAZ (2) RDÝ/PSENÝ Low to Address Float TRHDZ1 TRHDZ2 TRHLH1 TRHLH2 TAVDV2 TAVDV3 Typ. e 0 (5) ns (4) 2(1 a N) TOSC b 55 0 2 12 MHz 16 MHz WRÝ High to ALE High @ 12 MHz @ 16 MHz Units Max Typ. e 0 (5) ns 2 ns ns 0 0 0 ns 151.6 110 2TOSC b 15 ns 0 0 0 RDÝ/PSENÝ High to ALE High (Data) @ TAVDV1 0 Data Float after RDÝ/PSENÝ High @ 12 MHz @ 16 MHz @ TWHLH Min 111.6 70 Instruction Float after RDÝ/PSENÝ High @ 12 MHz @ 16 MHz RDÝ/PSENÝ High to ALE High (Instruction) @ 12 MHz @ 16 MHz Max FOSC Variable ns 156.6 115 2TOSC b 10 ns 166.6 125 2TOSC Address (P0) Valid to Valid Data/Instruction In @ 12 MHz @ 16 MHz 253.2 170 Address (P2) Valid to Valid Data/Instruction In @ 12 MHz @ 16 MHz 268.2 185 Address (P0) Valid to Valid Instruction In @ 12 MHz @ 16 MHz 116.6 75 ns (3) 4(1 a M/2) TOSC b 80 ns (3) 4(1 a M/2) TOSC b 65 ns 2TOSC b 50 NOTES: 1. 16 MHz. 2. Specifications for PSENÝ are identical to those for RDÝ. 3. In the formula, M e Number of wait states (0 or 1) for ALE. 4. In the formula, N e Number of wait states (0, 1, 2, or 3) for RDÝ/PSENÝ/WRÝ. 5. ‘‘Typical’’ specifications are untested and not guaranteed. 17 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 9. AC Characteristics (Capacitive Loading e 50 pF) (Continued) Symbol Parameter @ Max FOSC (1) Min TAVRL (2) TAVWL1 TAVWL2 TWHQX TQVWH TWHAX Address Valid to RDÝ/PSENÝ Low @ 12 MHz @ 16 MHz 126.6 85 Address (P0) Valid to WRÝ Low @ 12 MHz @ 16 MHz 126.6 85 Address (P2) Valid to WRÝ Low @ 12 MHz @ 16 MHz 141.6 100 Data Hold after WRÝ High @ 12 MHz @ 16 MHz 58.3 37.5 Data Valid to WRÝ High @ 12 MHz @ 16 MHz 146.6 105 WRÝ High to Address Hold @ 12 MHz @ 16 MHz 146.6 105 Max Min Units Max ns (3) 2(1 a M) TOSC b 40 ns (3) 2(1 a M) TOSC b 40 ns (3) 2(1 a M) TOSC b 25 ns TOSC b 25 ns (4) 2(1 a N) TOSC b 20 ns NOTES: 1. 16 MHz. 2. Specifications for PSENÝ are identical to those for RDÝ. 3. In the formula, M e Number of wait states (0 or 1) for ALE. 4. In the formula, N e Number of wait states (0, 1, 2, or 3) for RDÝ/PSENÝ/WRÝ. 5. ‘‘Typical’’ specifications are untested and not guaranteed. 18 FOSC Variable 2TOSC b 20 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER SYSTEM BUS TIMINGS 272814 – 6 ² The value of this parameter depends on wait states. See the table of AC characteristics. Figure 6. External Read Data Bus Cycle in Nonpage Mode 19 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 272814 – 7 ² The value of this parameter depends on wait states. See the table of AC characteristics. Figure 7. External Instruction Bus Cycle in Nonpage Mode 20 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 272814 – 8 ² The value of this parameter depends on wait states. See the table of AC characteristics. Figure 8. External Write Data Bus Cycle in Nonpage Mode 21 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 272814 – 9 ² The value of this parameter depends on wait states. See the table of AC characteristics. Figure 9. External Read Data Bus Cycle in Page Mode 22 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 272814 – 10 ² The value of this parameter depends on wait states. See the table of AC characteristics. Figure 10. External Write Data Bus Cycle in Page Mode 23 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 272814 – 11 ² The value of this parameter depends on wait states. See the table of AC characteristics. ² ² A page hit (i.e., a code fetch to the same 256-byte ‘‘page’’ as the previous code fetch) requires one state (2TOSC); a page miss requires two states (4TOSC). ² ² ² During a sequence of page hits, PSENÝ remains low until the end of the last page-hit cycle. Figure 11. External Instruction Bus Cycle in Page Mode 24 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER AC CharacteristicsÐSerial Port, Shift Register Mode Table 10. Serial Port Timing Shift Register Mode Symbol Parameter Min Max Units TXLXL Serial Port Clock Cycle Time 12TOSC ns TQVSH Output Data Setup to Clock Rising Edge 10TOSC b 133 ns TXHQX Output Data Hold after Clock Rising Edge 2TOSC b 117 ns TXHDX Input Data Hold after Clock Rising Edge 0 ns TXHDV Clock Rising Edge to Input Data Valid 10TOSC b 133 ns 272814 – 12 ² TI and RI are set during S1P1 of the peripheral cycle following the shift of the eighth bit. Figure 12. Serial Port Waveform ÐShift Register Mode 25 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER External Clock Drive Table 11. External Clock Drive Symbol Parameter 1/TCLCL Oscillator Frequency (FOSC) Min Max Units 16 MHz TCHCX High Time 20 ns TCLCX Low Time 20 ns TCLCH Rise Time 10 ns TCHCL Fall Time 10 ns 272814 – 13 Figure 13. External Clock Drive Waveforms 272814 – 14 AC inputs during testing are driven at VCC b 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at a min of VIH for logic 1 and VOL for a logic 0. Figure 14. AC Testing Input, Output Waveforms 26 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 272814 – 15 For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH/VOL level occurs with IOL/IOH e g 20 mA. Figure 15. Float Waveforms 272814 – 16 Figure 16. Setup for Programming and Verifying Nonvolatile Memory 27 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER PROGRAMMING AND VERIFYING NONVOLATILE MEMORY The 87C151SA/SB has several areas of nonvolatile memory that can be programmed and/or verified: on-chip code memory (8/16 Kbytes), lock bits (3 bits), encryption array (128 bytes), and signature bytes (3 bytes). Figure 16 shows the setup for programming and/or verifying the nonvolatile memory. Table 11 lists the programming and verification operations and indicates which operations apply to the different versions of the 87C151SA/SB. It also specifies the signals on the programming input (PROGÝ) and the ports. The ROM/OTPROM mode (port 0) specifies the operation (program or verify) and the base address of the memory area. The addresses (ports 1 and 3) are relative to the base address. (On-chip memory for a 16-Kbyte ROM/OTPROM device is located at address range 0000H–3FFFH. The other areas of the ROM/OTPROM are outside the memory address space and are accessible only during programming and verification.) 28 Information in Figures 17 and 18 define the configuration bits. Figure 19 shows the waveforms for the programming and verification cycles, and Table 12 lists the timing specifications. The signature bytes of the 83C151SA/SB ROM versions and the 87C151SA/SB OTPROM versions are factory programmed. Table 13 lists the addresses and the contents of the signature bytes. Factory-programmed ROM and OTPROM versions of 8XC151SA/SB use configuration byte information supplied in a separate hexadecimal disk file. 8XC151SA/SB devices without internal ROM/OTPROM arrays fetch configuration byte information from external application memory based on an internal address range of FFF9:8H. NOTE: The VPP source in Figure 16 must be well regulated and free of glitches. The voltage on the VPP pin must not exceed the specified maximum, even under transient conditions. 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 12. Programming and Verification Modes Mode Mode 8XC151SA/SB Xe7 Program On-Chip Code Memory Y Verify On-Chip Code Memory Y Addresses P1 (high), P3 (low) PROGÝ P0 P2 5 Pulses 68H Data 0000H – 3FFFH (16K) 0000H – 1FFFH (8K) High 28H Data 0000H – 3FFFH (16K) 0000H – 1FFFH (8K) Notes Xe3 Y 1 Program Configuration Bytes 2 Verify Configuration Bytes 2 Program Lock Bits Y Verify Lock Bits Y Program Encryption Array Y Verify Signature Bytes Y Y Y 25 Pulses 6BH XX High 2BH Data 0000H 0001H – 0003H 1, 3 4 25 Pulses 6CH Data 0000H – 007FH 1 High 29H Data 0030H, 0031H, 0060H NOTES: 1. The PROGÝ pulse waveform is shown in Figure 19. 2. Factory-programmed ROM and OTPROM versions of 8XC151SA/SB use configuration byte information supplied in a separate hexadecimal disk file. 8XC151SA/SB devices without internal ROM/OTPROM arrays fetch configuration byte information from external application memory based on an internal address range of FFF9:8H. 3. When programming the lock bits, the data bits on port 2 are don’t care. Identify the lock bits with the address as follows: LB3 - 0003H, LB2 - 0002H, LB1 - 0001H. 4. The three lock bits are verified in a single operation. The states of the lock bits appear simultaneously at port 2 as follows: LB3 - P2.3, LB2 - P2.2. LB1 - P2.1. High e programmed. 29 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Address FFF8H 0 UCONFIG0 7 Ð Bit Number WSA1Ý WSA0Ý Bit Mnemonic XALEÝ Ð Ð PAGEÝ Ð Function 7 Ð 6:5 WSA1Ý WSA0Ý (see Note) Reserved 4 XALEÝ Extend Ale: If this bit is set, the time of the ALE pulse is TOSC. Clearing this bit extends the time of the ALE pulse from TOSC to 3TOSC, which adds one external wait state. 1 PAGEÝ Page Mode Select: Clear this bit for page-mode (A15:8/D7:0 on P2, and A7:0 on P0). Set this bit for nonpage-mode (A15:8 on P2, and A7:0/D7:0 on P0 (compatible with MCS 51 microcontrollers)). Wait State Select for external code WSA1Ý WSA0Ý Description 1 1 No wait states 1 0 Insert 1 wait state 0 1 Insert 2 wait states 0 0 Insert 3 wait states NOTE: Factory-programmed ROM and OTPROM versions of 8XC151SA/SB use configuration byte information supplied in a separate hexadecimal disk file. 8XC151SA/SB devices without internal ROM/OTPROM arrays fetch configuration byte information from external application memory based on an internal address range of FFF9:8H. Figure 17. Configuration Byte 0 30 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Address FFF9H 0 UCONFIG1 7 Ð Ð Ð Bit Number Bit Mnemonic 7:5 Ð 2:1 WSB1Ý, WSB0Ý Ð Ð WSB1Ý WSB0Ý Ð Function Reserved; set these bits when writing to UCONFIG1. Wait States for external data WSB1Ý WSB0Ý Description 1 1 0 0 1 0 1 0 No wait states Insert 1 wait state Insert 2 wait states Insert 3 wait states NOTE: Factory-programmed ROM and OTPROM versions of 8XC151SA/SB use configuration byte information supplied in a separate hexadecimal disk file. 8XC151SA/SB devices without internal ROM/OTPROM arrays fetch configuration byte information from external application memory based on an internal address range of FFF9:8H. Figure 18. Configuration Byte 1 31 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER 272814 – 17 Figure 19. Timing for Programming and Verification of Nonvolatile Memory 32 8XC151SA/SB HIGH-PERFORMANCE CHMOS MICROCONTROLLER Table 13. Nonvolatile Memory Programming and Verification Characteristics at TA e 21 b 27§ C, VCC e 5V, and VSS e 0V Symbol Definition Min Max Units 12.5 13.5 D.C. Volts 75 mA 4.0 6.0 MHz VPP Programming Supply Voltage IPP Programming Supply Current FOSC Oscillator Frequency TAVGL Address Setup to PROGÝ Low 48TOSC TGHAX Address Hold after PROGÝ 48TOSC TDVGL Data Setup to PROGÝ Low 48TOSC TGHDX Data Hold after PROGÝ 48TOSC TEHSH ENABLE High to VPP 48TOSC TSHGL VPP Setup to PROGÝ Low TGHSL VPP Hold after PROGÝ 10 TGLGH PROGÝ Width 90 TAVQV Address to Data Valid 48TOSC TELQV ENABLE Low to Data Valid 48ToSC TEHQZ Data Float after ENABLE 0 TGHGL PROGÝ High to PROGÝ Low 10 10 ms ms 110 ms 48TOSC ms NOTE: Notation for timing parameters: A e Address Q e Data out D e Data S e Supply (VPP) E e Enable V e Valid G e PROGÝ X e No Longer Valid H e High Z e Floating L e Low Table 14. Contents of the Signature Bytes ADDRESS CONTENTS DEVICE TYPE 30H 89H Indicates Intel Devices 31H 48H Indicates MCS 151 core product 60H 7BH Indicates 83C151SB device 60H FBH Indicates 87C151SB device 60H 7AH Indicates 83C151SA device 60H FAH Indicates 87C151SA device 33