ISSI IS62C1024-70T

ISSI
®
IS62C1024
128K x 8 HIGH-SPEED CMOS STATIC RAM
FEATURES
• High-speed access time: 35, 45, 55, 70 ns
• Low active power: 450 mW (typical)
• Low standby power: 500 µW (typical) CMOS
standby
• Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 5V (±10%) power supply
JANUARY 2000
DESCRIPTION
The ISSI IS62C1024 is a low power,131,072-word by
8-bit CMOS static RAM. It is fabricated using ISSI's
high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design techniques,
yields higher performance and low power consumption
devices.
When CE1 is HIGH or CE2 is LOW (deselected), the
device assumes a standby mode at which the power
dissipation can be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip
Enable inputs, CE1 and CE2. The active LOW Write
Enable (WE) controls both writing and reading of the
memory.
The IS62C1024 is available in 32-pin 525-mil plastic SOP
and TSOP (type 1) packages.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
512 X 2048
MEMORY ARRAY
I/O
DATA
CIRCUIT
COLUMN I/O
VCC
GND
I/O0-I/O7
CE1
CE2
OE
WE
CONTROL
CIRCUIT
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
01/14/00
1
ISSI
IS62C1024
®
PIN CONFIGURATION
32-Pin SOP
32-Pin TSOP (Type 1)
NC
1
32
VCC
A16
2
31
A15
A14
3
30
CE2
A12
4
29
WE
A7
5
28
A13
A6
6
A5
7
62C1024 27
26
A4
8
25
A11
A3
9
24
OE
A2
10
23
A10
A1
11
22
CE1
ISSI
A8
A9
A0
12
21
I/O7
I/O0
13
20
I/O6
I/O1
14
19
I/O5
I/O2
15
18
I/O4
GND
16
17
I/O3
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
PIN DESCRIPTIONS
A0-A16
Address Inputs
CE1
Chip Enable 1 Input
CE2
Chip Enable 2 Input
OE
Output Enable Input
WE
Write Enable Input
I/O0-I/O7
Input/Output
Vcc
Power
GND
Ground
OPERATING RANGE
Range
Commercial
Industrial
2
Ambient Temperature
0°C to +70°C
VCC
5V ± 10%
–40°C to +85°C
5V ± 10%
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
01/14/00
ISSI
IS62C1024
®
TRUTH TABLE
Mode
Not Selected
(Power-down)
Output Disabled
Read
Write
WE
CE1
CE2
OE
X
X
H
H
L
H
X
L
L
L
X
L
H
H
H
X
X
H
L
X
I/O Operation
High-Z
High-Z
High-Z
DOUT
DIN
Vcc Current
ISB1, ISB2
ISB1, ISB2
I CC
I CC
I CC
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TBIAS
TSTG
PT
IOUT
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current (LOW)
Value
–0.5 to +7.0
–10 to +85
–65 to +150
1.5
20
Unit
V
°C
°C
W
mA
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
CAPACITANCE(1,2)
Symbol
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
Max.
Unit
VIN = 0V
6
pF
VOUT = 0V
8
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
VOH
VOL
VIH
VIL
ILI
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage(1)
Input Leakage
VCC = Min., IOH = –1.0 mA
VCC = Min., IOL = 2.1 mA
Output Leakage
GND ≤ VOUT ≤ VCC
—
0.4
VCC + 0.5
0.8
5
10
5
10
V
V
V
V
µA
ILO
2.4
—
2.2
–0.3
–5
–10
–5
–10
GND ≤ VIN ≤ VCC
Com.
Ind.
Com.
Ind.
µA
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
01/14/00
3
ISSI
IS62C1024
®
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
-35
Min. Max.
Test Conditions
-45
Min. Max.
-55
Min. Max.
-70
Min. Max.
Unit
ICC
Vcc Dynamic Operating
Supply Current
VCC = Max., CE = VIL
IOUT = 0 mA, f = fMAX
Com.
Ind.
—
—
150
160
—
—
135
145
—
—
120
130
—
—
90
100
mA
ISB1
TTL Standby Current
(TTL Inputs)
VCC = Max.,
Com.
VIN = VIH or VIL, CE1 ≥ VIH, Ind.
or CE2 ≤ VIL, f = 0
—
—
40
60
—
—
40
60
—
—
40
60
—
—
40
60
mA
ISB2
CMOS Standby
Current (CMOS Inputs)
VCC = Max.,
Com.
CE1 ≤ VCC – 0.2V,
Ind.
CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V,
or VIN ≤ 0.2V, f = 0
—
—
30
40
—
—
30
40
—
—
30
40
—
—
30
40
mA
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Level
Output Load
Unit
0V to 3.0V
5 ns
1.5V
See Figures 1a and 1b
AC TEST LOADS
480 Ω
5V
5V
OUTPUT
OUTPUT
100 pF
Including
jig and
scope
Figure 1a.
4
480 Ω
255 Ω
5 pF
Including
jig and
scope
255 Ω
Figure 1b.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
01/14/00
ISSI
IS62C1024
®
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol
Parameter
-35
Min.
Max.
-45
Min.
Max.
-55
Min.
Max.
-70
Min.
Max.
Unit
tRC
Read Cycle Time
35
—
45
—
55
—
70
—
ns
tAA
Address Access Time
—
35
—
45
—
55
—
70
ns
tOHA
Output Hold Time
3
—
3
—
3
—
3
—
ns
tACE1
CE1 Access Time
—
35
—
45
—
55
—
70
ns
tACE2
CE2 Access Time
—
35
—
45
—
55
—
70
ns
tDOE
OE Access Time
—
10
—
20
—
25
—
35
ns
OE to Low-Z Output
0
—
0
—
0
—
0
—
ns
tHZOE
OE to High-Z Output
0
10
0
15
0
20
0
25
ns
tLZCE1(2)
CE1 to Low-Z Output
3
—
5
—
7
—
10
—
ns
tLZCE2(2)
CE2 to Low-Z Output
3
—
5
—
7
—
10
—
ns
tHZCE
CE1 or CE2 to High-Z Output
0
10
0
15
0
20
0
25
ns
tLZOE
(2)
(2)
(2)
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
tRC
ADDRESS
tAA
tOHA
DOUT
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
01/14/00
tOHA
DATA VALID
5
ISSI
IS62C1024
®
READ CYCLE NO. 2(1,3)
tRC
ADDRESS
tAA
tOHA
OE
tHZOE
tDOE
CE1
tLZOE
tACE1/tACE2
CE2
DOUT
tLZCE1/
tLZCE2
tHZCE
HIGH-Z
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1 = VIL, CE2 = VIH.
3. Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions.
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range, Standard and Low Power)
-35
Symbol
Parameter
-45
-55
Min.
Max.
Min.
Max.
Min.
Max.
-70
Min. Max.
Unit
tWC
Write Cycle Time
35
—
45
—
55
—
70
—
ns
tSCE1
CE1 to Write End
25
—
35
—
50
—
60
—
ns
tSCE2
CE2 to Write End
25
—
35
—
50
—
60
—
ns
tAW
Address Setup Time to Write End
25
—
35
—
45
—
60
—
ns
tHA
Address Hold from Write End
0
—
0
—
0
—
0
—
ns
tSA
Address Setup Time
0
—
0
—
0
—
0
—
ns
WE Pulse Width
25
—
35
—
40
—
50
—
ns
Data Setup to Write End
20
—
25
—
25
—
30
—
ns
tPWE
(4)
tSD
tHD
Data Hold from Write End
0
—
0
—
0
—
0
—
ns
(2)
tHZWE
WE LOW to High-Z Output
—
10
—
15
—
20
—
25
ns
(2)
tLZWE
WE HIGH to Low-Z Output
3
—
5
—
5
—
5
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
4. Tested with OE HIGH.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
01/14/00
ISSI
IS62C1024
®
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)(1,2)
tWC
ADDRESS
tHA
tSCE1
CE1
tSCE2
CE2
tAW
tPWE(4)
WE
tSA
DOUT
tHZWE
tLZWE
HIGH-Z
DATA UNDEFINED
tSD
DIN
tHD
DATA-IN VALID
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)(1,2)
tWC
ADDRESS
tSA
tHA
tSCE1
CE1
tSCE2
CE2
tAW
tPWE(4)
WE
tHZWE
DOUT
DATA UNDEFINED
tLZWE
HIGH-Z
tSD
DIN
tHD
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
01/14/00
7
ISSI
IS62C1024
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns)
Order Part No.
Package
35
35
IS62C1024-35Q
IS62C1024-35T
525-mil Plastic SOP
TSOP, Type 1
45
45
IS62C1024-45Q
IS62C1024-45T
525-mil Plastic SOP
TSOP, Type 1
55
55
IS62C1024-55Q
IS62C1024-55T
525-mil Plastic SOP
TSOP, Type 1
70
70
IS62C1024-70Q
IS62C1024-70T
525-mil Plastic SOP
TSOP, Type 1
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
35
35
IS62C1024-35QI
IS62C1024-35TI
525-mil Plastic SOP
TSOP, Type 1
45
45
IS62C1024-45QI
IS62C1024-45TI
525-mil Plastic SOP
TSOP, Type 1
55
55
IS62C1024-55QI
IS62C1024-55TI
525-mil Plastic SOP
TSOP, Type 1
70
70
IS62C1024-70QI
IS62C1024-70TI
525-mil Plastic SOP
TSOP, Type 1
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: [email protected]
www.issi.com
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. G
01/14/00