TI CD74HC4015ME4

[ /Title
(CD74
HC401
5)
/Subject
(High
Speed
CMOS
Logic
Dual
4-
CD54HC4015, CD74HC4015
Data sheet acquired from Harris Semiconductor
SCHS198C
High Speed CMOS Logic
Dual 4-Stage Static Shift Register
November 1997 - Revised May 2003
Features
Description
• Maximum Frequency, Typically 60MHz
CL = 15pF, VCC = 5V, TA = 25oC
The ’HC4015 consists of two identical, independent, 4-stage
serial-input/parallel-output registers. Each register has
independent Clock (CP) and Reset (MR) inputs as well as a
single serial Data input. “Q” outputs are available from each
of the four stages on both registers. All register stages are Dtype, master-slave flip-flops. The logic level present at the
Data input is transferred into the first register stage and
shifted over one stage at each positive- going clock
transition. Resetting of all stages is accomplished by a high
level on the reset line.
• Positive-Edge Clocking
• Overriding Reset
• Buffered Inputs and Outputs
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
The device can drive up to 10 low power Schottky equivalent
loads. The ’HC4015 is an enhanced version of equivalent
CMOS types.
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
Ordering Information
• Significant Power Reduction Compared to LSTTL
Logic ICs
TEMP. RANGE (oC)
PACKAGE
CD54HC4015F3A
-55 to 125
16 Ld CERDIP
CD74HC4015E
-55 to 125
16 Ld PDIP
CD74HC4015M
-55 to 125
16 Ld SOIC
PART NUMBER
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
Pinout
CD54HC4015
(CERDIP)
CD74HC4015
(PDIP, SOIC)
TOP VIEW
2CP 1
16 VCC
2Q3 2
15 2D
1Q2 3
14 2MR
1Q1 4
13 2Q0
1Q0 5
12 2Q1
1MR 6
11 2Q2
1D 7
10 1Q3
GND 8
9 1CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
1
CD54HC4015, CD74HC4015
Functional Diagram
5
7
1D
4
9
3
1CP
10
6
1MR
1Q0
1Q1
1Q2
1Q3
13
15
2D
12
1
11
2CP
2
14
2MR
2Q0
2Q1
2Q2
2Q3
GND = 8
VCC = 16
TRUTH TABLE
INPUTS
CP
OUTPUTS
D
R
Q0
Q1
Q2
Q3
↑
l
↑
h
L
L
q’0
q’1
q’2
L
H
q’0
q’1
q’2
↓
X
L
q’0
q’1
q’2
q’3
X
X
H
L
L
L
L
H = High Voltage Level
h = High Voltage Level One Set-up Time Prior to the Low to High Clock Transition
L = Low Voltage Level
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition
X = Don’t Care.
↑ = Low to High Clock Transition
↓ = High to Low Clock Transition
q’n = Lower case letters indicate the state of the referenced output one set-up time prior to the Low to
High clock transition.
2
CD54HC4015, CD74HC4015
t6
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
67
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
73
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
f
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
High Level Input
Voltage
VI (V)
IO (mA)
VIH
-
-
2
1.5
-
-
1.5
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
VIL
High Level Output
Voltage
CMOS Loads
VOH
-
VIH or VIL
High Level Output
Voltage
TTL Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
-40oC TO 85oC -55oC TO 125oC
SYMBOL
Low Level Input
Voltage
Low Level Output
Voltage
CMOS Loads
25oC
VCC
(V)
-
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
-
1.5
-
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-
-
-
-
-
-
-
-
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
-
-
-
-
-
-
-
-
-
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
II
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
-
8
-
80
-
160
µA
3
CD54HC4015, CD74HC4015
Prerequisite for Switching Specifications
25oC
PARAMETER
Maximum Clock
Frequency
Clock Pulse Width
MR Pulse Width
MR Recovery Time
-40oC TO 85oC
-55oC TO 125oC
SYMBOL
VCC (V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
fMAX
2
6
-
5
-
4
-
MHz
4.5
30
-
24
-
20
-
MHz
6
35
-
28
-
24
-
MHz
2
80
-
100
-
120
-
ns
4.5
16
-
20
-
24
-
ns
6
14
-
17
-
20
-
ns
tW
tW
2
150
-
190
-
225
-
ns
4.5
30
-
38
-
45
-
ns
6
26
-
33
-
38
-
ns
tREC
Set-up Time,
Data-In to CP
tSUL, tSUH
Hold Time,
Data-In to CP
tH
2
50
-
65
-
75
-
ns
4.5
10
-
13
-
15
-
ns
6
9
-
11
-
13
-
ns
2
60
-
75
-
90
-
ns
4.5
12
-
15
-
18
-
ns
6
10
-
13
-
15
-
ns
2
0
-
0
-
0
-
ns
4.5
0
-
0
-
0
-
ns
6
0
-
0
-
0
-
ns
Switching Specifications Input tr, tf = 6ns
PARAMETER
Propagation Delay (Figure 1)
Clock to Qn
MR to Qn, (Clock High)
TEST
SYMBOL CONDITIONS
tPLH,
tPHL
tPLH,
tPHL
CL = 50pF
25oC
tPLH,
tPHL
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
-
-
175
-
220
-
270
ns
4.5
-
-
35
-
44
-
54
ns
CL =15pF
5
-
14
-
-
-
-
-
ns
CL = 50pF
6
-
-
30
-
37
-
46
ns
CL = 50pF
2
-
-
275
-
345
-
415
ns
4.5
-
-
55
-
64
-
83
ns
25
-
-
-
-
-
ns
CL = 50pF
6
-
-
47
-
54
-
71
ns
CL = 50pF
2
-
-
325
-
400
-
490
ns
4.5
-
CL =15pF
CL = 50pF
Output Transition Time
(Figure 1)
-55oC TO 125oC
2
CL =15pF
MR to Qn, (Clock Low)
-40oC TO 85oC
VCC
(V)
tTLH, tTHL CL = 50pF
6
-
-
65
-
81
-
98
ns
25
-
-
-
-
-
ns
-
55
-
69
-
83
ns
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
CIN
CL = 50pF
-
-
-
10
-
10
-
10
pF
Maximum Clock Frequency
fMAX
CL =15pF
5
-
60
-
-
-
-
-
MHz
Power Dissipation
Capacitance
(Notes 2, 3)
CPD
CL =15pF
5
-
43
-
-
-
-
-
pF
Input Capacitance
NOTES:
2. CPD is used to determine the dynamic power consumption, per shift register.
3. PD = VCC2 fi + ∑ CL VCC2 where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
4
CD54HC4015, CD74HC4015
Test Circuit and Waveform
tfCL
trCL
CLOCK
INPUT
VCC
90%
50%
10%
GND
tH(H)
tH(L)
VCC
DATA
INPUT
50%
GND
tSU(H)
tSU(L)
tTLH
90%
tTHL
90%
50%
10%
tPLH
tPHL
OUTPUT
tREM
VCC
SET, RESET
OR PRESET
50%
GND
IC
CL
50pF
FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED
SEQUENTIAL LOGIC CIRCUITS
5
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
5962-8995301EA
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
N / A for Pkg Type
CD54HC4015F3A
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
N / A for Pkg Type
CD74HC4015E
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HC4015EE4
ACTIVE
PDIP
N
16
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HC4015M
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4015ME4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HC4015MG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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