TI CD74HCU04M

[ /Title
(CD74
HCU04
)
/Subject
(High
Speed
CMOS
Logic
Hex
Inverter
CD74HCU04
Data sheet acquired from Harris Semiconductor
SCHS127D
High-Speed CMOS Logic
Hex Inverter
February 1998 - Revised May 2004
Features
Description
• Typical Propagation Delay: 6ns at VCC = 5V,
CL = 15pF, TA = 25oC, Fastest Part in QMOS Line
The CD74HCU04 unbuffered hex inverter utilizes silicon-gate
CMOS technology to achieve operation speeds similar to
LSTTL gates, with the low power consumption of standard
CMOS integrated circuits. These devices especially are useful
in crystal oscillator and analog applications.
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
Ordering Information
• HCU Types
- 2-V to 6-V Operation
- High Noise Immunity: NIL = 20%, NIH = 30% of
VCC at VCC = 5V
PART NUMBER
• CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
TEMP. RANGE
(oC)
PACKAGE
CD74HCU04E
-55 to 125
14 Ld PDIP
CD74HCU04M
-55 to 125
14 Ld SOIC
CD74HCU04MT
-55 to 125
14 Ld SOIC
CD74HCU04M96
-55 to 125
14 Ld SOIC
CD74HCU04PWR
-55 to 125
14 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffixes
96 and R denote tape and reel. The suffix T denotes a smallquantity reel of 250.
Pinout
CD74HCU04
(PDIP, SOIC, TSSOP)
TOP VIEW
1A 1
14 VCC
1Y 2
13 6A
2A 3
12 6Y
2Y 4
11 5A
3A 5
10 5Y
3Y 6
9 4A
GND 7
8 4Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2004, Texas Instruments Incorporated
1
CD74HCU04
Functional Diagram
1A
1Y
2A
2Y
3A
3Y
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
6A
6Y
5A
5Y
4A
4Y
Logic Symbol
nA
nY
Schematic Diagram
VCC
(3, 5, 9, 11, 13) 1
2 (4, 6, 8, 10, 12)
2
CD74HCU04
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC
Voltages Referenced to Ground . . . . . . . . . . . . . . . . -0.5V to +7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
M (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range TA . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating, and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
SYMBOL
VI (V)
VIH
-
VIL
Quiescent Device
Current
MAX
MIN
MAX
MIN
MAX
UNITS
2
1.7
-
1.7
-
1.7
-
V
4.5
3.6
-
3.6
-
3.6
-
V
6
4.8
-
4.8
-
4.8
-
V
-
0.3
-
0.3
-
0.3
V
0.8
-
0.8
-
0.8
V
6
-
1.1
-
1.1
-
1.1
V
-0.02
2
1.8
-
1.8
-
1.8
-
V
-0.02
4.5
4
-
4
-
4
-
V
-0.02
6
5.5
-
5.5
-
5.5
-
V
-4
4.5
3.98
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
5.34
-
5.2
-
V
0.02
2
-
0.2
-
0.2
-
0.2
V
0.02
4.5
-
0.5
-
0.5
-
0.5
V
0.02
6
-
0.5
-
0.5
-
0.5
V
4
4.5
-
0.26
-
0.33
-
0.4
V
VCC or
GND
5.2
6
-
0.26
-
0.33
-
0.4
V
II
VCC or
GND
-
6
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
2
-
20
-
40
µA
VIH or
VIL
VCC or
GND
VOL
VIH or
VIL
-
MIN
-
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
-
-55oC TO 125oC
2
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
IO (mA) VCC (V)
-40oC TO +85oC
4.5
VOH
-
25oC
3
CD74HCU04
Switching Specifications Input tr, tf = 6ns
PARAMETER
Propagation Delay,
Input to Output Y (Figure 1)
Transition Times (Figure 1)
Input Capacitance
Power Dissipation Capacitance
(Notes 2, 3)
25oC
-40oC TO 85oC -55oC TO 125oC
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
2
-
-
70
-
90
-
105
ns
CL = 50pF
4.5
-
-
14
-
18
-
21
ns
CL = 15pF
5
-
5
-
-
-
-
-
ns
CL = 50pF
6
-
-
12
-
15
-
18
ns
CL = 50pF
2
-
-
75
-
95
18
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
tTLH, tTHL
CI
-
CPD
-
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
See Figure 3
5
-
14
-
-
pF
-
-
-
NOTES:
2. CPD is used to determine the dynamic power consumption, per inverter.
3. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
Test Circuits and Waveforms
tr = 6ns
tf = 6ns
VCC
90%
50%
10%
INPUT
GND
tTHL
tTLH
90%
50%
10%
INVERTING
OUTPUT
tPLH
tPHL
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
ICC, VCC TO GND CURRENT (mA)
Typical Performance Curves
AMBIENT TEMPERATURE
TA = 25o C
25.0
22.5
VCC = 6V
20.0
17.5
15.0
VCC = 4.5V
12.5
10.0
7.5
5.0
VCC = 2V
2.5
0
1
2
3
4
5
VI, INPUT VOLTAGE (V)
6
FIGURE 2. TYPICAL INVERTER SUPPLY CURRENT AS FUNCTION OF INPUT VOLTAGE
4
pF
CD74HCU04
CI, INPUT CAPACITANCE (pF)
Typical Performance Curves
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
(Continued)
AMBIENT TEMPERATURE, TA = 25oC
VDD = 2V, VI 0-2V
INPUT PIN 5 CONDITIONS
VDD = 3V, VI 0-3V
VDD = 4V, VI 0-4V
VDD = 5V, VI 0-5V
VDD = 6V, VI 0-6V
1
2
3
VIN, INPUT VOLTAGE (V)
4
FIGURE 3. INPUT CAPACITANCE AS A FUNCTION OF INPUT VOLTAGE
5
5
6
PACKAGE OPTION ADDENDUM
www.ti.com
24-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CD74HCU04E
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HCU04EE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
CD74HCU04M
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCU04M96
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCU04M96E4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCU04M96G4
ACTIVE
SOIC
D
14
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCU04ME4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCU04MG4
ACTIVE
SOIC
D
14
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCU04MT
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCU04MTE4
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCU04MTG4
ACTIVE
SOIC
D
14
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCU04PWR
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCU04PWRE4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
CD74HCU04PWRG4
ACTIVE
TSSOP
PW
14
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-May-2007
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CD74HCU04M96
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
CD74HCU04PWR
TSSOP
PW
14
2000
330.0
12.4
7.0
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CD74HCU04M96
SOIC
D
14
2500
346.0
346.0
33.0
CD74HCU04PWR
TSSOP
PW
14
2000
346.0
346.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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• DALLAS, TEXAS 75265
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