SN74CBT3384A 10-BIT FET BUS SWITCH SCDS004L − NOVEMBER 1992 − REVISED JANUARY 2004 D 5-Ω Switch Connection Between Two Ports D TTL-Compatible Input Levels DB, DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW) 1OE 1B1 1A1 1A2 1B2 1B3 1A3 1A4 1B4 1B5 1A5 GND description/ordering information The SN74CBT3384A provides ten bits of high-speed TTL-compatible bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The device is organized as two 5-bit switches with separate output-enable (OE) inputs. When OE is low, the switch is on, and port A is connected to port B. When OE is high, the switch is open, and the high-impedance state exists between the two ports. 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 2B5 2A5 2A4 2B4 2B3 2A3 2A2 2B2 2B1 2A1 2OE ORDERING INFORMATION SN74CBT3384ADW Tape and reel SN74CBT3384ADWR SSOP − DB Tape and reel SN74CBT3384ADBR CU384A SSOP (QSOP) − DBQ Tape and reel SN74CBT3384ADBQR CBT3384A Tube SN74CBT3384APW Tape and reel SN74CBT3384APWR Tape and reel SN74CBT3384ADGVR TSSOP − PW TVSOP − DGV † TOP-SIDE MARKING Tube SOIC − DW −40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA CBT3384A CU384A CU384A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each 5-bit bus switch) INPUTS INPUTS/OUTPUTS 1OE 2OE 1B1−1B5 2B1−2B5 L L 1A1−1A5 2A1−2A5 L H 1A1−1A5 Z H L Z 2A1−2A5 H H Z Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright © 2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74CBT3384A 10-BIT FET BUS SWITCH SCDS004L − NOVEMBER 1992 − REVISED JANUARY 2004 logic diagram (positive logic) 1A1 1A5 1OE 2A1 2A5 2OE 3 2 11 10 1B1 1B5 1 14 15 22 23 2B1 2B5 13 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Continuous channel current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI/O < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W DBQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) MIN MAX VCC Supply voltage 4 5.5 VIH High-level control input voltage 2 VIL Low-level control input voltage TA Operating free-air temperature −40 UNIT V V 0.8 V 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74CBT3384A 10-BIT FET BUS SWITCH SCDS004L − NOVEMBER 1992 − REVISED JANUARY 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VIK VCC = 4.5 V, II = −18 mA II VCC = 5.5 V, VI = 5.5 V or GND ICC VCC = 5.5 V, IO = 0, VI = VCC or GND One input at 3.4 V, Other inputs at VCC or GND ΔICC‡ Control inputs VCC = 5.5 V, Ci Control inputs VI = 3 V or 0 Cio(OFF) VO = 3 V or 0, OE = VCC VCC = 4 V, TYP at VCC = 4 V VI = 2.4 V, ron§ VI = 0 VCC = 4.5 V VI = 2.4 V, TYP† MAX UNIT −1.2 V ±1 μA 3 μA 2.5 mA 4 pF 4.5 pF II = 15 mA 14 20 II = 64 mA 5 7 II = 30 mA 5 7 II = 15 mA 10 15 Ω † All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. § Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lowest voltage of the two (A or B) terminals. ‡ switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) ¶ VCC = 4 V VCC = 5 V ± 0.5 V MIN MIN FROM (INPUT) TO (OUTPUT) tpd¶ A or B B or A 0.35 ten OE A or B 6.2 tdis OE A or B 5.5 PARAMETER MAX UNIT MAX 0.25 ns 1.9 5.7 ns 2.1 5.2 ns The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74CBT3384A 10-BIT FET BUS SWITCH SCDS004L − NOVEMBER 1992 − REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION 7V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 7V Open 3V Output Control LOAD CIRCUIT 1.5 V 1.5 V 0V tPZL 3V Input 1.5 V 1.5 V 0V tPLH 1.5 V 3.5 V 1.5 V 1.5 V VOL Output Waveform 2 S1 at Open (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOL + 0.3 V VOL tPZH tPHL VOH Output Output Waveform 1 S1 at 7 V (see Note B) tPLZ tPHZ 1.5 V VOH VOH − 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 28-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TBD Lead/Ball Finish SN74CBT3384ADBLE OBSOLETE SSOP DB 24 SN74CBT3384ADBQR ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74CBT3384ADBQRE4 ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74CBT3384ADBQRG4 ACTIVE SSOP/ QSOP DBQ 24 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74CBT3384ADBR ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3384ADBRE4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3384ADBRG4 ACTIVE SSOP DB 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3384ADGVR ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3384ADGVRE4 ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3384ADGVRG4 ACTIVE TVSOP DGV 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3384ADW ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3384ADWE4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3384ADWG4 ACTIVE SOIC DW 24 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3384ADWR ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3384ADWRE4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3384ADWRG4 ACTIVE SOIC DW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3384APW ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3384APWE4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3384APWG4 ACTIVE TSSOP PW 24 60 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3384APWLE OBSOLETE TSSOP PW 24 SN74CBT3384APWR ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3384APWRE4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3384APWRG4 ACTIVE TSSOP PW 24 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TBD (1) Call TI MSL Peak Temp (3) Call TI Call TI Call TI The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 28-May-2007 PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74CBT3384ADBQR Package Package Pins Type Drawing SSOP/ QSOP SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DBQ 24 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74CBT3384ADBR SSOP DB 24 2000 330.0 16.4 8.2 8.8 2.5 12.0 16.0 Q1 SN74CBT3384ADGVR TVSOP DGV 24 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 SN74CBT3384ADWR SOIC DW 24 2000 330.0 24.4 10.75 15.7 2.7 12.0 24.0 Q1 SN74CBT3384APWR TSSOP PW 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74CBT3384ADBQR SSOP/QSOP DBQ 24 2500 346.0 346.0 33.0 SN74CBT3384ADBR SSOP DB 24 2000 346.0 346.0 33.0 SN74CBT3384ADGVR TVSOP DGV 24 2000 346.0 346.0 29.0 SN74CBT3384ADWR SOIC DW 24 2000 346.0 346.0 41.0 SN74CBT3384APWR TSSOP PW 24 2000 346.0 346.0 33.0 Pack Materials-Page 2 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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