SN54ABT823, SN74ABT823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS158E – JANUARY 1991 – REVISED MAY 1997 D D D D D D SN54ABT823 . . . JT OR W PACKAGE SN74ABT823 . . . DB, DW, OR NT PACKAGE (TOP VIEW) OE 1D 2D 3D 4D 5D 6D 7D 8D 9D CLR GND These 9-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers. With the clock-enable (CLKEN) input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the clock buffer, thus latching the outputs. Taking the clear (CLR) input low causes the nine Q outputs to go low, independently of the clock. 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q CLKEN CLK SN54ABT823 . . . FK PACKAGE (TOP VIEW) 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 4 description 1 2D 1D OE NC VCC 1Q 2Q D State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Impedance State During Power Up and Power Down High-Drive Outputs (–32-mA IOH, 64-mA IOL) Buffered Control Inputs to Reduce dc Loading Effects Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK) and Flatpacks (W), and Standard Plastic (NT) and Ceramic (JT) DIPs 3D 4D 5D NC 6D 7D 8D 10 20 11 19 12 13 14 15 16 17 18 3Q 4Q 5Q NC 6Q 7Q 8Q 9D CLR GND NC CLK CLKEN 9Q D NC – No internal connection A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup components. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54ABT823 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT823 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT823, SN74ABT823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS158E – JANUARY 1991 – REVISED MAY 1997 FUNCTION TABLE (each flip-flop) INPUTS OE D OUTPUT Q CLR CLKEN CLK L L X X X L L H L ↑ H H L H L ↑ L L L H H X X Q0 H X X X X Z logic symbol† OE CLR CLKEN CLK 1D 2D 3D 4D 5D 6D 7D 8D 9D 1 11 14 13 2 EN R G1 1C2 23 2D 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, and W packages. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q 9Q SN54ABT823, SN74ABT823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS158E – JANUARY 1991 – REVISED MAY 1997 logic diagram (positive logic) OE CLR CLKEN CLK 1 11 14 R 13 C1 1D 2 23 1Q 1D To Eight Other Channels Pin numbers shown are for the DB, DW, JT, NT, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT823 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT823 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the “recommended operating conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT823, SN74ABT823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS158E – JANUARY 1991 – REVISED MAY 1997 recommended operating conditions (see Note 3) SN54ABT823 SN74ABT823 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC –24 Low-level output current 48 64 mA ∆t/∆v Input transition rise or fall rate 5 5 ns/V ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 High-level input voltage 2 2 0.8 Input voltage 0 V 0.8 0 VCC –32 –40 V V mA µs/V 200 125 V 85 °C NOTE 3: Unused inputs must be held high or low to prevent them from floating. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOL Vhys II IOZPU‡ IOZPD‡ IOZH IOZL Ioff ICEX IO¶ VCC = 4 4.5 5V SN54ABT823 MIN –1.2 MAX SN74ABT823 MIN –1.2 2.5 2.5 IOH = –3 mA IOH = –24 mA 3 3 3 2 2 IOH = –32 mA IOL = 48 mA 2* 0.55 IOL = 64 mA 0.55 0.55* VCC = 5.5 V, VI = VCC or GND VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE ≥ 2 V VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE ≥ 2 V VCC = 0, VI or VO ≤ 4.5 V 0.55 VCC = 5.5 5 5 V, V IO = 0, 0 VI = VCC or GND ∆ICC# VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND Ci VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V Outputs low Outputs disabled ±1 ±1 ±1 µA ±50 ±50 ±50 µA ±50 10§ –10§ ±50 10§ –10§ ±50 10§ –10§ µA ±100 µA 50 µA –180 mA 50 –50 POST OFFICE BOX 655303 V mV ±100 Outputs high VO = 2.5 V Outputs high V V 100 VCC = 5.5 V, VO = 5.5 V VCC = 5.5 V, UNIT 2 50 –50 –180 –50 µA µA –140 –180 1 250 250 250 µA 24 0.5 38 250 38 250 38 250 mA µA 1.5 1.5 1.5 mA 4 pF 7 pF * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ This parameter is characterized, but not production tested. § This data sheet limit may vary among suppliers. ¶ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. # This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 4 MAX –1.2 2.5 ICC Co TA = 25°C MIN TYP† MAX • DALLAS, TEXAS 75265 SN54ABT823, SN74ABT823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS158E – JANUARY 1991 – REVISED MAY 1997 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C fclock Clock frequency tw Pulse duration tsu th ↑ Setup time before CLK↑ SN74ABT823 MIN MAX MIN MAX MIN MAX 0 125 0 125 0 125 CLR low 5.5 5.5 5.5 CLK high 2.9 2.9 2.9 CLK low 3.8 3.8 3.8 CLR inactive 2.5 2.5 2.5 Data 2.1 2.1 2.1 2 2 2 CLKEN low 3.3 3.3 3.3 Data 1.3 1.3 1.3 CLKEN high 1 1 1 CLKEN low 2 2 2 CLKEN high Hold time after CLK↑ ↑ SN54ABT823 UNIT MHz ns ns ns switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ FROM (INPUT) TO (OUTPUT) CLK Q CLR Q OE Q OE Q VCC = 5 V, TA = 25°C SN54ABT823 MAX MIN MAX SN74ABT823 MIN TYP 125 200 2.1 4.3 5.9 2.1 8.1 2.1 6.8 2.2 4.4 6.1 2.2 7 2.2 6.7 2 4.1 7.3 2 3 6.3 4.7† 2 1 1 6.3 1 7.1 6† 2.2 4.1 2.2 6.6 2.2 2.7 4.8 5.6 6.5† 2.7 7.7 2.7 6.5† 7.5† 1.9 5 6.4 1.9 7.4 1.9 6.9 125 MIN UNIT MAX 125 MHz ns ns ns ns † This data sheet limit may vary among suppliers. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ABT823, SN74ABT823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS158E – JANUARY 1991 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT 3V Timing Input 1.5 V 0V tw tsu 3V Input 1.5 V 1.5 V th 3V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V VOH 1.5 V Output 1.5 V VOL VOH Output 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPLZ Output Waveform 1 S1 at 7 V (see Note B) tPLH tPHL 1.5 V tPZL tPHL tPLH 3V Output Control Output Waveform 2 S1 at Open (see Note B) 1.5 V tPZH 3.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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