TI SN74ABTH16823DL

SN54ABTH16823, SN74ABTH16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS664B – APRIL 1996 – REVISED MAY 1997
D
D
D
D
D
D
D
D
D
D
SN54ABTH16823 . . . WD PACKAGE
SN74ABTH16823 . . . DGG OR DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
State-of-the-Art EPIC-ΙΙB  BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
1CLR
1OE
1Q1
GND
1Q2
1Q3
VCC
1Q4
1Q5
1Q6
GND
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2OE
2CLR
Typical VOLP (Output Ground Bounce) < 1 V
at VCC = 5 V, TA = 25°C
High-Impedance State During Power Up
and Power Down
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
These 18-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1CLK
1CLKEN
1D1
GND
1D2
1D3
VCC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2CLKEN
2CLK
The ’ABTH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN) input
low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the
clock buffer, latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently
of the clock.
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
SN54ABTH16823, SN74ABTH16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS664B – APRIL 1996 – REVISED MAY 1997
description (continued)
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ABTH16823 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABTH16823 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 9-bit flip-flop)
INPUTS
2
OE
CLR
CLKEN
CLK
D
OUTPUT
Q
L
L
X
X
X
L
L
H
L
↑
H
H
L
H
L
↑
L
L
L
H
L
L
X
Q0
L
H
H
X
X
Q0
H
X
X
X
X
Z
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• DALLAS, TEXAS 75265
SN54ABTH16823, SN74ABTH16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS664B – APRIL 1996 – REVISED MAY 1997
logic symbol†
1OE
1CLR
2
1
55
1CLKEN
1CLK
2OE
2CLR
2CLKEN
2CLK
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
56
27
28
30
29
54
EN1
R2
G3
3C4
EN5
R6
G7
7C8
4D
52
1, 2
3
5
51
6
49
8
48
9
47
10
45
12
44
13
43
14
42
8D
41
5, 6
15
16
40
17
38
19
37
20
36
21
34
23
33
24
31
26
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
1Q9
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303
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3
SN54ABTH16823, SN74ABTH16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS664B – APRIL 1996 – REVISED MAY 1997
logic diagram (positive logic)
1OE
1CLR
1CLKEN
2
1
55
CE
R
1CLK
1D1
56
C1
54
3
1Q1
1D
To Eight Other Channels
2OE
2CLR
2CLKEN
27
28
30
CE
R
2CLK
2D1
29
C1
42
15
2Q1
1D
To Eight Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABTH16823 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABTH16823 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Package thermal impedance, θJA (see Note 2): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
4
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SN54ABTH16823, SN74ABTH16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS664B – APRIL 1996 – REVISED MAY 1997
recommended operating conditions (see Note 3)
SN54ABTH16823
MAX
MIN
MAX
4.5
5.5
4.5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
200
Operating free-air temperature
–55
High-level input voltage
SN74ABTH16823
MIN
2
2
0.8
Input voltage
0
Low-level output current
Outputs enabled
VCC
–24
V
V
0.8
0
UNIT
VCC
–32
V
V
mA
48
64
mA
10
10
ns/V
µs/V
200
125
–40
85
°C
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
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5
SN54ABTH16823, SN74ABTH16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS664B – APRIL 1996 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = –18 mA
IOH = –3 mA
VCC = 5 V,
VCC = 4
4.5
5V
VOL
VCC = 4
4.5
5V
Vhys
II
MIN
TA = 25°C
TYP†
MAX
SN54ABTH16823
MIN
–1.2
MAX
SN74ABTH16823
MIN
–1.2
–1.2
2.5
2.5
2.5
IOH = –3 mA
IOH = –24 mA
3
3
3
2
2
IOH = –32 mA
IOL = 48 mA
2*
IOZPU‡
V
2
0.55
IOL = 64 mA
VCC = 0 to 5.5 V, VI = VCC or GND
VI = 0.8 V
VCC = –4.5
45V
VI = 2 V
VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE = X
UNIT
V
0.55
0.55*
0.55
100
II(hold)
I(h ld)
V
mV
±1
±1
±1
100
100
100
–100
–100
–100
µA
µA
±50
±50
±50
µA
IOZPD‡
VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE = X
±50
±50
±50
µA
IOZH
VCC = 2.1 V to 5.5 V,
VO = 2.7 V, OE ≥ 2 V
10**
50
10
µA
IOZL
VCC = 2.1 V to 5.5 V,
VO = 0.5 V, OE ≥ 2 V
–10**
–50
–10
µA
±100
µA
Ioff
ICEX
IO§
Outputs high
VCC = 0,
VCC = 5.5 V,
VI or VO ≤ 4.5 V
VO = 5.5 V
VCC = 5.5 V,
VO = 2.5 V
±100
50
–50
–100
Outputs high
ICC
Outputs low
Outputs
disabled
VCC = 5.5 V, IO = 0,
VI = VCC or GND
∆ICC¶
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
Ci
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
Co
–200
50
–50
–200
–50
POST OFFICE BOX 655303
50
µA
–200
mA
0.5
0.5
0.5
80
80
80
0.5
0.5
0.5
1.5
1.5
1.5
mA
mA
4
pF
8.5
pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
** These limits apply only to the SN74ABTH16823.
† All typical values are at VCC = 5 V.
‡ This parameter is characterized, but not production tested.
§ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
6
MAX
• DALLAS, TEXAS 75265
SN54ABTH16823, SN74ABTH16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS664B – APRIL 1996 – REVISED MAY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C
fclock
Clock frequency
tw
Pulse duration
tsu
th
Setup time before CLK↑
Hold time after CLK↑
SN54ABTH16823
SN74ABTH16823
MIN
MAX
MIN
MAX
MIN
MAX
0
150
0
150
0
150
CLR low
3.3
3.3
3.3
CLK high or low
3.3
3.3
3.3
CLR inactive
1.6
2
1.6
Data
1.7
1.7
1.7
CLKEN low
2.8
2.8
2.8
Data
1.2
1.2
1.2
CLKEN low
0.6
0.6
0.6
UNIT
MHz
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54ABTH16823
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°C
MIN
fmax
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
TYP
MIN
Q
CLR
Q
OE
Q
OE
Q
UNIT
MAX
150
CLK
MAX
150
MHz
1.6
3.9
5.5
1.6
7.7
2.1
3.9
5.4
2.1
6.4
1.9
4.1
6
1.9
6.9
1
3.1
4.2
1
5.1
1.5
3.5
4.6
1.5
5.7
2.2
4.3
6
2.2
6.8
1.6
4.3
6.4
1.6
9.9
ns
ns
ns
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN74ABTH16823
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
TA = 25°C
MIN
fmax
tPLH
Q
tPHL
CLR
Q
tPZH
tPZL
OE
Q
tPHZ
tPLZ
OE
Q
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MAX
TYP
MAX
1.6
3.9
5.5
1.6
6.8
2.1
3.9
5.4
2.1
6
1.9
4.1
6
1.9
6.7
150
CLK
tPHL
MIN
150
UNIT
MHz
1
3.1
4.2
1
4.9
1.5
3.5
4.6
1.5
5.5
2.2
4.3
5.6
2.2
6.1
1.6
4.3
6.4
1.6
8.7
ns
ns
ns
ns
7
SN54ABTH16823, SN74ABTH16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCBS664B – APRIL 1996 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
S1
7V
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
3V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
3V
th
3V
Input
1.5 V
1.5 V
0V
Data Input
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
VOH
1.5 V
Output
1.5 V
VOL
VOH
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
1.5 V
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLH
tPHL
Output
3V
Output
Control
tPHL
tPLH
1.5 V
Output
Waveform 2
S1 at Open
(see Note B)
1.5 V
3.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
1.5 V
VOH – 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
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