LF48410 LF48410 DEVICES INCORPORATED 1024 x 24-bit Video Histogrammer 1024 x 24-bit Video Histogrammer DEVICES INCORPORATED FEATURES DESCRIPTION ❑ 40 MHz Data Input and Computation Rate ❑ 1024 x 24-bit Memory Array ❑ Histograms of Images up to 4K x 4K with 10-bit Pixel Resolution ❑ Memory Array Flash Clear ❑ User-Programmable Modes: Histogram, Histogram Accumulate, Look Up Table, Bin Accumulate, Delay Memory, Delay and Subtract, Single Port RAM ❑ Replaces Harris HSP48410 ❑ 84-pin PLCC, J-Lead The LF48410 is capable of generating histograms and Cumulative Distribution Functions of video images. It may also be used as a look up table, a bin accumulator, a delay memory (delay and subtract also possible), or a single port RAM. The on-chip 1024 x 24-bit memory array facilitates histograms of images up to 4K x 4K pixels with a 10-bit pixel resolution. Once the histogram of a video image is stored in the memory array, the Cumulative Distribution Function can be calculated by putting the device in Histogram Accumulate Mode. Transformation functions can be performed on pixel values when the device is in Look Up Table Mode. If the Cumulative Distribution Function is the desired transformation function, the LF48410 can calculate it and have it available for Look Up Table Mode. When the device is in Delay Memory Mode, it functions as a video row buffer. In this mode, the LF48410 can buffer video lines as long as 1029 pixels. The device can also function as an asynchronous single port RAM. During asynchronous modes, the device can be configured as a 1024 x 24, 1024 x 16, or 1024 x 8-bit RAM. A Flash Clear function is provided which sets all memory array locations and data path registers to “0”. LF48410 BLOCK DIAGRAM RAM ARRAY DATA IN 24 ADDRESS 3 DIN23-0 DATA OUT WR ADDER INPUT CONTROL 10 DIO I/F 24 DIO23-0 IOA9-0 ADDRESS GENERATOR 10 PIN9-0 CLK (TO ALL REGISTERS) COUNTER WR RD UWS START FC CONTROL 3 FCT2-0 LD FUNCTION DECODE MUX CONTROL SIGNALS Video Imaging Products 1 08/08/2000–LDS.48410-L LF48410 DEVICES INCORPORATED SIGNAL DEFINITIONS Power VCC and GND +5 V power supply. All pins must be connected. Clock CLK — Master Clock When operating in a synchronous mode, the rising edge of CLK strobes all enabled registers. CLK has no effect when operating in an asynchronous mode. Inputs PIN9-0 — Pixel Data Input PIN9-0 provides address information to the memory array in Histogram, Bin Accumulate, and Look Up Table Modes. Data is latched on the rising edge of CLK. DIN23-0 — Data Input In Bin Accumulate Mode, DIN23-0 provides data to the internal summer to be added to data already in the memory array. In Look Up Table Mode, DIN23-0 is used to load the memory array with the desired values. In Delay Memory Mode, the data to be delayed is input to the memory array using DIN23-0, and in Delay and Subtract Mode it also provides data to be subtracted from the delayed data. In all four modes, DIN23-0 is latched on the rising edge of CLK. IOA9-0 — Asynchronous Address Input IOA9-0 provides address information to the memory array in Asynchronous 16 and 24 Modes. FCT2-0 — Function Input FCT2-0 is used to put the LF48410 into one of its eight modes of operation (Table 1). Data is latched on the 1024 x 24-bit Video Histogrammer rising edge of LD. To ensure proper operation of the device, START must be HIGH while changing modes, and there must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START. Inputs/Outputs DIO23-0 — Data Input/Output In all synchronous modes, DIO23-0 is the 24-bit registered data output port. In all asynchronous modes, DIO23-0 is both the data input and data output port for the memory array. Controls START — Device Enable START is used to enable and disable the synchronous modes of operation (except for the Delay Memory and Delay and Subtract Modes). The synchronous mode sections explain how START functions in each mode. START has no effect in asynchronous modes. Data is latched on the rising edge of CLK. START must be held HIGH when changing from one mode to another. To ensure proper operation of the device, there must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START. RD — Read/Output Enable In all synchronous modes, RD is used as an output enable for DIO23-0. When RD is LOW, DIO23-0 is enabled for output. When RD is HIGH, DIO23-0 is placed in a high-impedance state. In all asynchronous modes, RD is used as a read enable for the memory array (see asynchronous mode sections for details). WR — Write Enable In all asynchronous modes, WR is used as a write enable for the memory array (see asynchronous mode sections for details). WR has no effect in the synchronous modes. UWS — Upper Word Select UWS is only used in Asynchronous 16 Mode. If UWS is LOW and a memory write is performed, data on DIO15-0 is written to the lower 16 bits of the addressed 24-bit word. If UWS is LOW and a memory read is performed, the lower 16 bits of the addressed 24-bit word will be output on DIO15-0. If UWS is HIGH and a memory write is performed, data on DIO7-0 is written to the upper 8 bits of the addressed 24-bit word. If UWS is HIGH and a memory read is performed, the upper 8 bits of the addressed 24-bit word will be output on DIO7-0. FC — Flash Clear When FC is LOW, all memory array locations and data path registers are set to “0”. To ensure that Flash Clear functions properly, FC should not be set LOW until START is HIGH (synchronous modes) or WR is HIGH (asynchronous modes). LD — Function Load Strobe Data present on FCT2-0 is latched into the LF48410 on the rising edge of LD. To ensure proper operation of the device, there must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START. TABLE 1. FCT2-0 LF48410 MODES MODE 0 0 0 Histogram 0 0 1 Histogram Accumulate 0 1 0 Delay and Subtract 0 1 1 Look Up Table 1 0 0 Bin Accumulate 1 0 1 Delay Memory 1 1 0 Asynchronous 24 1 1 1 Asynchronous 16 Video Imaging Products 2 08/08/2000–LDS.48410-L LF48410 DEVICES INCORPORATED HISTOGRAM MODE When the LF48410 is in this mode, the chip is configured as shown in Figure 1. The memory array keeps track of how many times a particular pixel value is used in a video image. The pixel value is input on PIN9-0 and is latched on the rising edge of CLK. Data at the address defined by PIN9-0 is read out of the memory array and incremented by one. The data is then written back to the memory array, in the same location it was read from, and is also output on DIO23-0 (if RD is LOW). As long as START is LOW, the device will be enabled for Histogram Mode. When START is HIGH, the device will still read pixel values, but the addres-sed data will not be incremented. The unchanged data is output on DIO23-0 and is not written back to the memory array (writing is disabled). START is delayed internally three clock cycles to match the latency of the address generator. 1024 x 24-bit Video Histogrammer FIGURE 1. HISTOGRAM MODE RAM ARRAY DATA IN After this mode is selected, the internal counter and all data path registers are reset to zero when WR DIO I/F 10 CLK FIGURE 2. DIO23-0 RD "1" START 24 "0" ADDRESS GENERATOR PIN9-0 CONTROL TO ALL REGISTERS HISTOGRAM ACCUMULATE MODE RAM ARRAY DATA IN DATA OUT ADDRESS WR DIO I/F ADDRESS GENERATOR HISTOGRAM ACCUMULATE MODE When the LF48410 is in this mode, the chip is configured as shown in Figure 2. This mode is used to calculate the Cumulative Distribution Function of a video image. Before this can be done, the histogram of the image must already be in the memory array. The internal counter is used to generate address data for the memory array. Data at the address defined by the counter is read out of the memory array and added to the sum of the data from all previous address locations. This new value is written back to the memory array, in the same location where the last read occurred, and is also output on DIO23-0 (if RD is LOW). After all memory locations with histogram data are accumulated, the memory array will contain the Cumulative Distribution Function. DATA OUT ADDRESS 24 DIO23-0 "0" RD CLK (TO ALL REGISTERS) COUNTER CONTROL START START is set LOW. Every rising edge of CLK causes the counter to increment its output by one until the counter reaches a value of 1023. At this point, the counter will hold the value of 1023 and writing to the memory array will be disabled. As long as START is LOW, the device will be enabled for Histogram Accumulate Mode. When START is HIGH, the counter will still increment its address values, but the addressed data will not be added to anything. The unchanged data is output on DIO23-0 and is not written back to the memory array (writing is disabled). START is delayed internally three clock cycles to match the latency of the address generator. LOOK UP TABLE MODE When the LF48410 is in this mode, the chip is configured as shown in Figure 3. This mode is used to perform fixed transformation functions on pixel values. The transformation function can be loaded into the memory array in Look Up Table Write Mode, Asynchronous 16/24 Mode, or Histogram Accumulate Mode. In Look Up Table Write Mode, data is loaded into the memory array using DIN23-0, CLK, and START. The internal counter is used to generate address data for the memory array. When START goes LOW, the counter is reset to zero. As long as START is LOW, data on DIN23-0 is latched on the rising edge of CLK and loaded Video Imaging Products 3 08/08/2000–LDS.48410-L LF48410 DEVICES INCORPORATED FIGURE 3. 1024 x 24-bit Video Histogrammer LOOK UP TABLE MODE RAM ARRAY 24 3 DIN23-0 DATA IN DATA OUT ADDRESS WR 24 DIO I/F 10 DIO23-0 ADDRESS GENERATOR PIN9-0 "0" BIN ACCUMULATE MODE RD CLK (TO ALL REGISTERS) COUNTER CONTROL START FIGURE 4. NOTE: NUMBER IN REGISTER INDICATES NUMBER OF PIPELINE DELAYS. BIN ACCUMULATE MODE RAM ARRAY DATA IN DATA OUT ADDRESS WR 24 DIO I/F 3 DIN23-0 10 PIN9-0 ADDRESS GENERATOR START CONTROL CLK DIO23-0 (if RD is LOW). If Look Up Table Write Mode was used to load the memory array, it is important to wait until the third clock cycle after START goes HIGH to input data on PIN9-0 to insure that all data is written into the memory array before any reading is done. into the memory array at the address defined by the counter. The value already in the memory array at that address is output on DIO23-0 (if RD is LOW). Every rising edge of CLK causes the counter to increment its output by one until the counter reaches a value of 1023. At this point, the counter will hold the value of 1023 and writing to the memory array will be disabled. DIN23-0 is delayed internally three clock cycles to match the latency of the address generator. In Asynchronous 16/24 Mode, data is loaded into the memory array as detailed in the asynchronous mode DIO23-0 RD "0" TO ALL REGISTERS 24 NOTE: NUMBER IN REGISTER INDICATES NUMBER OF PIPELINE DELAYS. sections. If the Cumulative Distribution Function is the desired transformation function, the memory array will contain this data as soon as the Histogram Accumulate function has been completed. Once the memory array contains the desired data, the device needs to be put in Look Up Table Read Mode by setting START HIGH. In Look Up Table Read Mode, pixel values are input on PIN9-0 and are latched on the rising edge of CLK. Data at the address defined by PIN9-0 is read out of the memory array and output on When the LF48410 is in this mode, the chip is configured as shown in Figure 4. PIN9-0 provides address data for the memory array and is latched on the rising edge of CLK. Data at the address defined by PIN9-0 is read out of the memory array and added to the data on DIN23-0. This new value is written back to the memory array, in the same location where the last read occured, and is also output on DIO23-0 (if RD is LOW). As long as START is LOW, the device will be enabled for Bin Accumulate Mode. When START is HIGH, the device will still read address values on PIN9-0, but the addressed data will not be added to anything. The unchanged data will be output on DIO23-0 and is not written back to the memory array (writing is disabled). START and DIN23-0 are delayed internally three clock cycles to match the latency of the address generator. DELAY MEMORY MODE When the LF48410 is in this mode, the chip is configured as shown in Figure 5. This mode allows the device to function as a row buffer. The internal counter is used to generate address data for the memory array. When START goes LOW, the counter is reset to zero. Delay length (row length) is determined by reseting the counter every N–4 clock cycles, where N is the number of delays. For Video Imaging Products 4 08/08/2000–LDS.48410-L LF48410 DEVICES INCORPORATED FIGURE 5. DELAY MEMORY MODE RAM ARRAY 24 DIN23-0 DATA IN 3 example, to set the number of delays to 10, START would have to be set LOW every 6 cycles. The maximum delay length is 1029 and the minimum delay length is 6. Data on DIN 23-0 is latched on the rising edge of CLK and loaded into the memory array at the address defined by the counter. Data is output on DIO23-0 (if RD is LOW). If the counter reaches the value of 1023, the counter will hold this value and writing to the memory array will be disabled. 1024 x 24-bit Video Histogrammer DATA OUT ADDRESS WR DIO I/F CLK (TO ALL REGISTERS) DIO23-0 COUNTER "0" RD START CONTROL NOTE: NUMBER IN REGISTER INDICATES NUMBER OF PIPELINE DELAYS. DELAY AND SUBTRACT MODE FIGURE 6. DELAY AND SUBTRACT MODE RAM ARRAY 24 DIN23-0 DATA IN 3 When the LF48410 is in this mode, the chip is configured as shown in Figure 6. The internal counter is used to generate address data for the memory array. When START goes LOW, the counter is reset to zero. Delay length (row length) is determined by reseting the counter every N–4 clock cycles, where N is the number of delays. The maximum delay length is 1029 and the minimum delay length is 6. Data on DIN23-0 is latched on the rising edge of CLK and loaded into the memory array at the address defined by the counter. Data is output on DIO23-0 (if RD is LOW). Before data read from the memory array is output to DIO23-0, input data is subtracted from it according to the following formula: OUTC = D(C–N+1) – D(C–3). OUTC is the data sent to the output port (DIO23-0) on clock cycle C. D(C–N+1) is the data latched into the device on clock cycle C–N+1, and D(C3) is the data latched into the device on clock cycle C–3. N is the number of delays. For example, to determine what will be output on DIO23-0 on clock cycle 12 when the device is set for 10 delays, set C=12 and N=10 to obtain: OUT12 = D3 – D9. If the counter reaches the value of 1023, the counter will hold this value and writing to the memory array will be disabled. 24 DATA OUT ADDRESS WR DIO I/F CLK (TO ALL REGISTERS) 24 DIO23-0 COUNTER –DIN23-0 RD CONTROL START NOTE: NUMBER IN REGISTER INDICATES NUMBER OF PIPELINE DELAYS. ASYNCHRONOUS 16 MODE When the LF48410 is in this mode, the chip is configured as shown in Figure 7. This mode allows the device to function as an asynchronous single port RAM. Each 24-bit memory location is split into two parts, the lower 16 bits and the upper 8 bits. IOA9-0 addresses the 24-bit memory locations, and UWS addresses the lower 16 or upper 8 bits of those locations. If UWS is LOW, the lower 16 bits of the 24-bit memory location are addressed. If UWS is HIGH, the upper 8 bits are addressed. Address data on IOA9-0 and UWS is latched into the device on the falling edge of RD or WR. If RD latches the address data, a memory read is performed. Data at the specified address is output on DIO15-0 (if UWS was latched LOW) or DIO7-0 (if UWS was latched HIGH). If UWS was latched LOW/HIGH, DIO16-23/DIO8-23 will output zeros during a memory read. If WR latches the address data, a memory write is performed. After the falling edge of WR latches the address, data on DIO15-0 (if UWS was latched LOW) or DIO7-0 (if UWS was latched HIGH) is written to the RAM on the rising edge of WR. Video Imaging Products 5 08/08/2000–LDS.48410-L LF48410 DEVICES INCORPORATED ASYNCHRONOUS 24 MODE When the LF48410 is in this mode, the chip is configured as shown in Figure 7. In this mode, the device functions the same as when in Asynchronous 16 Mode except that the 24-bit memory locations are not split into two parts. All 24 bits are used during a read or write operation. When reading, data is output on DIO23-0. When writing, data is input on DIO23-0. UWS is not used in this mode. 1024 x 24-bit Video Histogrammer FIGURE 7. ASYNCHRONOUS 16/24 MODE RAM ARRAY DATA IN DATA OUT ADDRESS 10 IOA9-0 ADDRESS GENERATOR WR RD UWS CONTROL DIO I/F 24 DIO23-0 WR Video Imaging Products 6 08/08/2000–LDS.48410-L LF48410 DEVICES INCORPORATED 1024 x 24-bit Video Histogrammer MAXIMUM RATINGS Above which useful life may be impaired (Notes 1, 2, 3, 8) Storage temperature ........................................................................................................... –65°C to +150°C Operating ambient temperature ........................................................................................... –55°C to +125°C VCC supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V Input signal with respect to ground ............................................................................... –0.5 V to V CC + 0.5 V Signal applied to high impedance output ...................................................................... –0.5 V to VCC + 0.5 V Output current into low outputs ............................................................................................................. 25 mA Latchup current ............................................................................................................................... > 400 mA OPERATING CONDITIONS To meet specified electrical and switching characteristics Mode Active Operation, Commercial Active Operation, Military Temperature Range (Ambient) 0°C to +70°C –55°C to +125°C Supply Voltage 4.75 V ≤ VCC ≤ 5.25 V 4.50 V ≤ VCC ≤ 5.50 V ELECTRICAL CHARACTERISTICS Over Operating Conditions (Note 4) Symbol Parameter Test Condition Min VOH Output High Voltage VCC = Min., IOH = –2.0 mA 2.6 VOL Output Low Voltage VCC = Min., IOL = 4.0 mA VIH Input High Voltage VIL Input Low Voltage (Note 3) IIX Input Current IOZ Typ Max Unit V 0.4 V 2.2 VCC V 0.0 0.8 V Ground ≤ VIN ≤ VCC (Note 12) ±10 µA Output Leakage Current Ground ≤ VOUT ≤ VCC (Note 12) ±10 µA ICC1 VCC Current, Dynamic (Notes 5, 6) 310 mA ICC2 VCC Current, Quiescent (Note 7) 500 µA CIN Input Capacitance TA = 25°C, f = 1 MHz 12 pF COUT Output Capacitance TA = 25°C, f = 1 MHz 12 pF Video Imaging Products 7 08/08/2000–LDS.48410-L LF48410 DEVICES INCORPORATED 1024 x 24-bit Video Histogrammer SWITCHING CHARACTERISTICS COMMERCIAL OPERATING RANGE (0°C to +70°C) Notes 9, 10 (ns) 30 Symbol 1234567890123456 1234567890123456 1234567890123456 15* 1234567890123456 1234567890123456 Max 1234567890123456 Min Max 1234567890123456 1234567890123456 15 1234567890123456 1234567890123456 1234567890123456 1234567890123456 10 1234567890123456 1234567890123456 1234567890123456 10 1234567890123456 1234567890123456 1234567890123456 5 1234567890123456 1234567890123456 1234567890123456 2 1234567890123456 1234567890123456 1234567890123456 5 1234567890123456 1234567890123456 1234567890123456 1234567890123456 2 1234567890123456 1234567890123456 1234567890123456 5 1234567890123456 1234567890123456 1234567890123456 2 1234567890123456 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18 1234567890123456 15 1234567890123456 1234567890123456 18 1234567890123456 15 1234567890123456 LF48410– 25 Parameter Min Max Min tCYC Cycle Time 30 25 tPWL Clock Pulse Width Low 12 10 tPWH Clock Pulse Width High 12 10 tPS PIN9-0 Setup Time 13 12 tPH PIN9-0 Hold Time 2 2 tDS DIN23-0 Setup Time 13 12 tDH DIN23-0 Hold Time 2 2 tSS START Setup Time 13 12 tSH START Hold Time 2 2 tCY Read/Write Cycle Time 65 55 tAS Address Setup Time 15 13 tAH Address Hold Time 2 2 tWL WR Pulse Width Low 15 12 tWH WR Pulse Width High 15 12 tWDS DIO23-0 Setup Time 15 12 tWDH DIO23-0 Hold Time 2 2 tRL RD Pulse Width Low 43 35 tRH RD Pulse Width High 17 15 tRD RD Low to DIO23-0 Valid 43 tOH RD High to DIO23-0 Valid 0 tLL LD Pulse Width 12 10 tLS LD Setup to START 30 25 tFS FCT2-0 Setup Time 10 10 tFH FCT2-0 Hold Time 2 2 tFL FC Pulse Width 35 35 tD Output Delay 19 tENA Three-State Output Enable Delay (Note 11) 19 tDIS Three-State Output Disable Delay (Note 11) 19 123456789012345678901234 123456789012345678901234 123456789012345678901234 *DISCONTINUED SPEED GRADE 123456789012345678901234 Video Imaging Products 8 08/08/2000–LDS.48410-L LF48410 DEVICES INCORPORATED 1024 x 24-bit Video Histogrammer SWITCHING CHARACTERISTICS MILITARY OPERATING RANGE (–55°C to +125°C) Notes 9, 10 (ns) Symbol LF48410– 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 * 39 30* 25* 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 Min Max Min Max Min Max 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 39 30 25 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 15 12 12 1234567890123456789012345678901212345678901234 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1234567890123456789012345678901212345678901234 2 2 2 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 80 65 55 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 20 16 13 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 2 2 2 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 20 15 12 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 20 15 10 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 20 16 12 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1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 39 30 25 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 15 12 10 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 2 2 2 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 35 35 35 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 24 19 15 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 24 19 18 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 1234567890123456789012345678901212345678901234 27 27 18 1234567890123456789012345678901212345678901234 Parameter tCYC Cycle Time tPWL Clock Pulse Width Low tPWH Clock Pulse Width High tPS PIN9-0 Setup Time tPH PIN9-0 Hold Time tDS DIN23-0 Setup Time tDH DIN23-0 Hold Time tSS START Setup Time tSH START Hold Time tCY Read/Write Cycle Time tAS Address Setup Time tAH Address Hold Time tWL WR Pulse Width Low tWH WR Pulse Width High tWDS DIO23-0 Setup Time tWDH DIO23-0 Hold Time tRL RD Pulse Width Low tRH RD Pulse Width High tRD RD Low to DIO23-0 Valid tOH RD High to DIO23-0 High Z tLL LD Pulse Width tLS LD Setup to START tFS FCT2-0 Setup Time tFH FCT2-0 Hold Time tFL FC Pulse Width tD Output Delay tENA Three-State Output Enable Delay (Note 11) tDIS Three-State Output Disable Delay (Note 11) 123456789012345678901234 123456789012345678901234 123456789012345678901234 *DISCONTINUED SPEED GRADE 123456789012345678901234 Video Imaging Products 9 08/08/2000–LDS.48410-L LF48410 DEVICES INCORPORATED 1024 x 24-bit Video Histogrammer SWITCHING WAVEFORMS: HISTOGRAM MODE 1 2 3 4 5 6 7 CLK tSS tSS tSH tPWH tPWL tCYC START tPH tPS PIN9-0 tSH 1 2 3 4 5 6 7 1 2 3* RD tDIS tENA tD HIGH IMPEDANCE DIO23-0 *RAM contents not changed. SWITCHING WAVEFORMS: HISTOGRAM ACCUMULATE MODE 1 2 3 4 5 6 7 CLK tSS tSS tSH tPWH tPWL tCYC START tSH RD tDIS tENA tD HIGH IMPEDANCE DIO23-0 1 2 3* *RAM contents not changed. SWITCHING WAVEFORMS: BIN ACCUMULATE MODE 1 2 3 4 5 6 7 CLK tSS tSS tSH tPWH tPWL tCYC START tPS PIN9-0 tSH 1 tDS DIN23-0 tPH 2 3 4 5 6 7 2 3 4 5 6 7 1 2 3* tDH 1 RD tDIS DIO23-0 tENA tD HIGH IMPEDANCE *RAM contents not changed. Video Imaging Products 10 08/08/2000–LDS.48410-L LF48410 DEVICES INCORPORATED 1024 x 24-bit Video Histogrammer SWITCHING WAVEFORMS: LOOK UP TABLE WRITE MODE 1 2 3 4 5 6 7 CLK tPWH tPWL tCYC tSS START* tDH tDS DIN23-0 1 2 3 4 5 6 7 1 2 3 4 tD RD tDIS tENA HIGH IMPEDANCE DIO23-0 *START must be held LOW a minimum of tSH after the rising edge of CLK that loads the last value of DIN23-0. SWITCHING WAVEFORMS: LOOK UP TABLE READ MODE 1 2 3 4 5 6 7 CLK tSS tPWH tPWL tCYC START* tDH tDS PIN9-0 1 2 3 4 5 tD RD tDIS tENA HIGH IMPEDANCE DIO23-0 1 *START must be held HIGH a minimum of tSH after the rising edge of CLK that loads the last value of PIN9-0. SWITCHING WAVEFORMS: 1 DELAY MEMORY/DELAY AND SUBTRACT MODE 2 3 4 5 6 7 8 9 10 11 12 13 14 CLK tSH tSS tPWH tPWL tSH tSS tCYC tSS tSH START tDH tDS DIN23-0 1 tSH tSS 2 3 4 5 6 7 8 9 10 11 tSH tSS 12 13 14 RD tDIS DIO23-0 tENA tD HIGH IMPEDANCE 1 2 3 4 Shown are the waveforms for a delay length of 10. Video Imaging Products 11 08/08/2000–LDS.48410-L LF48410 DEVICES INCORPORATED 1024 x 24-bit Video Histogrammer SWITCHING WAVEFORMS: ASYNCHRONOUS WRITE 16/24 MODE tCY tWL tWH WR RD tAS tAH IOA9-0 UWS* tWDS tWDH DIO23-0 *applies only to 16-bit Asynchronous Mode. SWITCHING WAVEFORMS: ASYNCHRONOUS READ 16/24 MODE WR tCY tRL tRH RD tAS tAH IOA9-0 UWS* tRD DIO23-0 tDIS HIGH IMPEDANCE HIGH IMPEDANCE *applies only to 16-bit Asynchronous Mode. SWITCHING WAVEFORMS: FUCNTION LOAD SWITCHING WAVEFORMS: FLASH CLEAR tLL LD tFS tFH tFL FCT2-0 FC tLS START* *there must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START. Video Imaging Products 12 08/08/2000–LDS.48410-L LF48410 DEVICES INCORPORATED 1024 x 24-bit Video Histogrammer NOTES 1. Maximum Ratings indicate stress specifications only. Functional operation of these products at values beyond those indicated in the Operating Conditions table is not implied. Exposure to maximum rating conditions for extended periods may affect reliability. 9. AC specifications are tested with input transition times less than 3 ns, output reference levels of 1.5 V (except tDIS test), and input levels of nominally 0 to 3.0 V. Output loading may be a resistive divider which provides for specified IOH and IOL at an output voltage of VOH min and VOL max 2. The products described by this spec- respectively. Alternatively, a diode ification include internal circuitry de- bridge with upper and lower current signed to protect the chip from damagsources of I OH and I OL respectively, ing substrate injection currents and ac- and a balancing voltage of 1.5 V may be cumulations of static charge. Neverthe- used. Parasitic capacitance is 30 pF less, conventional precautions should minimum, and may be distributed. be observed during storage, handling, and use of these circuits in order to This device has high-speed outputs caavoid exposure to excessive electrical pable of large instantaneous current stress values. pulses and fast turn-on/turn-off times. As a result, care must be exercised in the 3. This device provides hard clamping of testing of this device. The following transient undershoot and overshoot. In- measures are recommended: put levels below ground or above VCC will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be VCC + 0.6 V. The device can withstand installed between VCC and Ground indefinite operation with inputs in the leads as close to the Device Under Test range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors tion will not be adversely affected, how- should be installed between device VCC ever, input current levels will be well in and the tester common, and device ground and tester common. excess of 100 mA. 4. Actual test conditions may vary from b. Ground and VCC supply planes those designated but operation is guar- must be brought directly to the DUT anteed as specified. socket or contactor fingers. 5. Supply current for a given applica- c. Input voltages should be adjusted to tion can be accurately approximated by: compensate for inductive ground and VCC noise to maintain required DUT input NCV2 F levels relative to the DUT ground pin. 4 where 10. Each parameter is shown as a min- 11. For the tENA test, the transition is measured to the 1.5 V crossing point with datasheet loads. For the tDIS test, the transition is measured to the ±200mV level from the measured steady-state output voltage with ±10mA loads. The balancing voltage, V TH , is set at 3.5 V for Z-to-0 and 0-to-Z tests, and set at 0 V for Zto-1 and 1-to-Z tests. 12. These parameters are only tested at the high temperature extreme, which is the worst case for leakage current. FIGURE A. OUTPUT LOADING CIRCUIT S1 DUT IOL VTH CL IOH FIGURE B. THRESHOLD LEVELS tENA OE Z tDIS 1.5 V 1.5 V 3.5V Vth 0 1.5 V 1.5 V Z 1 VOL* 0.2 V VOH* 0.2 V 0 Z 1 Z 0V Vth VOL* Measured VOL with IOH = –10mA and IOL = 10mA VOH* Measured VOH with IOH = –10mA and IOL = 10mA imum or maximum value. Input requirements are specified from the point of view of the external system driving the chip. Setup time, for example, is specified as a minimum since the exter6. Tested with all outputs changing ev- nal system must supply at least that ery cycle and no load, at a 20 MHz clock much time to meet the worst-case requirements of all parts. Responses from rate. the internal circuitry are specified from 7. Tested with all inputs within 0.1 V of the point of view of the device. Output VCC or Ground, no load. delay, for example, is specified as a 8. These parameters are guaranteed maximum since worst-case operation of any device always provides data within but not 100% tested. that time. N = total number of device outputs C = capacitive load per output V = supply voltage F = clock frequency Video Imaging Products 13 08/08/2000–LDS.48410-L LF48410 DEVICES INCORPORATED 1024 x 24-bit Video Histogrammer ORDERING INFORMATION PIN0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 PIN8 VCC CLK GND PIN9 DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 84-pin 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 12 74 13 73 14 72 15 71 16 70 17 69 18 68 19 67 20 66 Top View 21 22 23 65 64 63 24 62 25 61 26 60 27 59 28 58 29 57 30 56 31 55 32 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 DIN8 DIN9 DIN10 DIN11 DIN12 DIN13 DIN14 DIN15 DIN16 DIN17 GND DIN18 DIN19 DIN20 DIN21 DIN22 DIN23 DIO23 DIO22 DIO21 DIO20 DIO0 DIO1 DIO2 DIO3 DIO4 DIO5 DIO6 DIO7 GND DIO8 DIO9 DIO10 DIO11 DIO12 DIO13 DIO14 DIO15 DIO16 DIO17 DIO18 DIO19 FC RD START LD FCT2 FCT1 FCT0 WR GND UWS IOA9 IOA8 IOA7 IOA6 IOA5 IOA4 IOA3 IOA2 IOA1 IOA0 VCC Plastic J-Lead Chip Carrier (J3) Speed 0°C to +70°C — COMMERCIAL SCREENING 30 ns 25 ns LF48410JC30 LF48410JC25 –40°C to +85°C — COMMERCIAL SCREENING Video Imaging Products 14 08/08/2000–LDS.48410-L LF48410 DEVICES INCORPORATED 1024 x 24-bit Video Histogrammer ORDERING INFORMATION 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 84-pin 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1 2 3 4 5 6 7 8 9 10 11 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 A 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 PIN0 PIN2 PIN3 PIN5 PIN8 VCC PIN9 DIN2 DIN4 DIN5 DIN8 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 B 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 START FC PIN1 PIN4 PIN7 DIN1 DIN0 DIN3 DIN6 DIN7 DIN10 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 C 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 RD LD PIN6 CLK GND DIN9 DIN11 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 D 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 FCT1 FCT2 DIN12 DIN13 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 E 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Top View 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 GND WR FCT0 DIN14 DIN15 DIN16 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Through Package F 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 IOA5 UWS IOA9 GND DIN21 DIN17 (i.e., Component Side Pinout) 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 G 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 IOA7 IOA6 IOA8 DIN18 DIN20 DIN19 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 H 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 IOA4 IOA3 DIN23 DIN22 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 J 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 IOA2 IOA0 DIO6 DIO9 DIO10 DIO21 DIO23 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 K 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 IOA1 DIO0 DIO1 DIO4 DIO7 DIO8 DIO12 DIO15 DIO18 DIO20 DIO22 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 L 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 VCC DIO2 DIO3 DIO5 GND DIO13 DIO11 DIO14 DIO16 DIO17 DIO19 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Discontinued Package 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121 Ceramic Pin Grid Array (G6) Speed 0°C to +70°C — COMMERCIAL SCREENING –55°C to +125°C — COMMERCIAL SCREENING –55°C to +125°C — MIL-STD-883 COMPLIANT Video Imaging Products 15 08/08/2000–LDS.48410-L