HSP48410/883 TM Data Sheet May 1999 FN3542.2 Histogrammer/Accumulating Buffer Features The Intersil HSP48410/883 is an 84 lead Histogrammer IC int.ended for use in image and signal analysis. The on board memory is configured as 1024 x 24 array. This translates to a pixel resolution of 10 bits and an image size of 4k x 4k with no possibility of overflow. • This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • 10-Bit Pixel Data • 4k x 4k Frame Sizes In addition to 4-Histogramming, the HSP48410 can generate and store the Cumulative Distribution Function for use in Histogram Equalization Applications. Other capabilities of the HSP48410 include: Bin Accumulation, Look Up Table, 24-bit Delay Memory, and Delay and Subtract Mode. • Asynchronous Flash Clear Pin • Fully Asynchronous 16-Bit or 24-Bit Host Interface • DC to 33MHz Clock Rate Applications A flash clear pin is available in all modes of operation and performs a single cycle reset on all locations of the internal memory array and all internal data paths. • Histogramming • Histogram Equalization The HSP48410 includes a fully asynchronous interface which provides a means for communications with a host, such as a microprocessor. The interface includes dedicated Read/Write pins and an address port which are asynchronous to the system clock. This allows random access of the Histogram Memory Array for analysis or conditioning of the stored data. • Image and Signal Analysis Ordering Information PART NUMBER TEMP. RANGE ( oC) PACKAGE PKG. NO. HSP48410GM-33/883 -55 to 125 84 Ld PGA G84.A HSP48410GM-25/883 -55 to 125 84 Ld PGA G84.A Block Diagram HISTOGRAM MEMORY ARRAY MUX DATA IN DATA OUT ADDER DIO0-23 DIO INTERACE DIN0-23 ADDRESS PIN0-9 ADDRESS GENERATOR IOADD0-9 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved HSP48410/883 Pinouts 84 PIN PGA TOP VIEW PIN “A1” ID 11 DIN8 DIN10 DIN11 DIN13 DIN16 DIN17 DIN19 DIN22 DIO23 DIO22 DIO19 10 DIN5 DIN7 DIN9 DIN12 DIN15 DIN21 DIN20 DIN23 DIO21 DIO20 DIO17 9 DIN4 DIN6 DIN14 GND DIN18 DIO18 DIO16 8 DIN2 DIN3 DIO15 DIO14 7 PIN9 DIN0 GND DIO10 DIO12 DIO11 6 VCC DIN1 CLK DIO9 DIO8 DIO13 5 PIN8 PIN7 PIN6 DIO6 DIO7 GND 4 PIN5 PIN4 DINO4 DINO5 3 PIN3 PIN1 DIO1 DIO3 2 PIN2 FC RD FCT2 WR DIO0 DIO2 1 PIN0 START LD FCT1 GND A B C D E FCT0 IOADD9 IOADD8 UWS IOADD6 IOADD3 IOADD0 IOADD5 IOADD7 IOADD4 IOADD2 IOADD1 F G VCC H J K L 84 PIN PGA BOTTOM VIEW DIN19 DIO22 DIO23 DIN22 DIN19 DIN17 DIN16 DIN13 DIN11 DIN10 DIN8 11 DIO17 DIO20 DIO21 DIN23 DIN20 DIN21 DIN15 DIN12 DIN9 DIN7 DIN5 10 DIO16 DIO18 DIN18 GND DIN14 DIN6 DIN4 9 DIO14 DIO15 DIN3 DIN2 8 DIO11 DIO12 DIO10 GND DIN0 DIN9 7 DIO13 DIO8 DIO9 CLK DIN1 VCC 6 GND DIO7 DIO6 PIN6 PIN7 PIN8 5 DIO5 DIO4 PIN4 PIN5 4 DIO3 DIO4 PIN1 PIN3 3 DIO2 DIO0 VCC IOADD8 IOADD9 IOADD3 IOADD3 IOADD6 UWS IOADD1 IOADD2 IOADD4 IOADD7 IOADD5 L K 2 J H G F FCT0 WR FCT2 RD FC PIN2 2 GND FCT1 LD START PIN0 1 E D C B A HSP48410/883 Pin Description SYMBOL PIN NUMBER TYPE DESCRIPTION CLK C6 I Clock Input. This input has no effect on the chips functionality when the chip is programmed to an asynchronous mode. All signals denoted as synchronous have their timing specified with reference to this signal. PIN0-9 A1-5, A7, B3-5, C5 I Pixel Input. This input bus is sampled by the rising edge of clock. It provides the on chip RAM with address values in Histogram, Bin Accumulate and LUT (write) mode. During Asynchronous modes it is unused. LD C1 I The Load pin is used to load the FCT0-2 bits into the FCT Registers. (See below). FCT0-2 D1-2, E3 I These three pins are decoded to determine the mode of operation for the chip. The signals are sampled by the rising edge of LD and take effect after the rising edge of LD. Since the loading of this function is asynchronous to CLK, it is necessary to disable the START pin during loading and enable START at least 1 CLK cycle following the LD pulse. START B1 I This pin informs the on chip circuitry which clock cycle will start and/or stop the current mode of operation. Thus, the modes are asynchronously selected (via LD) but are synchronously started and stopped. This input is sampled by the rising edge of CLK. The actual function of this input depends on the mode that is selected. START must always be held high (disabled) when changing modes. This will provide a smooth transition from one mode to the next by allowing the part to reconfigure itself before new mode begins. When START is high, LUT (read) mode is enabled except for Delay and Subtract Modes. FC B2 I Flash Clear. This input provides a fully asynchronous signal which effectively resets all bits in the RAM Array and the input and output data paths to zero. DIN0-23 A8-11, B6-11, C10-11, D10-11, E9-11, F10-11, G9-11, H10-11 I Data Input Bus. Provides data to the Histogrammer during Bin Accumulate, LUT, Delay and Delay and Subtract Modes. Synchronous to CLK. DIO0-23 J5-7, J10-11, K2-11, L2-4, L6-11 I/O Asynchronous Data Bus. Provides RAM access for a microprocessor in preconditioning the memory array and reading the results of the previous operation. Configurable as either a 24-bit or 16-bit bus. IOADD0-9 F1, F3, G1-3, H1-2, J1-2, K1 I RAM Address in Asynchronous Modes. Sampled on the falling edge of WR or RD. UWS F2 I Upper Word Select. In 16-bit asynchronous mode, a one on this pin denotes the contents of DIO0-7 as being the upper eight-bits of the data in or out of the Histogrammer. A zero means that DIO0-15 are the lower 16 bits. In all other modes, this pin has no effect. WR E2 I Write enable to the RAM for the data on DIO0-23 when the HSP48410 is configured in one of the asynchronous modes. Asynchronous to CLK. RD C2 I Read control for the data on DIO0-23 in asynchronous modes. Output enable for DIO0-23 in other modes. Asynchronous to CLK. VCC A6, L1 +5V. GND C7, E1, F9, L5 Ground. 3 HSP48410/883 Absolute Maximum Ratings Thermal Information Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8V Input, Output Voltage . . . . . . . . . . . . . . . . .GND -0.5V to VCC +0.5V ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, Note 1) Operating Conditions Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC θJA ( oC/W) θJC (oC/W) PGA Package. . . . . . . . . . . . . . . . . . . . 36 7.0 Maximum Package Power Dissipation at 125oC PGA Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.46 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3,500 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. DC ELECTRICAL SPECIFICATIONS Device Guaranteed and 100% Tested PARAMETER SYMBOL CONDITIONS GROUP A SUBGROUP TEMP (oC) MIN MAX UNITS Logical One Input Voltage VIH VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 2.2 - V Logical Zero Input Voltage VIL VCC = 4.5V 1, 2, 3 -55 ≤ TA ≤ 125 - 0.8 V High Level Clock Input V IHC VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 3.0 - V Low Level Clock Input VILC VCC = 4.5V 1, 2, 3 -55 ≤ TA ≤ 125 - 0.8 V Output High Voltage VOH IOH = -400µA, VCC = 4.5V (Note 2) 1, 2, 3 -55 ≤ TA ≤ 125 2.6 - V Output Low Voltage VOL IOL = +2.0mA, VCC = 4.5V (Note 2) 1, 2, 3 -55 ≤ TA ≤ 125 - 0.4 V Input Leakage Current IL VIN = VCC or GND, VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 -10 10 µA I/O Leakage Current IO VOUT = VCC or GND, VCC = 5.5V 1, 2, 3 -55 ≤ TA ≤ 125 -10 10 µA Standby Supply Current ICCSB VIN = VCC or GND, VCC = 5.5V, Outputs Open 1, 2, 3 -55 ≤ TA ≤ 125 - 500 µA Operating Power Supply Current ICCOP f = 25.6MHz, VIN = VCC or GND VCC = 5.5V (Note 3) 1, 2, 3 -55 ≤ TA ≤ 125 - 308 mA 7, 8 -55 ≤ TA ≤ 125 - - - Functional Test FT (Notes 4, 5) NOTES: 2. Interchanging of force and sense conditions is permitted. 3. Power supply current is proportional to operating frequency. Typical rating for ICCOP is 12mA/MHz. Maximum junction temperature must be considered when operating part at high clock frequencies. 4. Tested as follows: f = 1MHz, VIH = 2.6V, VIL = 0.4V, VOH ≥ 1.5V, VOL ≤ 1.5V, VIHC = 3.4V and VILC = 0.4V. 5. Loading is as specified in the test load circuit with CL = 40pF. 4 HSP48410/883 TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: V CC = 5.0V ±10%, TA = -55oC to 125oC (Note 1) -33 (33MHz) PARAMETER SYMBOL NOTES -25 (25.6MHz) GROUP A SUBGROUPS TEMP ( oC) MIN MAX MIN MAX UNITS Clock Period t CP 9, 10, 11 -55 ≤ TA ≤ 125 30 - 39 - ns Clock Low t CH 9, 10, 11 -55 ≤ TA ≤ 125 12 - 15 - ns Clock High t CL 9, 10, 11 -55 ≤ TA ≤ 125 12 - 15 - ns DIN Setup t DS 9, 10, 11 -55 ≤ TA ≤ 125 15 - 16 - ns DIN 0-23 Hold t DH 9, 10, 11 -55 ≤ TA ≤ 125 1 - 1 - ns Clock to DIO 0-23 Valid t DO 9, 10, 11 -55 ≤ TA ≤ 125 - 19 - 24 ns FC Pulse Width t FL 9, 10, 11 -55 ≤ TA ≤ 125 35 - 35 - ns FCT 0-2 Setup to LD t FS 9, 10, 11 -55 ≤ TA ≤ 125 12 - 15 - ns FCT 0-2 Hold from LD t FH 9, 10, 11 -55 ≤ TA ≤ 125 1 - 1 - ns START Setup to CLK t SS 9, 10, 11 -55 ≤ TA ≤ 125 15 - 16 - ns START Hold from CLK t SH 9, 10, 11 -55 ≤ TA ≤ 125 0 - 0 - ns PIN 0-9 Setup Time t PS 9, 10, 11 -55 ≤ TA ≤ 125 15 - 16 - ns PIN 0-9 Hold Time t PH 9, 10, 11 -55 ≤ TA ≤ 125 1 - 1 - ns LD Pulse Width t LL 9, 10, 11 -55 ≤ TA ≤ 125 12 - 15 - ns LD Setup to START t LS 9, 10, 11 -55 ≤ TA ≤ 125 tCP tCP - ns WR Low t WL 9, 10, 11 -55 ≤ TA ≤ 125 15 - 20 - ns WR High t WH 9, 10, 11 -55 ≤ TA ≤ 125 15 - 20 - ns Address Setup t AS 9, 10, 11 -55 ≤ TA ≤ 125 16 - 20 - ns Address Hold t AH 9, 10, 11 -55 ≤ TA ≤ 125 2 - 2 - ns DIO Setup to WR t WS 9, 10, 11 -55 ≤ TA ≤ 125 16 - 20 - ns DIO Hold from WR t WH 9, 10, 11 -55 ≤ TA ≤ 125 2 - 2 - ns RD Low t RL 9, 10, 11 -55 ≤ TA ≤ 125 43 - 55 - ns RD High t RH 9, 10, 11 -55 ≤ TA ≤ 125 17 - 20 - ns RD Low to DIO Valid t RD 9, 10, 11 -55 ≤ TA ≤ 125 - 43 - 55 ns Output Enable Time t OE 9, 10, 11 -55 ≤ TA ≤ 125 - 19 - 24 ns Read/Write Cycle Time t CY 9, 10, 11 -55 ≤ TA ≤ 125 65 - 80 - ns Note 7 Note 8 NOTES: 6. AC Testing is performed as follows: Input levels (CLK) 0.0V and 4.0V; input levels (all other inputs) 0V and 3.0V. Timing reference levels (CLK) = 2.0V, (all others) = 1.5V. Output load circuit with CL= 40pF. Output transition measured at V OH ≥ 1.5V and VOL ≥ 1.5V. 7. There must be at least one rising edge of CLK between the rising edge of LD and the falling edge of START. 8. Transition is measured at ±200 mV from steady state voltage with loading as specified in test load circuit with CL= 40pF. 5 HSP48410/883 TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS -33 (33MHz) -25 (25.6MHz) MIN MAX MIN MAX UNITS SYMBOL CONDITIONS NOTES TEMP (oC) Input Capacitance CIN VCC = Open, f = 1MHz, all measurements are referenced to device GND. 9 TA = 25 - 12 - 12 pF Output Capacitance CO VCC = Open, f = 1MHz, all measurements are referenced to device GND. 9 TA = 25 - 12 - 12 pF DIO Valid After RD High t OH 9, 10 -55 ≤ TA ≤ 125 0 - 0 - ns Output Disable Time t OD 9, 10 -55 ≤ TA ≤ 125 - 27 - 27 ns PARAMETER Output Rise Time tr From 0.8V to 2.0V 9, 10 -55 ≤ TA ≤ 125 - 9 - 9 ns Output Fall Time tf From 2.0V to 0.8V 9, 10 -55 ≤ TA ≤ 125 - 9 - 9 ns NOTES: 9. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 10. Loading is as specified in the test load circuit with CL = 40pF. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS METHOD SUBGROUPS Initial Test 100%/5004 - Interim Test 100%/5004 - PDA 100% 1 Final Test 100% 2, 3, 8A, 8B, 10, 11 - 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Samples/5005 1, 7, 9 Group A Groups C and D 6 HSP48410/883 Waveforms t CP t CH t CL CLK t DS t DH t PS t PH DIN0-23 PIN0-9 t DO DIO0-23 t SS t SH START t SH t SS t FL FC FIGURE 1. SYNCHRONOUS DATA AND CONTROL TIMING tLL LD tFS tFH FCT0-2 CLK tLS START FIGURE 2. FUNCTION LOAD TIMING 7 HSP48410/883 Waveforms (Continued) RD t OE t OD DIO0-23 FIGURE 3. SYNCHRONOUS OUTPUT TIMING t WL t WH WR RD t AH t AS IOADD0-9 t WDH t WDS DIO0-23 FIGURE 4. WRITE CYCLE TIMING WR t RL t RH RD t AH t AS IOADD0-9 t OD t RD t OH DIO0-23 FIGURE 5. READ CYCLE TIMING tr tf 2.0V 0.8V FIGURE 6. OUTPUT RISE AND FALL TIMES 8 HSP48410/883 Burn-In Circuits 84 PIN PGA TOP VIEW PIN “A1” ID 11 DIN8 DIN10 DIN11 DIN13 DIN16 DIN17 DIN19 DIN22 DIO23 DIO22 DIO19 10 DIN5 DIN7 DIN9 DIN12 DIN15 DIN21 DIN20 DIN23 DIO21 DIO20 DIO17 9 DIN4 DIN6 DIN14 GND DIN18 DIO18 DIO16 8 DIN2 DIN3 DIO15 DIO14 7 PIN9 DIN0 GND DIO10 DIO12 DIO11 6 VCC DIN1 CLK DIO9 DIO8 DIO13 5 PIN8 PIN7 PIN6 DIO6 DIO7 GND 4 PIN5 PIN4 DINO4 DINO5 3 PIN3 PIN1 DIO1 DIO3 2 PIN2 FC RD FCT2 WR DIO0 DIO2 1 PIN0 START LD FCT1 GND A B C D E 9 FCT0 IOADD9 IOADD8 UWS IOADD6 IOADD3 IOADD0 IOADD5 IOADD7 IOADD4 IOADD2 IOADD1 F G H J K VCC L HSP48410/883 TABLE 5. PGA PIN PIN NAME BURN-IN SIGNAL PGA PIN PIN NAME BURN-IN SIGNAL PGA PIN PIN NAME BURN-IN SIGNAL PGA PIN PIN NAME BURN-IN SIGNAL A1 PIN0 F1 B9 DIN6 F7 E11 DIN16 F2 J5 DIO6 F7 A2 PIN2 F3 B10 DIN7 F8 F1 IOADD5 F6 J6 DIO9 F10 A3 PIN3 F4 B11 DIN10 F11 F2 UWS F11 J7 DIO10 F11 A4 PIN5 F6 C1 LD F11 F3 IOADD9 F10 J10 DIO21 F7 A5 PIN8 F9 C2 RD F1 F9 GND GND J11 DIO23 F9 A6 VCC VCC C5 PIN6 F7 F10 DIN21 F7 K1 IOADD1 F2 A7 PIN9 F10 C6 CLK F0 F11 DIN17 F3 K2 DIO0 F1 A8 DIN2 F3 C7 GND GND G1 IOADD7 F8 K3 DIO1 F2 A9 DIN4 F5 C10 DIN9 F10 G2 IOADD6 F7 K4 DIO4 F5 A10 DIN5 F6 C11 DIN11 F12 G3 IOADD8 F9 K5 DIO7 F8 A11 DIN8 F9 D1 FCT1 F13 G9 DIN18 F4 K6 DIO8 F9 B1 START F10 D2 FCT2 F14 G10 DIN20 F6 K7 DIO12 F13 B2 FC F16 D10 DIN12 F13 G11 DIN19 F5 K8 DIO15 F1 B3 PIN1 F2 D11 DIN13 F14 H1 IOADD4 F5 K9 DIO18 F4 B4 PIN4 F5 E1 GND GND H2 IOADD3 F4 K10 DIO20 F6 B5 PIN7 F8 E2 WR F2 H10 DIN23 F9 K11 DIO22 F8 B6 DIN1 F2 E3 FCT0 F12 H11 DIN22 F8 L1 VCC VCC B7 DIN0 F1 E9 DIN14 F15 J1 IOADD2 F3 L2 DIO2 F3 B8 DIN3 F4 E10 DIN15 F1 J2 IOADD0 F1 L3 DIO3 F4 L4 DIO4 F6 NOTES: 11. V CC/2 (2.7V ±10%) used for outputs only. 12. 47kΩ (±20%) resistor connected to all pins except VCC and GND. 13. V CC = 5.5 ±0.5V. 14. 0.1µF (min) capacitor between VCC and GND per position. 15. FO = 100kHz ±10%, F1 = F0/2, F2 = F1/2 . . . F16 = F15/2, 40% - 60% duty cycle. 16. Input Voltage Limits: VIL = 0.8V max. VIH = 4.5V ±10%. Die Characteristics DIE DIMENSIONS: GLASSIVATION: 330 x 281 x 19 ± 1mils Type: Nitrox Thickness: 10kÅ METALLIZATION: WORST CASE CURRENT DENSITY: Type: Si - Al or Si-Al-Cu Thickness: 8kÅ 0.47 x 105 A/cm 2 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10