LSI/CSI UL ® LS7210 LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405 A3800 PROGRAMMABLE DIGITAL DELAY TIMER February 1998 PIN ASSIGNMENT - TOP VIEW 14 V SS (+V) A 2 13 OUT 3 12 WB0 11 WB1 TRIGGER LS7210 DESCRIPTION: The LS7210 is a monolithic MOS integrated circuit programmable digital timer that can generate a delay in the range of 6ms to infinity. The delay is programmed by 5 binary weighted input bits in combination with the time base provided. The chip can be operated in four different modes: Delayed Operate, Delayed Release, Dual Delay and One Shot. These modes are selected by the control inputs A and B. B 1 LSI FEATURES: • Programmable Delay from 6 ms to "Infinity" • Can be Cascaded for Sequential Events or Extended Delay • +4.75V to +15V Operation (Vss -VDD) • On Chip Oscillator or External Clock time base • High Noise Immunity • LS7210 (DIP), LS7210-S (SOIC)-See Figure 1 CLOCK SELECT 4 OSCILLATOR 5 10 WB2 EXTERNAL CLOCK 6 9 WB3 V DD (-V) 7 8 WB4 FIGURE 1 TABLE 1. WEIGHTING BITS ASSIGNMENTS INPUT/OUTPUT DESCRIPTION: OSCILLATOR Input (Pin 5) The frequency of the internal oscillator is set by an RC network connected to the OSC input, as shown in Figure 2. The nominal oscillator frequency, f, at room temperature is given by f≈1/RC where R values range from a minimum of 47KΩ to a maximum 3MΩ. NOTE: Oscillation accuracy from chip to chip for a fixed value of RC, is + 10%. (Parts can supplied to tighter tolerances.) INPUTS WB0 WB1 WB2 WB3 WB4 VALUE 1 2 4 8 16 Example: For a weighting factor of 25, inputs WB4, WB3, and EXTERNAL CLOCK Input (Pin 6) WB0 should be programmed to logic 0. If the internal oscillator is not used, the chip can be driven by an external clock applied to this input. MODE SELECT Inputs A, B (Pins 2, 1) The chip can be programmed to operate in four different modes CLOCK SELECT Input (Pin 4) by applying the logic levels to inputs A and B as indicated in The internal oscillator or the external clock is selected by the proper Table 2. The mode select inputs are clocked into the input latchlogic level applied to this input. A logic 1 selects the external clock es with the negative edge of the time base clock. These inputs and logic 0 selects the internal oscillator. (See Note 1) should not be changed while a delay timing is in progress. (See Note 1) TRIGGER Input (Pin 3) TABLE 2. MODE SELECTION A positive or a negative transition at the trigger input initiates a delay in turning on or off the output. A negative transition always turns on CONTROL MODE the output with or without delay depending on the selected mode. A A B positive transition at the trigger input always turns off the output (with 1 1 Dual Delay the exception of one-shot mode) with or without delay depending on 1 0 Delayed Release the selected mode. The delay is a function of the time base fre0 1 Delayed Operate quency and the weighting factor programmed at the weighting bit in0 0 One Shot puts. The trigger input is clocked into the input latch with the negative edge of the selected time base clock. All timings begin after the OUT Output (Pin 13) latch has been set up. (See Note 1) The output is an open drain FET. To obtain proper switching of the output between Logic 0 and 1 levels, an external pull down resistor to VDD must be used. If the output is used only as a current WEIGHTING FACTOR Inputs, WB0-WB4 (Pins 12-8) source, no such pull down is needed. The output is logically inA delay from the trigger input to the output is programmed by ap- verted with respect to the trigger input. plying 1's complement binary weighted numbers at these 5 inputs. (See Note 1) The exact equation for the delay is: VSS, VDD (Pins 14, 9) Supply voltage positive, negative terminals. f = Oscillation Frequency Delay = (1 + 1, 023N) NOTE 1: These inputs have internal pullup resistors. f N = Weighting Factor 7210-041700-1 MODE DEFINITION TIMING DIAGRAM: (See Figure 3) DUAL DELAY MODE Thls is the Default Mode when the inputs A and B are left unprogrammed. The function of the Dual Delay mode is to provide a time delay on both the turn-on and turn-off of the output. Once turned on, the output will remain on as long as the trigger input is Logic 0. Once turned off, the output will remain off as long as the trigger input is a logic 1. DELAYED OPERATE MODE This mode causes a retriggerable delay in turning the output on in response to a negative edge at the trigger input. The output is turned off without delay in response to a positive transition at the trigger input. DELAYED RELEASE MODE This mode causes a retriggerable delay in turning off the output whenever there is a positive transition at the trigger input. The output is turned on without delay in response to a negative transition at the trigger input. ONE-SHOT MODE In this mode, the chip functions like a retriggerable monostable multi-vibrator. The output is turned on whenever there is a negative transition at the trigger input. At the end of the programmed delay, the output is turned off automatically. If there is a negative transition at the trigger input before the delay is over, the delay is restarted. A positive transition at the trigger input has no effect on the output in this mode. NOTE: In One-Shot mode, the TRIGGER input must be held at logic 1 during a power-up. ABSOLUTE MAXIMUM RATINGS: (All voltages referenced to VDD) SYMBOL VALUE DC Supply Voltage VSS +18 Voltage (Any Pin) VIN 0 to VSS+.3 Operating Temperature TA -25 to +70 Storage Temperature TSTG -65 to +150 UNIT V V °C °C DC ELECTRICAL CHARACERISTICS: (-25°C ≤TA ≤+70°C unless otherwise specified. All voltages referenced to VDD) PARAMETER Suppy Voltage Supply Current SYMBOL VSS ISS MIN +4.75 - MAX +15.0 3.0 UNIT V mA Trigger Input Logic 1 VTH VSS -1 VSS V - Logic 0 VTL 0 .2VSS V - All Other Inputs Logic 1 VIH .8VSS VSS V - Logic 0 VIL 0 .2VSS V - Io Io Io +1.0 +2.8 +4.2 - mA mA mA Output Source Current for Vo = Vss - 1V SWITCHING CHARACTERISTICS: (See Figure 4) PARAMETER Oscillator Frequency SYMBOL fOSC MIN - CONDITION VSS = +15V, output off VSS = + 5V VSS = +10V VSS = +15V MAX 50 UNIT KHz External Clock Frequency External Clock, Positive Pulse Width External Clock, Negative Pulse Width fext tH tL DC 3 3 160 - KHz µs µs A,B and Trigger Input Set-Up Time tS - 300 ns Time-base Clock to Output Delay (turn-on delay in Delayed Release mode and turn-off delay in Delayed Operate mode) tnd - 1 µs Time-base Clock to Output Delay at the End of Time Out tod - 1.6 µs Time-base Clock to Output Delay (turn-on delay in One- Shot Mode) tsd - 600 ns 7210-020298-2 +V TRIGGER 14 OUT (Dual Delay) V SS +V (C) C OUT (Delayed Release) LS7210 5 OSC R OUT (Delayed Operate) (D) V DD 7 FIGURE 2. LS7210 OSCILLATOR CONNECTION < OUT (One-Shot) (A) (B) (E) FIGURE 3. MODE DEFINITION TIMING DIAGRAM The information included herein is believed to be accurate and reliable. However, LSI Computer Systems, Inc. assumes no responsibilities for inaccuracies, nor for any infringements of patent rights of others which may result from its use. A - Turn-off delay in Dual Delay and Delayed Release mode. B - Turn-on delay in Dual Delay and Delayed Operate mode; one-shot period in One-Shot mode. C - Output remains on in Delayed Release and Dual Delay modes due to negative trigger transition before the turn-off delay is over. D - Output remains off in Delayed Operate mode due to positive trigger transition before the turn-on delay is over. E - One-Shot period extended by re-triggering. Note: ∆ is the programmed delay. tL tH TIME-BASE CLK A ONE-SHOT MODE DELAYED RELEASE MODE B ts TRIGGER t od t nd OUT t sd t od PROGRAMMED TURN-OFF DELAY FIGURE 4. LS7210 TIMING DIAGRAM N o t e 1 . - A,B and Trigger inputs are clocked into the input latches with the negative edge of the time-base clock. N o t e 2 . - In all modes except One-Shot, the output changes with the positive transition of the time-base clock. In One-Shot mode the output is turned on with the negative transition and turned off with the positive transition of the time-base clock. 7210-020298-3 +V CLOCK SELECT EXT CLOCK +V FIGURE 5. LS7210 BLOCK DIAGRAM 4 8 WB4 9 WB3 10 WB2 11 WB1 12 WB0 6 +V CLOCK SELECT LOGIC OSC 5 PRESCALER ÷ 1023 (SEE NOTE) TIMER OUTPUT LATCH +V POR GENERATOR A 2 2 LATCH +V CONTROL LOGIC B 1 LATCH +V TRIGGER LATCH 3 V SS 14 +V V DD 7 -V NOTE: ÷ 1023 is standard. Any number from 1 to 1022 can be mask programmed. FIGURE 6. ASYMMETRICAL FLASHER 1 V SS B 2 A OUT TRIG WB0 68K f 5 OSC 6 LS7210 4 CS .005µF 13 WB1 11 WB2 10 EXT CLK WB3 V DD WB4 7 f = 3.17KHz +V OUT 12 3 +V 14 8.068 s OUT 9 8 323ms 47K NOTE: Inputs A, B in Dual-Delay mode. For symmetical flasher tie Pins 8, 9, 10, 11 & 12 to fixed logic level. 7210-020298-4 +V 13 OUT