SED1190 CMOS LCD 64-COMMON DRIVERS ■ DESCRIPTION The SED1190 is a dot matrix LCD common (row) driver for driving high-capacity LCD panel at duty cycles higher than 1/64. The LSI uses two serially connected, 32-bit shift registers to hold the display data, and level shifter converts the TTL level 64-bit parallel data from the shift registers to levels suitable for use by the LCD drive circuitry. The SED1190 generates common drive signals using the voltages supplied to LCD drive voltages pins. The SED1190 is used in conjunction with the SED1180 (64-bit row driver) to drive a large capacity dot matrix LCD panel. ■ FEATURES • Low-power CMOS technology • 64-bit common (row) driver • Display blanking • Duty cycle: 1/64 to 1/128 • Daisy chain enable support • Wide range of LCD voltage: –14V to –25V • Supply voltage: 5.0V ±10% pin (F • Package: ............................... QFP1-80 QFP5-80 pin (F 0A) 5A) DIE: Al pad chip (D0A) ■ SYSTEM BLOCK DIAGRAM D0 ~ D3 XSCL LCD CONTR LP, FR YSCL YD SED1190 64 SED1180 SED1180 SED1180 SED1180F 64 64 64 64 256SEG × 64 COM DUTY: 1/64 705 SED1190 ■ BLOCK DIAGRAM 0 LAT Latch DI 31 COM LCD Driver 32 bits Level Shifter 32 bits Shift Register 32 bits INH Voltage Control YSCL FR Shift Register 32 bits Level Shifter 32 bits LCD Driver 32 bits DO 5 VSS VDD V2 V3 VSSH 32 63 COM COM63 COM62 COM61 COM60 COM59 COM58 COM57 COM56 COM55 COM54 COM53 COM52 COM51 COM50 COM49 COM48 COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 ■ PIN CONFIGURATION 65 60 55 50 45 70 40 35 SED1190 Index 75 80 1 5 30 10 15 20 25 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 DO VSSH V4 NC NC NC NC V1 VSS VDD NC DI LAT INH FR YSCL 706 COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SED1190 Number Name Number Name Number Name Number Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 COM11 COM10 COM 9 COM 8 COM 7 COM 6 COM 5 COM 4 COM 3 COM 2 COM 1 COM 0 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 COM60 COM61 COM62 COM63 DO VSSH V4 NC NC NC NC V1 VSS VDD NC DI LAT NC = Not connected ■ PIN DESCRIPTION Pin Name Function COM0 to COM63 LCD common drive outputs DI Serial data input Transparent latch control input: LAT LAT H L DI DI latch output H H L L X DI latch DO Serial data output YSCL Serial data shift clock. Data is shifted through the controller on the falling edge of this clock FR LCD AC-drive signal input INH Active-low blanking input VDD, VSS Logic power supply inputs V1, V4, VSSH LCD drive power inputs VDD ≥ V1 ≥ V4 ≥ VSSH 707 INH FR YSCL SED1190 ■ ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings • Parameter Supply voltage (1) Supply voltage (2) Input voltage Symbol Ratings Unit VSS –7.0 to +0.3 V –28.0 to +0.3 V VSS –0.3 to +0.3 V VSSH V1, V4 VI Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +125 °C Soldering temperature and time Tsol 260, 10 °C, s Notes: 1. All voltages referenced to a VDD of 0 V. 2. V1 and V4 must satisfy the relationship VDD ≥ V1, V4 ≥ VSSH 3. Exceeding the absolute maximum ratings can cause permanent damage to the device. Functional operation under these conditions is not implied. 4. Moisture resistance of flat packages can be reduced by the soldering process. Care should be taken to avoid thermally stressing the package during board assembly. 708 SED1190 • DC Characteristics Parameter Supply voltage (1) Supply voltage (2) (VDD = 0V, VSS = –5.0 V ±10%, Ta = –20 to 75°C) Symbol VSS V1 V4 VSSH High level input voltage Low level input voltage High level output voltage Low level output voltage Input leakage current Output leakage current Shift clock Frame signal Input capacitance VIH VIL VOH VOL ILI ILO YSCL FR CI Common output on resistance RCOM Quiescent current Operating current for the logic Conditions IQ ISS Operating current for LCD ISSH Pull up MOS current –Ip Recommended VSSH Operable VSSH (see note) IOH = –0.6 mA IOL = 0.6 mA 0 V ≥ VI ≥ VSS 0 V ≥ VO ≥ VSS Ta = 25°C VSSH = –20.0 V VSSH = –14.0 V VSSH = –9.0 V VSSH = –5.0 V VSSH = –25 V, VSSH = –5.5 V, VI = VDD VOH = VDD –0.5 V VOL = VSSH +0.5 V COM bit SED 1190 VSS = –5.0 V, VIH = VDD, VIL = VSS, YSCL cycle = FR cycle = 16.7 ms 130 µs (duty 50%), All “H” output terminals are opened at every data input all 1/128 duty. VSS = –4.5 V, V1 = –2.0 V, V4 = –18.0 V, YSCL cycle = FR cycle = 16.7 ms 130 µs (duty 50%), All “H” output terminals are opened at every data input of 1/128 duty. VSS = –5.0 V, VIL = –5.0 V Applicable to LAT input terminals Rating Unit Min Typ Max –5.5 –5.0 –4.5 V VSSH — VDD V VSSH — VDD V –25.0 — –14.0 V –25.0 — –5.0 V 0.2VSS — VDD+0.3 V VSS–0.3 — 0.8VSS V –0.4 — — V — — VSS+0.4 V — 0.05 2.0 µA — 0.05 5.0 µA — — 2.5 MHz — 1/60 — s — 5.0 8.0 pF — 0.8 1.0 — 0.9 1.3 kΩ — 1.3 2.0 — 3.0 30.0 — 0.05 30 µA — 3.0 8.0 µA — 3.0 8.0 µA 10.0 25.0 50.0 µA Note: Error free operation is guaranteed in this range but the output resistance of the LCD drivers is higher than in the recommended operating range. It is suggested that the driver is tested with the target LCD panel to determine if performance is acceptable. 709 SED1190 • ° AC Electrical Characteristics I/O Signal Timing FR 0 1 2 3 63 0 1 2 3 63 0 1 0 1 2 3 *63 *0 1 2 3 63 0 1 LAT DI DATA 0 0 1 2 1 2 3 63 3 0 63 1 0 2 1 3 2 3 63 0 63 0 1 1 YSCL 0 DO 1 2 3 63 LAT 1 *0 is the data of COM0 *63 is the data of COM63 tCYL tWLTH 0 tWLTL tDS tST tDH tSTH DI tDS YSCL tDS tCYC tWCLH tDH tWCLL tDFR FR tPD DO VDD = 0V, VSS = –5.0V ± 10%, Ta = –20 to 75°C Parameter Latch pulse cycle time Latch pulse “H” width Latch pulse “L” width Shift clock cycle time Shift clock “H” time Shift clock “L” time Data setup time Data hold time Data shift timing Data shift hold time Permissible frame signal delay Input signal rise time Input signal fall time Data output delay time Symbol tCYL tWLTH tWLL tCYC tWCLH tWCLL tDS tDH tST tSTH tDFR tr tf tpD Conditions — — — — — — — — — — — — — CL = 15pF * tr, tf = (tCYL – tWLH – tWLTL) / 2 where tf ≥ 50ns. 710 Min 400 180 180 400 110 110 (240) 100 (70) 30 0 125 –500 — — 30 Typ — — — — — — — — — — 0 — — — Max — — — — — — — — — — 500 * * 170 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns SED1190 • Common Drive YSCL VIL VIH VIL FR tFRCD tCLCD Vn –0.5V Vn +0.5V COM out VDD ,V1 V1, V4, VSSH tIHCD INH VIH = 0.2 × VSS VIL = 0.8 × VSS VDD = 0V, VSS = –5.0V ± 10%, Ta = –20 to 75°C Parameter YSCL – COM output delay time RF – COM output delay time INH – COM output delay time Symbol tCLCD tFRCD tIHCD Conditions VSSH = –14.0 to –25.0V CL = 100pF 711 Min — — — Typ — — — Max 3.0 3.0 3.0 Unit µs µs µs SED1190 ■ EXAMPLE OF APPLICATION (64 × 640 pixels, 1/64 duty ratio) *2 LP YSCL YD YDIS SED1190 0 LCD PANEL COM 64 × 640 Full Dot Graphic Display VSSH FR YSCL LAT DIN INH 63 0 VSS VDD + R V1 + R V2 VDD, V1, V4, VSS + SEG 0 63 5R SEG 0 63 191 SED1180 SED1180 2 3 EI EO FR LP EO EI FR LP 576 SEG 0 63 1 EI 4 127 128 SED1180 C C + 63 64 C R + R *1 C 100Ω V4 VDD, VSS V2, V3 4 SED1180 10 EO EI FR LP 100Ω 4 4 2 4 2 4 *1 2 4 Notes: 1. Current limiting resistors 2. Bypass VSS and VSSH with capacitors of at least 0.01 µF 712 EO FR LP VSSH FR LP ECL, XSCL D0 to D3 SEG 0 63 V3 + 639 2 4