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IUHTXHQF\ï 7KH FRXQW LV LQFUHPHQWHG HDFK WLPH D ]HUR LV UHFHLYHGñ DQG UHVHW WR ]HUR HDFK WLPH D RQH õPDUNô LV UHFHLYHGï 8SRQ UHFHLSW RI ìæè FRQVHFXWLYH ]HURV WKH /26 SLQ JRHV KLJKñ DQG D VPRRWK WUDQVLWLRQ UHSODFHV WKH 5&/. RXWSXW ZLWK WKH 0&/.ï õ,I 0&/. LV QRW VXSSOLHG WKH 5&/. RXWSXW ZLOO EH UHSODFHG ZLWK WKH FHQWHUHG FU\VWDO FORFNïô 7KH /26 SLQ LV UHVHW ZKHQ WKH UHFHLYHG VLJQDO UHDFKHV ìëïèø RQHV GHQVLW\ õé PDUNV LQ êë ELWVô ZLWK QR PRUH WKDQ ìè FRQVHFXWLYH ]HURVï 5HFRYHUHG FORFN VLJQDOV DUH VXSSOLHG WR WKH -LWWHU $WWHQXDð WRU DQG WKH GDWD ODWFKï 7KH UHFRYHUHG GDWD LV SDVVHG WR WKH (ODVWLF 6WRUH ZKHUH LW LV EXIIHUHG DQG V\QFKURQL]HG ZLWK WKH GHMLWWHUHG UHFRYHUHG FORFN õ5&/.ôï -LWWHU $WWHQXDWLRQ Jitter attenuation of the LXT304A clock and data outputs is provided by a Jitter Attenuation Loop (JAL) and an Elastic Store (ES). An external crystal oscillating at 4 times the bit rate provides clock stabilization. Refer to Application Information for crystal specifications. The ES is a 32 x 2- ëðëè /;7êíé$ /RZð3RZHU 7ìî(ì 6KRUWð+DXO 7UDQVFHLYHU (&6$ VSHFLILFDWLRQV IRU &68 DSSOLFDWLRQVï $ ìãìïìè WUDQVð PLW WUDQVIRUPHU LV XVHG IRU ìïèéé 0ESV V\VWHPVï )RU KLJKHU UHWXUQ ORVV LQ '6;ðì DSSOLFDWLRQVñ XVH äïì Ω UHVLVð WRUV LQ VHULHV ZLWK D ìãëïê WUDQVPLW WUDQVIRUPHUï bit register. Recovered data is clocked into the ES with the recovered clock signal, and clocked out of the ES with the dejittered clock from the JAL. When the bit count in the ES is within two bits of overflowing or underflowing, the ES adjusts the output clock by 1/8 of a bit period. The ES produces an average delay of 16 bits in the receive path. ëïíéå 0ESV SXOVHV FDQ GULYH FRD[LDO RU VKLHOGHG WZLVWHGð SDLU OLQHVï )RU (ì V\VWHPVñ D ìãë WUDQVPLW WUDQVIRUPHU DQG VHULHV UHVLVWRUV DUH UHFRPPHQGHGï 7KLV GHVLJQ PHHWV RU H[FHHGV DOO ,78 DQG (76, VSHFLILFDWLRQV IRU WUDQVPLW DQG UHFHLYH UHWXUQ ORVVï $ ìãì RU ìãìïëç WUDQVIRUPHU PD\ EH XVHG ZLWKRXW VHULHV UHVLVWRUVï 7UDQVPLWWHU 'DWD UHFHLYHG IRU WUDQVPLVVLRQ RQWR WKH OLQH LV FORFNHG VHULð DOO\ LQWR WKH GHYLFH DW 7326 DQG 71(*ï ,QSXW V\QFKURQLð ]DWLRQ LV VXSSOLHG E\ WKH WUDQVPLW FORFN õ7&/.ôï ,I 7&/. LV QRW VXSSOLHG WKH WUDQVPLWWHU UHPDLQV SRZHUHG GRZQñ H[FHSW GXULQJ UHPRWH ORRSEDFNï 5HIHU WR 7HVW 6SHFLILFDð WLRQV IRU PDVWHU DQG WUDQVPLW FORFN WLPLQJ FKDUDFWHULVWLFVï 'ULYHU 3HUIRUPDQFH 0RQLWRU The transceiver incorporates a Driver Performance Monitor (DPM) in parallel with TTIP and TRING at the output transformer. The DPM output goes High upon detection of 63 consecutive zeros. It is reset when a one is detected on the transmit line, or when a reset command is received. 7KH WUDQVPLWWHG SXOVH VKDSH LV GHWHUPLQHG E\ (TXDOL]HU &RQWURO VLJQDOV (&ì WKURXJK (&ê DV VKRZQ LQ 7DEOH ëï (TXDOL]HU &RQWURO VLJQDOV PD\ EH KDUGZLUHG LQ WKH +DUGð ZDUH PRGHñ RU LQSXW DV SDUW RI WKH VHULDO GDWD VWUHDP õ6',ô LQ WKH +RVW PRGHï 6KDSHG SXOVHV DUH DSSOLHG WR WKH $0, OLQH GULYHU IRU WUDQVPLVVLRQ RQWR WKH OLQH DW 77,3 DQG 75,1*ï 7KH OLQH GULYHU SURYLGHV D FRQVWDQW ORZ RXWSXW LPSHGDQFH RI ê Ω õW\SLFDOôï 7KLV ZHOO FRQWUROOHG RXWSXW LPSHGDQFH SURYLGHV H[FHOOHQW UHWXUQ ORVV õ! ìå G%ô ZKHQ XVHG ZLWK H[WHUQDO äïì Ω SUHFLVLRQ UHVLVWRUV õ‘ ìø DFFXð UDF\ô LQ VHULHV ZLWK D WUDQVPLW WUDQVIRUPHU ZLWK D WXUQV UDWLR RI ìãëïê õ‘ ëø DFFXUDF\ôï 6HULHV UHVLVWRUV DOVR SURYLGH LQFUHDVHG VXUJH SURWHFWLRQ DQG UHGXFH VKRUW FLUFXLW FXUUHQW IORZï /LQH &RGH The LXT304A transmits data as a 50% AMI line code as shown in Figure 2. The output driver maintains a constant low output impedance regardless of whether it is driving marks or spaces. 2SHUDWLQJ 0RGHV The LXT304A can be controlled through hard-wired pins (Hardware Mode) or by a microprocessor through a serial interface (Host Mode). The mode of operation is set by the MODE pin logic level. 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VKRZQ LQ 7DEOH éï SET LOOPBACKS OR RESET REMOTE LOCAL TAOS D7(MSB) L1 )XQFWLRQDO 'HVFULSWLRQ 7DEOH èã /;7êíé$ &U\VWDO 6SHFLILFDWLRQV õ([WHUQDOô 3DUDPHWHU )UHTXHQF\ )UHTXHQF\ VWDELOLW\ 7ì çïìæç 0+] ‘ ëí SSP # ëè ƒ& ‘ ëè SSP IURP ðéí ƒ& WR åè ƒ& õ5HI ëè ƒ& UHDGLQJô 3XOODELOLW\ &/ ìì S) WR ìåïæ S)ñ ò∆) ìæè WR ìäè SSP &/ ìåïæ S) WR êé S)ñ ð∆) ìæè WR ìäè SSP (IIHFWLYH VHULHV UHVLVWDQFH éí Ω 0D[LPXP &U\VWDO FXW $7 5HVRQDQFH 3DUDOOHO 0D[LPXP GULYH OHYHO ëïí P: 0RGH RI RSHUDWLRQ )XQGDPHQWDO &U\VWDO KROGHU +&éä õ5ê:ôñ &2 æ S) PD[LPXP &0 ìæ I) W\SLFDO L1 (ì åïìäë 0+] ‘ ëí SSP # ëè ƒ& ‘ ëè SSP IURP ðéí ƒ& WR òåè ƒ& õ5HI ëè ƒ& UHDGLQJô &/ ìì S) WR ìåïæ S)ñ ò∆) äè WR ììè SSP &/ ìåïæ S) WR êé S)ñ ð∆) äè WR ììè SSP êí Ω 0D[LPXP $7 3DUDOOHO ëïí P: )XQGDPHQWDO +&éä õ5ê:ôñ &2 æ S) PD[LPXP &0 ìæ I) W\SLFDO ëðëä /;7êíé$ /RZð3RZHU 7ìî(ì 6KRUWð+DXO 7UDQVFHLYHU IUDPHU SURYLGLQJ WKH GLJLWDO LQWHUIDFH ZLWK WKH KRVW FRQWUROð OHUï %RWK GHYLFHV DUH FRQWUROOHG WKURXJK WKH VHULDO LQWHUIDFHï $Q /;3çíí$ &ORFN $GDSWHU õ&/$'ô SURYLGHV WKH ëïíéå 0+] V\VWHP EDFNSODQH FORFNñ ORFNHG WR WKH UHFRYHUHG ìïèéé 0+] FORFN VLJQDOï 7KH SRZHU VXSSO\ LQSXWV DUH WLHG WR D FRPPRQ EXV ZLWK DSSURSULDWH GHFRXSOLQJ FDSDFLWRUV LQVWDOOHG õçå “) RQ WKH WUDQVPLW VLGHñ ìïí “) DQG íïì “) RQ WKH UHFHLYH VLGHôï $33/,&$7,21 ,1)250$7,21 ìïèéé 0ESV 7ì ,QWHUIDFH $SSOLFDWLRQ )LJXUH é LV D W\SLFDO ìïèéé 0ESV 7ì DSSOLFDWLRQï 7KH /;7êíé$ LV VKRZQ LQ WKH +RVW 0RGH ZLWK D 7ìî(6) )LJXUH éã 7\SLFDO /;7êíé$ ìïèéé 0ESV 7ì $SSOLFDWLRQ õ+RVW 0RGHô òè9 6&/. CS INT 6', 6'2 0RGH 0&/. &RQWURO DQG 0RQLWRU &/.( 0&/. /26 '30 µ3 6HULDO 3RUW &F 75,1* 5W éæíì S) /;7êíé$ 7UDQVPLW /LQH 77,3 07,3 57,3 5U ë&7ãì 79ò 5*1' 59ò ;7$/287 55,1* ;7$/,1 2.048 MHz 5HFHLYH /LQH 5U /;3çíí$ &/., CLKO FSI 7U 5W 05,1* 7*1' )UDPHU 7326 71(* 7&/. 5326 51(* 5&/. NOTE íïì µ) çå µ) ìïí µ) ìï 7\SLFDO YDOXH éæí S)ï $GMXVW IRU DFWXDO ERDUG SDUDVLWLFV WR REWDLQ RSWLð PXP UHWXUQ ORVVï òè9 ëðêí L1 $SSOLFDWLRQ ,QIRUPDWLRQ ëïíéå 0ESV (ì ,QWHUIDFH $SSOLFDWLRQV CRC4 Framer. The hard-wired control lines for TAOS, LLOOP and RLOOP are individually controllable, and the LLOOP and RLOOP lines are also tied to a single control for the Reset function. This configuration is illustrated with a crystal in place to enable the LXT304A Jitter Attenuation Loop, and a single power supply bus. Figure 5 is a 2.048 Mbps E1 TWP application using 15 Ω Rt resistors in line with the transmit transformer to provide high return loss and surge protection. When high return loss is not a critical factor, a 1:1 or 1:1.26 transformer without in-line resistors provides maximum power savings. The LXT304A is shown in Hardware Mode with a typical E1/ )LJXUH èã 7\SLFDO /;7êíé$ (ì ëïíéå 0ESV ìëí Ω $SSOLFDWLRQ õ+DUGZDUH 0RGHô 7$26 5/223 //223 /26 '30 77,3 &F 75,1* 5W õìèΩô 07,3 7326 71(* 7&/. 5326 51(* 5&/. 7UDQVPLW /LQH 7U 05,1* 57,3 5U 5HFHLYH /LQH 5U 5*1' 59ò ;7$/287 55,1* ;7$/,1 1.544 MHz 5W õìèΩô éæíì S) /;7êíé$ /;3çíí$ CLKO &/., FSI /LQH /HQJWK VHWWLQJ ë&7ãì 79ò )UDPHU (&ì EC2 EC2 7*1' &RQWURO DQG 0RQLWRU 0RGH 0&/. NOTE íïì µ) çå µ) ìïí µ) ìï 7\SLFDO YDOXH éæí S)ï $GMXVW IRU DFWXDO ERDUG SDUDVLWLFV WR REWDLQ RSWLð PXP UHWXUQ ORVVï òè9 L1 ëðêì /;7êíé$ /RZð3RZHU 7ìî(ì 6KRUWð+DXO 7UDQVFHLYHU 'é &KDQQHO %DQN $SSOLFDWLRQV Existing D4 Channel Bank architectures frequently employ: (1) a plug-in card for T1 pulse generation (6.0 V peak); and (2) a separate card for pulse shaping and Line Build-Out (LBO). The LXT304A integrates the functions of both cards on a single chip producing a DSX-1 compatible, 3.0 V peak output pulse with a standard transformer. In new designs, the LXT304A can replace two cards with one. However, the LXT304A is also compatible with ex- isting dual-card architectures. With an appropriate output transformer, the LXT304A can produce full 6.0 V peak amplitude pulses suitable for D4 Channel Bank applications with separate pulse shaping/LBO cards. To achieve the 6.0 V peak output, the FCC Part 68-010 Equalizer Code setting is used. (EC = 010.) With the standard 1:1.15 transformer, this code produces a 3.0 V peak pulse. However, doubling the transformer turns ratio to 1:2.30 produces the desired 6.0 V peak pulse. 7DEOH çã 7ìî(ì ,QSXWî2XWSXW &RQILJXUDWLRQV %LW 5DWH õ0ESVô ìïèéé õ7ìô ëïíéå õ(ìô &U\VWDO ;7$/ &DEOH õΩô /;&çìæç ìíí /;&åìäë ìëí æè 5Uë õ Ωô ëíí (&êîëîì íîìîì ð ìîìîì 7UDQVPLW 7UDQVIRUPHUì õ7Uô 5Wë õ Ωô 7\SLFDO 7; 5HWXUQ /RVVê õG%ô &F õµ)ô íîìîíé ìãìïìè ìãë ìãëïê ìãëïê í äïì äïì í íïè ìå ìå íé íïéæ í í íïéæ ëéí íîíîí íîíîí íîíîì íîíîì ìãìïëç ìãë ìãì ìãë í äïì í ìïè íïè ìë íïè ìå íïéæ í íïéæ í ìèí íîíîí íîíîí íîíîì íîíîì ìãì ìãë ìãì ìãë í äïì ìí ìéïê íïè ìå è ìí íïéæ í í í 1. Transformer turns ratio accuracy is ± 2%. 2. Rr and Rt values are ± 1%. 3. Typical return loss, 51 kHz to 3.072 MHz band. 4. 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Includes device and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load. 2. Functionality of pins 23 and 25 depends on mode. See Host/Hardware Mode descriptions. 3. Output drivers will output CMOS logic levels into CMOS loads. 4. Except MTIP and MRING ILL = ± 50 µA. L1 ëðêê /;7êíé$ /RZð3RZHU 7ìî(ì 6KRUWð+DXO 7UDQVFHLYHU 7DEOH äã (OHFWULFDO &KDUDFWHULVWLFV õ8QGHU 5HFRPPHQGHG 2SHUDWLQJ &RQGLWLRQVô ¤ FRQWLQXHG 3DUDPHWHU 6\P 0LQ 0D[ 8QLWV /RZ OHYHO RXWSXW YROWDJHëñê õSLQV çðåñ ììñ ìëñ ëêñ ëèô 92/ ¤ íïé 9 ,// ðìí òìí µ$ ,ê/ ðìí òìí µ$ é ,QSXW OHDNDJH FXUUHQW ë 7KUHHðVWDWH OHDNDJH FXUUHQW õSLQ ëèô 7HVW &RQGLWLRQV ,287 ìïç P$ ìï Power dissipation while driving 75 Ω load over operating temperature range. Includes device and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load. 2. Functionality of pins 23 and 25 depends on mode. See Host/Hardware Mode descriptions. 3. Output drivers will output CMOS logic levels into CMOS loads. 4. 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