CIRRUS CS61535A_09

Jul ’09
CONFIDENTIAL
CS61535A
T1/E1 Line Interface
Features
General Description
•
The CS61535A combines the complete analog transmit
and receive line interface for T1 or E1 applications in a
low power, 28-pin device operating from a +5V supply.
Provides Analog PCM Line Interface
for T1 and E1 Applications
• Provides Line Driver, and Data and
Clock Recovery Functions
• Transmit Side Jitter Attenuation
Starting at 6 Hz, with > 300 UI of Jitter
Tolerance
• Low Power Consumption
•
• B8ZS/HDB3/AMI Encoders/Decoders
• 14 dB of Transmitter Return Loss
• Compatible with SONET, M13 , CCITT
G.742, and Other Asynchronous
Muxes
9
RPOS
[RDATA]
RNEG
[BPV]
AMI,
B8ZS,
HDB3
CODER
Interfacing customer premises equipment to a CSU.
Interfacing to E1 links.
Ordering Information
(CLKE) (INT) (SDI) (SDO)
MODE TAOS LEN0 LEN1 LEN2
5
28
23
24
TGND
25
CONTROL
PULSE
SHAPER
14
TV+
15
LOOP
BACK
26
TRING
LINE DRIVER
LINE RECEIVER
19 RTIP
20 RRING
SIGNAL
QUALITY
MONITOR
27
RLOOP LLOOP
(CS) (SCLK)
Crystal
Semiconductor
Corporation
Cirrus Logic,
Inc.
http://www.cirrus.com
P.O.
Box 17847, Austin, TX 78760
(512) 445-7222 FAX: (512) 445-7581
1
12
ACLKI LOS
TTIP
16
CLOCK &
DATA
RECOVERY
7
6
10
JITTER
ATTENUATOR
3
8
•
•
13
2
4
Interfacing network transmission equipment such as
SONET multiplexor and M13 to a DSX-1 cross connect.
CS61535A-IL1Z
28 Pin PLCC (Lead-free)
CS61535A-IL1 28 Pin PLCC (j-leads)
[ ] = Pin Function in Extended Hardware Mode
( ) = Pin Function in Host Mode
XTALIN XTALOUT
TPOS
[TDATA]
TNEG
[TCODE]
RCLK
The IC uses a digital Delay-Locked-Loop clock and
data recovery circuit which is continuously calibrated
from a crystal reference to provide excellent stability
and jitter tolerance.
Applications
(typically 175 mW)
TCLK
The device features a transmitter jitter attenuator making it ideal for use in asynchronous multiplexor systems
with gapped transmit clocks. The CS61535A provides a
matched, constant impedance output stage to insure
signal quality on mismatched, poorly terminated lines.
DRIVER
MONITOR
21
22
17 MTIP
[RCODE]
18
MRING
[PCS]
11
DPM
[AIS]
RV+ RGND
CopyrightCopyright
¤ Cirrus Logic,
Inc.Semiconductor
2009
© Crystal
Corporation 1996
(All Rights Reserved)
(All Rights Reserved)
MAY
JUL ’96
’09
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CS61535A
ABSOLUTE MAXIMUM RATINGS
Symbol
Min
Max
Units
RV+
6.0
V
TV+
(RV+) + 0.3
V
Input Voltage, Any Pin
(Note 1)
Vin
RGND-0.3
(RV+) + 0.3
V
Input Current, Any Pin
(Note 2)
Iin
-10
10
mA
Ambient Operating Temperature
TA
-40
85
°C
Storage Temperature
Tstg
-65
150
°C
WARNING:Operations at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Notes: 1. Excluding RTIP, RRING, which must stay within -6V to (RV+) + 0.3V.
2. Transient currents of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND
can withstand a continuous current of 100 mA.
DC Supply
Parameter
(referenced to RGND,TGND=0V)
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Units
DC Supply
(Note 3) RV+, TV+
4.75
5.0
5.25
V
Ambient Operating Temperature
TA
-40
25
85
°C
Power Consumption
(Notes 4, 5)
PC
290
350
mW
Power Consumption
(Notes 4, 6)
PC
175
mW
Notes: 3. TV+ must not exceed RV+ by more than 0.3V.
4. Power consumption while driving line load over operating temperature range. Includes IC and load.
Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF load.
5. Assumes 100% ones density and maximum line length at 5.25V.
6. Assumes 50% ones density and 300ft. line length at 5.0V.
2
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CS61535A
DIGITAL CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V)
Parameter
Symbol
Min
Typ
Max
High-Level Input Voltage
2.0
Pins 1-4, 17, 18, 23-28
(Notes 7, 8, 9)
VIH
Low-Level Input Voltage
Pins 1-4, 17, 18, 23-28
(Notes 7, 8, 9)
VIL
0.8
High-Level Output Voltage (IOUT = -40 μA)
4.0
VOH
Pins 6-8, 11, 12, 25
(Notes 7, 8, 10)
Low-Level Output Voltage (IOUT = 1.6 mA)
0.4
Pins 6-8, 11, 12, 23, 25
(Notes 7, 8, 10)
VOL
Input Leakage Current (Except Pin 5)
±10
Low-Level Input Voltage, Pin 5
VIL
0.2
High-Level Input Voltage, Pin 5
VIH
(RV+) - 0.2
Mid-Level Input Voltage, Pin 5
(Note 11)
VIM
2.3
2.7
Notes: 7. This specification guarantees TTL compatibility (VOH = 2.4V @ IOUT = -40μA).
8. In Host Mode, pin 23 is an open drain output and pin 25 is a tristate output.
9. Pins 17 and 18 of the CS61535A are digital inputs in the Extended Hardware Mode.
10. Output drivers will drive CMOS logic levels into a CMOS load.
11. As an alternative to supplying a 2.3-to-2.7V input, this pin may be left floating.
ANALOG SPECIFICATIONS
Parameter
Units
V
V
V
V
μA
V
V
V
(TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V)
Min
Typ
Max
Units
Jitter Attenuator
Jitter Attenuation Curve Corner Frequency
(Note 12)
6
Hz
T1 Jitter Attenuation in Remote Loopback
(Note 13)
Jitter Freq. [Hz]
Amplitude [UIpp]
10
10
3.0
6.0
dB
100
10
20
30
dB
500
10
35
35
dB
1k
5
40
50
dB
10k, 40k
0.3
40
50
dB
E1 Jitter Attenuation in Remote Loopback
(Note 14)
Jitter Freq. [Hz]
Amplitude [UIpp]
10
1.5
3.0
6.0
dB
100
1.5
20
32
dB
400
1.5
30
43
dB
1k
1.5
35
50
dB
10k, 100k
0.2
35
50
dB
Attenuator Input Jitter Tolerance
(Note 15)
12
23
UI
Notes: 12. Not production tested. Parameters guaranteed by design and characterization.
13. Attenuation measured at the demodulator output of an HP3785B with input jitter equal to 3/4 of
measured jitter tolerance using a measurement bandwidth of 1 Hz (10<f<100Hz), 4Hz (100<f<1000
Hz) and 10 Hz (f> 1kHz) centered around the jitter frequency. With a 215-1 PRBS data pattern.
Crystal must meet specifcations in Appendix A.
14. Jitter measured at the demodulator output of an HP3785A using a measurement
bandwidth not to exceed 20 Hz centered around the jitter frequency. With a 215-1 PRBS data pattern.
Crystal must meet specifications in Appendix A.
15. Output jitter increases significantly when attenuator input jitter tolerance is exceeded.
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ANALOG SPECIFICATIONS
CS61535A
(TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V)
Parameter
Min
Typ
Max
Units
Transmitter
AMI Output Pulse Amplitudes
(Note 16)
2.14
2.37
2.6
V
E1, 75 Ω
(Note 17)
2.7
3.0
3.3
V
E1, 120 Ω
(Note 18)
2.7
3.0
3.3
V
T1, FCC Part 68
(Note 19)
2.4
3.0
3.6
V
T1, DSX-1
(Note 20)
E1 Zero (space) level (LEN2/1/0 = 0/0/0)
-0.237
0.237
V
75Ω application
(Note 17)
-0.3
0.3
V
120Ω application
(Note 18)
Recommended Output Load at TTIP and TRING
75
Ω
Jitter Added During Remote Loopback
(Note 21)
0.005
0.02
UI
10Hz - 8kHz
0.008
0.025
UI
8kHz - 40kHz
0.010
0.025
UI
10Hz - 40kHz
0.015
0.05
UI
Broad Band
Power in 2kHz band about 772kHz
(Notes 12, 16)
12.6
15
17.9
dBm
Power in 2kHz band about 1.544MHz
(Notes 12, 16)
-29
-38
dB
(referenced to power in 2kHz band at 772kHz)
Positive to Negative Pulse Imbalance
(Notes 12, 16)
0.2
0.5
dB
T1, DSX-1
-5
5
%
E1 amplitude at center of pulse
-5
5
%
E1 pulse width at 50% of nominal amplitude
Transmitter Return Loss
(Notes 12, 16, 22)
8
dB
51 kHz to 102 kHz
14
dB
102 kHz to 2.048 MHz
10
dB
2.048 MHz to 3.072 MHz
Transmitter Short Circuit Current
(Notes 12, 23)
50
mA RMS
Notes: 16. Using a 0.47 μF capacitor in series with the primary of a transformer recommended
in the Applications Section.
17. Amplitude measured at the transformer (CS61535A-1:1 or 1:1.26) output across a
75 Ω load for line length setting LEN2/1/0 = 0/0/0.
18. Amplitude measured at the transformer (CS61535A-1:1.26) output across a
120 Ω load for line length setting LEN2/1/0 = 0/0/0.
19. Amplitude measured at the transformer (CS61535A-1:1.15) output across a
100 Ω load for line length setting LEN2/1/0 = 0/1/0.
20. Amplitude measured across a 100 Ω load at the DSX-1 cross-connect for line length settings
LEN2/1/0 = 0/1/1, 1/0/0, 1/0/1, 1/1/0 and 1/1/1 after the length of #22 AWG ABAM equivalent cable
specified in Table 3. The CS61535A requires a 1:1.15 transformer.
21. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK.
22. Return loss = 20 log10 ABS((z1 +z0)/(z1-z0)) where z1 = impedance of the transmitter, and
z0 = impedance of line load. Measured with a repeating 1010 data pattern with LEN2/1/0 = 0/0/0
and a 1:1 transformer terminated with a 75Ω load, or a 1:1.26 transformer terminated with a
120Ω load.
23. Measured broadband through a 0.5 Ω resistor across the secondary of a 1:1.26 transformer
during the transmission of an all ones data pattern for LEN2/1/0 = 0/0/0.
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ANALOG SPECIFICATIONS
CS61535A
(TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V)
Parameter
Driver Performance Monitor
MTIP/MRING Sensitivity:
Differential Voltage Required for Detection
Receiver
RTIP/RRING Input Impedance
Sensitivity Below DSX (0dB = 2.4V)
Data Decision Threshold
T1, DSX-1
T1, DSX-1
T1, FCC Part 68 and E1
Data Decision Threshold
(Note 24)
(Note 25)
(Note 26)
T1
E1
Min
Typ
Max
Units
-
0.60
-
V
-13.6
50k
-
-
Ω
dB
60
53
45
160
65
65
50
65
50
175
70
77
55
190
%
%
%
%
%
of peak
of peak
of peak
of peak
of peak
bits
Allowable Consecutive Zeros before LOS
Receiver Input Jitter Tolerance
(Note 27)
0.4
UI
10kHz - 100kHz
6.0
UI
2kHz
300
UI
10Hz and below
Loss of Signal Threshold
(Note 28)
0.25
0.30
0.50
V
Notes: 24. For input amplitude of 1.2 Vpk to 4.14 Vpk.
25. For input amplitude of 0.5 Vpk to 1.2 Vpk and from 4.14 Vpk to RV+.
26. For input amplitude of 1.05 Vpk to 3.3 Vpk.
27. Jitter tolerance increases at lower frequencies. See Figure 11.
28. LOS goes high after 160 to 190 consecutive zeros are received. A zero is output on RPOS and
RNEG (or RDATA) for each bit period where the input signal amplitude remains below the data
decision threshold. The analog input squelch circuit operates when the input signal amplitude above
ground on the RTIP and RRING pins falls within the squelch range long enough for the internal
slicing threshold to decay within this range. Operation of the squelch causes zeros to be output on
RPOS and RNEG as long as the input amplitude remains below 0.25V. During receive LOS, pulses
greater than 0.25V in amplitude may be output on RPOS and RNEG. LOS returns low after the ones
density reaches 12.5% (based upon 175 bit periods starting with a one and containing
less than 100 consecutive zeros) as prescribed in ANSI T1.231-1993.
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CS61535A
T1 SWITCHING CHARACTERISTICS
(TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Crystal Frequency
ACLKI Duty Cycle
ACLKI Frequency
RCLK Duty Cycle
(Note 29)
(Note 30)
(Notes 31, 32)
RCLK Cycle Width
(Note 32)
Symbol
fc
tpwh3/tpw3
faclki
tpwh1/tpw1
tpw1
tpwh1
tpwl1
tr
tf
tsu2
th2
tsu1
tsu1
tsu1
th1
th1
th1
ftclk
tpwh2
Min
40
320
130
100
25
25
150
150
150
150
150
150
80
150
Typ
6.176000
1.544
78
29
648
190
458
274
274
274
274
274
274
1.544
-
Max
60
980
240
850
85
85
500
500
Units
MHz
%
MHz
%
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
Rise Time, All Digital Outputs
(Note 33)
Fall Time, All Digital Outputs
(Note 33)
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
RPOS/RNEG Valid Before RCLK Falling
(Note 34)
RDATA Valid Before RCLK Falling
(Note 35)
RPOS/RNEG Valid Before RCLK Rising
(Note 31)
RPOS/RNEG Valid After RCLK Falling
(Note 34)
RDATA Valid After RCLK Falling
(Note 35)
RPOS/RNEG Valid After RCLK Rising
(Note 31)
TCLK Frequency
TCLK Pulse Width
(Notes 12, 31, 34, 36, 37)
(Notes 35, 36, 37)
Notes: 29. Crystal must meet specifications described in Appendix A.
30. ACLKI provided by an external source or TCLK, but not RCLK.
31. Hardware Mode, or Host Mode (CLKE = 0).
32. RCLK cycle width will vary with extent by which pulses displaced by jitter. Specified under worst case
jitter conditions: 0.4 UI AMI data displacement for T1 and 0.2 UI AMI data displacement for E1.
33. At max load of 1.6 mA and 50 pF.
34. Host Mode (CLKE = 1).
35. Extended Hardware Mode.
36. The maximum TCLK burst rate is 5 MHz and tpw2(min) = 200 ns. The maximum gap size that can
be tolerated on TCLK is 12 VI.
37. The transmitted pulse width does not depend on the TCLK duty cycle.
tpw1
RCLK
t pwl1
RPOS
RNEG
RDATA
BPV
t su1
t pwh1
EXTENDED
HARDWARE
MODE OR
HOST MODE
(CLKE = 1)
t h1
HARDWARE
MODE OR
HOST MODE
(CLKE = 0)
RCLK
Figure 1. Recovered Clock and Data Switching Characteristics
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CS61535A
E1 SWITCHING CHARACTERISTICS
(TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3)
Parameter
Crystal Frequency
ACLKI Duty Cycle
ACLKI Frequency
RCLK Duty Cycle
RCLK Cycle Width
(Note 29)
(Note 30)
(Notes 31, 32)
(Note 32)
RCLK Cycle Width
(Note 32)
Rise Time, All Digital Outputs
(Note 33)
Fall Time, All Digital Outputs
(Note 33)
TPOS/TNEG (TDATA) to TCLK Falling Setup Time
TCLK Falling to TPOS/TNEG (TDATA) Hold Time
RPOS/RNEG Valid Before RCLK Falling
(Note 34)
RDATA Valid Before RCLK Falling
(Note 35)
RPOS/RNEG Valid Before RCLK Rising
(Note 31)
RPOS/RNEG Valid After RCLK Falling
(Note 34)
RDATA Valid After RCLK Falling
(Note 35)
RPOS/RNEG Valid After RCLK Rising
(Note 31)
TCLK Frequency
TCLK Pulse Width
(Notes 31, 34, 36, 37)
(Notes 35, 36, 37)
Symbol
Min
Typ
Max
Units
fc
tpwh3/tpw3
faclki
tpwh1/tpw1
tpw1
tpwh1
tpwl1
tpw1
tpwh1
tpwl1
tr
tf
tsu2
th2
tsu1
tsu1
tsu1
th1
th1
th1
ftclk
tpwh2
40
310
90
120
320
100
25
25
100
100
100
100
100
100
80
150
8.192000
2.048
29
488
140
348
488
348
140
194
194
194
194
194
194
2.048
-
60
670
190
500
670
85
85
340
340
MHz
%
MHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
tr
Any Digital Output
tf
90%
90%
10%
10%
Figure 2. Signal Rise and Fall Characteristics
t pw2
t pwh2
t pw3
TCLK
t su2
TPOS/TNEG
Figure 3a. Transmit Clock and Data Switching
Characteristics
DS40F3
t pwh3
t h2
ACLKI
Figure 3b. Alternate External Clock Characteristics
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SWITCHING CHARACTERISTICS
CS61535A
(TA = -40° to 85°C; TV+, RV+ = ±5%;
Inputs: Logic 0 = 0V, Logic 1 = RV+)
Parameter
Symbol
Min
Typ
Max
SDI to SCLK Setup Time
tdc
50
SCLK to SDI Hold Time
tcdh
50
SCLK Low Time
tcl
240
SCLK High Time
tch
240
SCLK Rise and Fall Time
tr, tf
50
CS to SCLK Setup Time
tcc
50
SCLK to CS Hold Time
(Note 38)
tcch
50
CS Inactive Time
tcwh
250
SCLK to SDO Valid
(Note 39)
tcdv
200
CS to SDO High Z
tcdz
100
Input Valid To PCS Falling Setup Time
tsu4
50
PCS Rising to Input Invalid Hold Time
th4
50
PCS Active Low Time
tpcsl
250
Notes: 38. For CLKE = 0, CS must remain low at least 50 ns after the 16th falling edge of SCLK.
39. Output load capacitance = 50pF.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t cwh
CS
t cc
t cch
t ch
t cl
SCLK
t dc
SDI
t cdh
LSB
CONTROL
t cdh
LSB
BYTE
MSB
DATA
BYTE
Figure 4. Serial Port Write Timing Diagram
8
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CS61535A
CS
t cdz
SCLK
t cdv
SDO
HIGH Z
CLKE = 1
Figure 5. Serial Port Read Timing Diagram
PCS
t su4
LEN0/1/2, TAOS,
RLOOP, LLOOP,
RCODE, TCODE
th4
t pcsl
VALID INPUT DATA
Figure 6. Extended Hardware Mode Parallel Chip Select Timing Diagram
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MODE
EXTENDED
HARDWARE HARDWARE
HOST
MODE-PIN
FLOAT, or
<0.2V
>(RV+) - 0.2V
INPUT LEVEL
2.5V
INDIVIDUAL
CONTROL
SERIAL
INDIVIDUAL
CONTROL
LINES &
CONTROL
μ-PROCESSOR
METHOD
PARALLEL
LINES
PORT
CHIP
SELECT
LINE CODE
AMI,
ENCODER &
NONE
B8ZS,
NONE
DECODER
HDB3
AIS DETECTION
NO
YES
NO
DRIVER
PERFORMYES
NO
YES
ANCE MONITOR
Table 1. Differences in Operating Modes
10
FUNCTION
PIN
3
TRANSMITTER
4
6
7
RECEIVER/DPM
11
17
18
18
23
24
CONTROL
25
26
27
28
HARDWARE
TPOS
TNEG
RNEG
RPOS
DPM
MTIP
MRING
LEN0
LEN1
LEN2
RLOOP
LLOOP
TAOS
MODE
EXTENDED
HARDWARE
TDATA
TCODE
BPV
RDATA
AIS
RCODE
PCS
LEN0
LEN1
LEN2
RLOOP
LLOOP
TAOS
HOST
TPOS
TNEG
RNEG
RPOS
DPM
MTIP
MRING
INT
SDI
SDO
CS
SCLK
CLKE
Table 2. Pin Definitions
DS40F3
-XO¶
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CS61535A
HARDWARE MODE
TAOS
LLOOP
RLOOP
LEN0/1/2
CONTROL
TPOS
TNEG
CS62180B
FRAMER
CIRCUIT
TTIP
JITTER
ATTENUATOR
LINE DRIVER
CS61535A
DRIVER MONITOR
TRING
MRING
MTIP
DPM
RTIP
RPOS
LINE RECEIVER
RNEG
TRANSMIT
TRANSFORMER
RRING
RECEIVE
TRANSFORMER
EXTENDED HARDWARE MODE
TCODE
RCODE
TAOS LLOOP
RLOOP
PCS
LEN0/1/2
CONTROL
TTIP
JITTER
ATTENUATOR
TDATA
AMI
B8ZS,
HDB3,
CODER
HIGH
SPEED
MUX
(e.g., M13)
BPV
TRANSMIT
TRANSFORMER
RTIP
LINE RECEIVER
RRING
RECEIVE
TRANSFORMER
AIS
HOST MODE
μP SERIAL PORT
5
CONTROL
TRING
CS61535A
AIS
DETECT
RDATA
LINE DRIVER
CLKE
CONTROL
TPOS
TNEG
CS62180B
FRAMER
CIRCUIT
TTIP
JITTER
ATTENUATOR
LINE DRIVER
CS61535A
DRIVER MONITOR
TRING
MRING
MTIP
DPM
RTIP
RPOS
RNEG
TRANSMIT
TRANSFORMER
LINE RECEIVER
RRING
RECEIVE
TRANSFORMER
Figure 7. Overview of Operating Modes
DS40F3
11
-XO¶
&21),'(17,$/
LEN2 LEN1 LEN0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
1
0
0
0
0
1
1
0
0
1
OPTION SELECTED
0-133 FEET
133-266 FEET
266-399 FEET
399-533 FEET
533-655 FEET
AT&T CB113
(CS61535A only)
CCITT G.703
FCC Part 68, Option A
ANSI T1.403
APPLICATION
DSX-1
ABAM
(AT&T 600B
or 600C)
REPEATER
2.048 MHz E1
CSU NETWORK
INTERFACE
Table 3. Line Length Selection
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NORMALIZED
AMPLITUDE
1.0
AT&T CB 119
SPECIFICATION
0.5
0
CS61535A
OUTPUT
PULSE SHAPE
-0.5
0
250
750
500
TIME (nanoseconds)
1000
Figure 8. Typical Pulse Shape at DSX-1 Cross Connect
F or c o axi al cab le , For shielded twisted
75Ω
loa d
a nd pair, 120Ω load and
transformer specified transformer specified
in Application Section. in Application Section.
2.37 V
3V
0 ±0.237 V
0 ±0.30 V
244 ns
Nominal peak voltage of a mark (pulse)
Peak voltage of a space (no pulse)
Nominal pulse width
Ratio of the amplitudes of positive and negative
0.95 to 1.05*
pulses at the center of the pulse interval
Ratio of the widths of positive and negative
0.95 to 1.05*
pulses at the nominal half amplitude
* When configured with a 0.47 μF nonpolarized capacitor in series with the TX transformer
primary as shown in Figures A1, A2 and A3.
Table 4. CCITT G.703 Specifications
12
DS40F3
-XO¶
&21),'(17,$/
Percent of
nominal
peak
voltage
CS61535A
0
a) Minimum Attenuation Limit
10
269 ns
120
AT&T 62411
Requirements
110
244 ns
100
194 ns
Attenuation in dB
20
90
80
30
40
b) Maximum
Attenuation
Limit
50
Measured Performance
60
50
1
10
100
1k
10 k
Frequency in Hz
Figure 10. Typical Jitter Attenuation Curve
10
Nominal Pulse
0
-10
-20
219 ns
488 ns
Figure 9 . Mask of the Pulse at the 2048 kbps Interface
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13
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1:2
RTIP
Data
Level
Slicer
RRING
Edge
Detector
Data
Sampling
&
Clock
Extraction
CS61535A
RPOS
RNEG
RCLK
Clock
Phase
Selector
Continuously
Calibrated
Delay Line
ACLKI or
Oscillator in Jitter
Attenuator
Figure 11. Receiver Block Diagram
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SHUIRUPDQFH, the crystal used must meet the
specifications in Appendix A
Transmit All Ones Select
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300
100
28
PEAK
TO
10
PEAK
JITTER
(unit intervals)
1
.4
.1
0
10
100 300 700 1k
10k
100k
JITTER FREQUENCY (Hz)
Figure 12. Input Jitter Tolerance of Receiver
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MODE
(pin 5)
CLKE
(pin 28)
DATA
CLOCK
Clock Edge for
Valid Data
LOW
(<0.2V)
X
RPOS
RNEG
RCLK
RCLK
Rising
Rising
HIGH
(>(V+) - 0.2V)
LOW
RPOS
RNEG
SDO
RCLK
RCLK
SCLK
Rising
Rising
Falling
HIGH
(>(V+) - 0.2V)
HIGH
RPOS
RNEG
SDO
RCLK
RCLK
SCLK
Falling
Falling
Rising
MIDDLE
(2.5V)
X
RDATA
RCLK
Falling
X = Don’t care
Table 5. Data Output/Clock Relationship
Jitter and Recovered Clock
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PLWWHULQS XWVL VWU DQVPLWWHGR QWK HOL QHX QOHVV
7$26LVVHOHFWHGWRFDXVHWKHWUDQVPLVVLRQRIDQ
DOORQHV V LJQDOLQV WHDG5HF HLYHULQS XWVD UHLJ QRUHGZKHQORFDOORRSEDFNLVLQHIIHFW7KHMLWWHU
DWWHQXDWRU LVQR WL QFOXGHGL QWK HOR FDOORR SEDFN
GDWDSD WK6H OHFWLRQR IOR FDOOR RSEDFNRYH UULGHV
WKHFKLS¶VORVVRIVLJQDOUHVSRQVH
Loss of Signal
Remote Loopback
5HFHLYHU ORVVRI VLJQDOLV LQ GLFDWHGXS RQUH FHLY
LQJ FR QVHFXWLYH] HURV$ GLJ LWDOFR XQWHU
FRXQWV UHFHLYHG] HURVE DVHG RQ 5&/.F\ FOHV$
]HURLQSXWLVGHWHUPLQHGHLWKHUZKHQ]HURVDUHUH
16
,QUHPRWHORRSEDFNWKHUHFRYHUHGFORFNDQGGDWD
LQSXWRQ 57,3DQ G55,1*DUH VHQWWKUR XJK WKH
MLWWHUDWWHQXDWRUDQGEDFNRXWRQWKHOLQHYLD77,3
DQG75,1*7KHUHFRYHUHGLQFRPLQJVLJQDOVDUH
DOVRV HQWWR 5&/ .53 26DQ G51( * RU
DS40F3
-XO¶
&21),'(17,$/
5'$7$5H PRWH ORRSEDFNL VV HOHFWHGE \WD NLQJ
SLQKLJKRU5/223PD\EHVHOHFWHGXVLQJWKH
VHULDOLQ WHUIDFH6L PXOWDQHRXVV HOHFWLRQR IOR FDO
DQGUHPRWHORRSEDFNPRGHVLVQRWYDOLGVHH5H
VHW
,QWK H &6$( [WHQGHG +DUGZDUH0RGH UH
PRWHORR SEDFNRFFXU VEHI RUHWKHOLQHFRGH
HQFRGHUGHFRGHULQVXULQJWKDWWKHWUDQVPLWWHGVLJ
QDOP DWFKHVWK HU HFHLYHGV LJQDOHYH QLQ WKH
SUHVHQFHR IUH FHLYHGE LSRODU YLRODWLRQV 7KH UH
FRYHUHGG DWDZLO OD OVRE HGH FRGHGD QGR XWSXWR Q
5'$7$LI5&2'(LVORZ
Driver Performance Monitor
7RDLGLQHDUO\GHWHF WLRQDQ GHD V\LV RODWLRQRI
QRQIXQFWLRQLQJOLQNV WKH+DU GZDUHDQG+ RVW
0RGHVRIWK H&6 $DUHDEOHWRP RQLWRU
WUDQVPLWGU LYH SHUIRUPDQFHDQG UHSRUWZKHQ WKH
GULYHU LVQ RO RQJHUR SHUDWLRQDO 7KLVIHD WXUHFD Q
EHXV HGW RPRQL WRUHL WKHU WKHGH YLFH¶V SHUIRUP
DQFH RUW KH SHUIRUPDQFHRID QHL JKERULQJGUL YHU
7KHGULYHUSHUIRUPDQFHPRQLWRULQGLFDWRULVQ RU
PDOO\DWDORZ]HURORJLFOHYHODQGJRHVWRKLJK
OHYHOXSR QGH WHFWLQJGU LYHUI DLOXUH, QW KH+ RVW
0RGH '30LV DYD LODEOH IURPERW K WKHUHJL VWHU
DQGSLQ
7KHGULYHUSHUIRUPDQFHPRQLWRUFRQVLVWVRIDQDF
WLYLW\GHWHFWRUWKDWPRQLWRUVWKHWUDQVPLWWHGVLJQDO
ZKHQ07,3LVFRQQHFWHGWR77,3DQG05,1*LV
FRQQHFWHGWR 7 5,1*'30ZLO OJRKL JKLIWK H
DEVROXWHGL IIHUHQFHEH WZHHQ07 ,3DQ G05, 1*
GRHVQR WWU DQVLWLRQD ERYHRU EH ORZDW KUHVKROG
OHYHOZLWKLQDWLPHRXWSHULRG
:KHQHYHUPRUHWKDQRQHOLQHLQWHUIDFH,&UHVLGHV
RQWKHVDPHFLUFXLWERDUGWKHHIIHFWLYHQHVVRIWKH
GULYHUSHUIRUPDQFHPRQLWRUFDQEHPD[LPL]HGE\
KDYLQJ HDFK,& PRQL WRU SHUIRUPDQFHRI DQ HLJK
ERULQJGHY LFHUD WKHUWKD QKD YLQJLW P RQLWRULWV
RZQSHUIRUPDQFH
CS61535A
Line Code Encoder/Decoder
,Q([WHQGHG+DUGZDUH0RGHWKUHHOLQHFRGHVDUH
DYDLODEOH$0, % =6DQG +'% 7 KHL QSXWWR
WKHHQFRGHULV7'$7$7KHRXWSXWVIURPWKHGH
FRGHUDUH5' $7$DQG%39 %LSRODU 9 LRODWLRQ
6WUREH7KHHQFRGHUDQGGHFRGHUDUHVHOHFWHGXV
LQJS LQV/ (1/ (1/ (1 7&2'(D QG
5&2'(DVVKRZQLQ7DEOH
TCODE
(Transmit
Encoder
Selection)
RCODE
(Receiver
Decoder
Selection)
LOW
HIGH
LOW
HIGH
LEN 2/1/0
000
010-111
HDB3
B8ZS
Encoder
Encoder
AMI
Encoder
HDB3
B8ZS
Decoder
Decoder
AMI
Decoder
Table 6. Selection of Encoder/Decoder
Alarm Indication Signal
,Q([WHQGHG+DUGZDUH0RGHWKHUHFHLYHUVHWVWKH
RXWSXWS LQ$,6KL JKZKH QOHV V WKDQ ]HURVDUH
GHWHFWHGRXWRIELWSHULRGV$,6UHWXUQVORZ
ZKHQRUPRUH]H URV DUHGHW HFWHGRX W RI ELWV
Parallel Chip Select
,Q([WHQGHG+DUGZDUH0RGH3&6FDQEHXVHGWR
JDWHWKHGLJLWDOFRQWUROLQSXWV7&2'(5&2'(
/(1/ (1/ (15 /223/ /223DQG
7$26, QSXWVDU HDFFHSWHGRQWKHV HSLQVRQO\
ZKHQ3&6LVORZ&KDQJHVLQLQSXWVZLOOLPPHGL
DWHO\FKDQJHWKHRSHUDWLQJV WDWHRIWKHGHYLFH
7KHUHIRUHZKHQF\FOLQJ3&6WRXSGDWHWKHRSHU
DWLQJV WDWHWKH GLJ LWDOFR QWUROLQS XWVV KRXOGE H
VWDEOHIRUWKHHQWLUH3&6ORZSHULRG7KHFRQWURO
LQSXWVDUHLJQRUHGZKHQ3&6LVKLJK
Power On Reset / Reset
8SRQSRZHUXSWKH&6$LVKHOGLQD VWDWLF
VWDWHX QWLOWK HV XSSO\F URVVHVD WKUH VKROGRIDS
DS40F3
17
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CS61535A
CS
SCLK
SDI
R/W
0
0
0
0
1
0
0
D0
D1
D2
D3
D4
D5
Data Input/Output
D6
D0
D1
D2
D6
Address/Command Byte
SDO
D3
D4
D5
D7
D7
Figure 13. Input/Output Timing
SUR[LPDWHO\WKUH H9ROWV: KHQW KLVWK UHVKROGLV
FURVVHGW KH GHYLFHZ LOOGH OD\I RUDE RXW PVW R
DOORZWKHSRZHUVXSSO\WRUHDFKRSHUDWLQJYROWDJH
$IWHUWKLVGHOD\FDOLEUDWLRQRIWKHGHOD\OLQHVXVHG
LQWKH WU DQVPLWDQ GU HFHLYHVHFW LRQVFR PPHQFHV
7KH GHOD\OLQ HVFDQ EHFDO LEUDWHGRQ O\LI DU HIHU
HQFHFORFNLVS UHVHQW7KHU HIHUHQFHFORFNIRUWKH
UHFHLYHULV SURYLGHGE\$ &/.,RU E\WKHFU\VWDO
RVFLOODWRULI$&/.,LVQRW SUHVHQW7KHUHIHUHQFH
FORFNIRUWKHWUDQVPLWWHULVSURYLGHGE\7&/.7KH
LQLWLDOFDOLEUDWLRQVKRXOGWDNHOHVVWKDQPV
,QRSHUDWLRQWKHGHOD\OLQHVDUHFRQWLQXRXVO\FDOL
EUDWHGP DNLQJWK HSH UIRUPDQFHR IW KHG HYLFH
LQGHSHQGHQWRISRZHUVXSSO\RUWHPSHUDWXUHYDUL
DWLRQV7 KHFRQWLQXRXV FDOLEUDWLRQIX QFWLRQ
IRUHJRHVD Q\UH TXLUHPHQW WRUH VHWWK HOLQ HLQW HU
IDFHZKHQLQRSHUDWLRQ+RZHYHUDUHVHWIXQFWLRQ
LVDYDLODEOHZKLFKZLOOFOHDUDOOUHJLVWHUV
,QWKH +DUGZDUHDQG ([WHQGHG+DUGZDUHPRGHVD
UHVHWUHTXHVWLVPDGHE\VLPXOWDQHRXVO\VHWWLQJERWK
5/223DQG//223KLJKIRUDWOHDVWQV5HVHW
ZLOOLQLWLDWHRQWKHI DOOLQJHGJHRIWKHUHV HWUHTXHVW
IDOOLQJHGJHRI5/ 223DQG/ /223,QWKH+RV W
0RGHDUHV HWLVLQLWLDWHG E\VLPXOWDQHRXVO\ZULWLQJ
5/223DQG//223WRWKHUHJLVWHU,QHLWKHUPRGH
DUHVHWZLOOVHWDOOUHJLVWHUVWRDQGVHW/26KLJK
Serial Interface
,QWKH+RVW0RGHSLQVWKURXJKVHUYHDVD
PLFURSURFHVVRUPLFURFRQWUROOHULQWHU IDFH2QH
HLJKWELWUHJLVWHUFDQEHZULWWHQWRYLDWKH6',SLQ
RUUHDGIURPWKH6'2S LQDWWKHFORFNUDWHGHWHU
PLQHGE\6&/ .7 KURXJKWKLV UHJLV WHUDKRV W
FRQWUROOHUFDQEHXVHGWRFRQWURORSHUDWLRQDOFKDU
18
DFWHULVWLFV DQGP RQLWRU GHYLFHVW DWXV7 KHV HULDO
SRUWUHD GZULWHWL PLQJLV LQG HSHQGHQWRI WKHV \V
WHPWUDQVPLWDQGUHFHLYHWLPLQJ
'DWDWUDQVIHUVDUHLQLWLDWHGE\WDNLQJWKHFKLSVH
OHFWL QSXW &6O RZ &6 PXVWLQ LWLDOO\E HK LJK
6&/. PD\E HH LWKHUKL JKR UORZZK HQ &6L Q
LWLDOO\JRH VO RZ$GG UHVVD QGL QSXWGD WDE LWVDUH
FORFNHGLQ RQW KHUL VLQJH GJHRI6&/ .'DWD RQ
6'2 LVYD OLGDQG V WDEOHRQ WKH IDOO LQJHGJ HRI
6&/.ZKHQ&/.(LVORZDQGRQWKHULVLQJHGJH
RI6&/.ZKHQ&/.(LVKLJ K'DWDWUDQVIHUVDUH
WHUPLQDWHGE\ V HWWLQJ &6K LJK &6PD\J RKL JK
QRVRRQHUWKDQQV DIWHUWKHULV LQJHGJHRI WKH
6&/.F \FOHFR UUHVSRQGLQJWR WKH ODV WZULW HELW )RUD VHULDOGD WD UHDG &6PD\JRKLJKDQ\WLPH
WRWHUPLQDWHWKHRXWSXW
)LJXUHV KRZVWKHWLPLQJUHODWLRQVKLSVIRUGD WD
WUDQVIHUVZKHQ&/.( :KHQ&/.( GDWD
RXWSXW IURP WKHVHULDO SRUW6'2 LVY DOLGR QW KH
IDOOLQJHGJHRI6&/.)RU&/.( GDWDELW'
LVKHOGWRWKHIDOOLQJHGJHRIWKHWKFORFNF\FOH
IRU& /.( G DWDEL W' LV K HOGWR WK HUL VLQJ
HGJHRIWK HWKFORFNF\FOH6'2JRHVWRDKL JK
LSB, first bit
0
R/W
1
2
3
4
5
6
ADD0
ADD1
ADD2
ADD3
ADD4
-
Read/Write Select; 0 = write, 1 =
read
LSB of address, Must be 0
Must be 0
Must be 0
Must be 0
Must be 1
Reserved - Must be 0
Table 7. Address/Command Byte
DS40F3
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LPSHGDQFHVWDWHHLWKHUDIWHUELW'LVRXWSXWRUDW
WKHHQGRIWKHKROGSHULRGRIGDWDELW'
$QD GGUHVVFRPPDQGE\W HV KRZQL Q7 DEOH
SUHFHGHV D GDWD UHJLVWHU7 KHI LUVWEL WRI WKH DG
GUHVVFRPPDQGE \WHGH WHUPLQHVZ KHWKHUD U HDG
RUDZU LWHLVU HTXHVWHG7K HQH[WVL[ELW VFRQ WDLQ
WKHDGG UHVV7 KH&6 $ UHVSRQGVWR DGGUHVV
7KHODVWELWLVLJQRUHG
7KHGDWDUHJLVWHUVKRZQLQ7DEOHFDQEHZULW
WHQ WR WKH VHULDOS RUW 'DWDL V LQSXWRQ WK HH LJKW
FORFNF\F OHVL PPHGLDWHO\I ROORZLQJWK HDG GUHVVFRPPDQGE\WH%LWV DQGDU HXV HGWR
FOHDUDQLQW HUUXSWLVVXHGIURPWKH,17SLQZKLFK
RFFXUVLQUHVSRQVHWRDORVVRIVLJQDORUDSUREOHP
ZLWKWKH RXWSXWGUL YHU,I ELWVRUDUHWUX HWKH
FRUUHVSRQGLQJLQWHUUXSWLVVXSSUHVVHG6RLIDORVV
RIVLJQDOLQWHUUXSWLVFOHDUHGE\ZULWLQJDW RELW
WKHLQWHUUXSWZLOOEHUHHQDEOHGE\ZULWLQJDWR
ELW7KLVKROGVIRU'30DVZHOO
LSB: first bit in
CS61535A
0
1
2
3
4
LOS
DPM
LEN0
LEN1
LEN2
Loss of Signal
Driver Performance Monitor
Bit 0 - Line Length Select
Bit 1 - Line Length Select
Bit 2 - Line Lenght Select
Table 9. Output Data Bits 0 - 4
Bits
5 6 7
Status
Reset has occurred or no program input.
TAOS in effect.
LLOOP in effect.
TAOS/LLOOP in effect.
RLOOP in effect
DPM changed state since last "clear DPM"
occured.
LOS changed state since last "clear LOS"
occured.
LOS and DPM have changed state since
last "clear LOS" and "clear DPM".
Table 10. Coding for Serial Output Bits 5, 6, 7
LSB: first bit in
0
1
2
3
4
5
6
MSB: last bit in 7
clr LOS
clr DPM
LEN0
LEN1
LEN2
RLOOP
LLOOP
TAOS
Clear Loss of Signal
Clear Driver Performance Monitor
Bit 0 - Line Length Select
Bit 1 - Line Length Select
Bit 2 - Line Lenght Select
Remote Loopback
Local Loopback
Transmit All Ones Select
Table 8. Input Data Register
:ULWLQJD WRHLWKHU&OHDU / 26RU &OHDU
'30RYHUWKHVHULDOLQWHUIDFHKDVWKUHHHIIHFWV
WKHF XUUHQWL QWHUUXSWRQ WK HVH ULDO LQWHUIDFH
ZLOOEH FOH DUHG 1RWHW KDWVL PSO\U HDGLQJWK H
UHJLVWHUELWVZLOOQRWFOHDUWKHLQWHUUXSW
RXWSXWGDWDELWVD QGZLOOEHUHVHWDV
DSSURSULDWH
:ULWLQJDWRHLWKHU &OHDU/26 RU & OHDU
'30H QDEOHVW KHF RUUHVSRQGLQJL QWHUUXSWI RU
/26RU'30
2XWSXWGDWDIURPWKHVHULDOLQWHUIDFHLVSUHVHQWHG
DVVKRZQLQ7DEOHV DQG%LWV DQG FDQ
EH UHDGW R YHULI\O LQHOH QJWKV HOHFWLRQ %LWV DQGPXV WEHGH FRGHG&RGHV DQG
ELWVDQ G LQ GLFDWH/ 26DQ G' 30V WDWH
FKDQJHV:ULWLQJDWRWKH&OHDU/26DQGRU
&OHDU'30ELWVLQWKHUHJLVWHUDOVRUHVHWVVWDWXV
ELWVDQG
6'2JRHVWRDKL JKLPSHGDQFHVWDWHZKHQQRWLQ
XVH6'2DQG6', PD\EHWLHGWRJHWKHULQDSSOL
FDWLRQVZ KHUHW KH KRVWS URFHVVRU KDV D
ELGLUHFWLRQDO,2SRUW
IXWXUHLQWHUUXSWVIRUW KHFRUUHVSRQGLQJ/26
RU'30ZLOOEHSUHYHQWHGIURPRFFXULQJ
DS40F3
19
-XO¶
&21),'(17,$/
CS61535A
Power Supply
7KHGHYLFHRSHUDWHVIURPDVLQJOH9ROWVXSSO\
6HSDUDWHSL QVI RUWU DQVPLWDQ GU HFHLYHV XSSOLHV
SURYLGHLQ WHUQDOL VRODWLRQ7 KHVHSL QV VKRXOG EH
FRQQHFWHGH[W HUQDOO\ QHDUWK HGHY LFH DQG GHFRX
SOHG WR WKHLUUH VSHFWLYHJUR XQGV7 9 PXVWQR W
H[FHHG59E\PRUHWKDQ9
'HFRXSOLQJDQGILOWHULQJRIWKHSRZHUVXSSOLHVLV
FUXFLDOIRUWKH SURSHURSHUDWLRQRIWKH DQDORJFLU
FXLWVLQERWKWKHWUDQVPLWDQGUHFHLYHSDWKV$
μ) FDSDFLWRU VKRXOGE HF RQQHFWHG EHWZHHQ7 9
DQG7*1'DQGDμ)FDSDFLWRUVKRXOGEHFRQ
QHFWHGEHW ZHHQ 59DQG 5*1'8VHP \ODURU
FHUDPLFF DSDFLWRUVDQG SOD FHW KHPDV FOR VHO\DV
SRVVLEOHWRWKHLUUHVSHFWLYHSRZHUVXSSO\SLQV$
μ)WD QWDOXPFD SDFLWRU VKRXOG EHDGG HGFO RVH
WRW KH5 95*1'V XSSO\: LUHZU DSEU HDG
ERDUGLQJRIWKHOLQHLQWHUIDFHLVQRWUHFRPPHQGHG
EHFDXVHO HDGU HVLVWDQFHD QG LQGXFWDQFHV HUYHW R
GHIHDWWKHIXQFWLRQRIWKHGHFRXSOLQJFDSDFLWRUV
20
Schematic & Layout Review Service
Confirm Optimum
Schematic & Layout
Before Building Your Board.
For Our Free Review Service
Call Applications Engineering.
C a l l : ( 5 1 2 ) 4 4 5 - 7 2 2 2
DS40F3
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&21),'(17,$/
CS61535A
PIN DESCRIPTIONS
Hardware Mode
ACLKI
TAOS
+DUGZDUH0RGH3LQRXW
1
28
TCLK 2
LLOOP
27
TPOS 3
RLOOP
26
TNEG 4
LEN2
25
MODE 5
LEN1
24
RNEG 6
LEN0
23
RPOS 7
RGND
22
RCLK 8
RV+
21
XTALIN 9
RRING
20
XTALOUT 10
RTIP
19
18
DPM 11
MRING
17
LOS 12
MTIP
16
TTIP 13
TRING
15
TGND 14
TV+
ACLKI
TCLK
TAOS
TPOS
LLOOP
TNEG
RLOOP
MODE
LEN2
RNEG
RPOS
RCLK
XTALIN
XTALOUT
5
4
3
2
1
28 27 26 25
24
6
23
7
8
top
view
22
9
21
10
20
19
11
LEN1
LEN0
RGND
RV+
RRING
12 13 14 15 16 17 18
DPM
RTIP
LOS
MRING
TTIP
MTIP
TGND
TRING
TV+
DS40F3
21
-XO¶
&21),'(17,$/
CS61535A
Extended Hardware Mode
([WHQGHG+DUGZDUH0RGH3LQRXW
ACLKI
TCLK
TDATA
TCODE
MODE
BPV
RDATA
RCLK
XTALIN
XTALOUT
AIS
LOS
TTIP
TGND
1
28
2
27
3
26
4
25
5
24
6
23
7
22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
TAOS
LLOOP
RLOOP
LEN2
LEN1
LEN0
RGND
RV+
RRING
RTIP
PCS
RCODE
TRING
TV+
ACLKI
TCLK
TAOS
TDATA
LLOOP
TCODE
RLOOP
MODE
BPV
RDATA
RCLK
XTALIN
XTALOUT
LEN2
5
4
3
2
1
28 27 26 25
24
6
23
7
8
top
view
22
9
21
10
20
19
11
LEN1
LEN0
RGND
RV+
RRING
12 13 14 15 16 17 18
AIS
RTIP
LOS
PCS
TTIP
RCODE
TGND
TRING
TV+
22
DS40F3
-XO¶
&21),'(17,$/
CS61535A
Host Mode
ACLKI
CLKE
+RVW0RGH3LQRXW
1
28
TCLK 2
SCLK
27
TPOS 3
CS
26
TNEG 4
SDO
25
MODE 5
SDI
24
RNEG 6
INT
23
RPOS 7
RGND
22
RCLK 8
RV+
21
XTALIN 9
RRING
20
XTALOUT 10
RTIP
19
18
DPM 11
MRING
17
LOS 12
MTIP
16
TTIP 13
TRING
15
TGND 14
TV+
ACLKI
TCLK
CLKE
TPOS
SCLK
TNEG
CS
MODE
SDO
RNEG
RPOS
RCLK
XTALIN
XTALOUT
5
4
3
2
1
28 27 26 25
24
6
23
7
8
top
view
22
9
21
10
20
19
11
SDI
INT
RGND
RV+
RRING
12 13 14 15 16 17 18
DPM
RTIP
LOS
MRING
TTIP
MTIP
TGND
TRING
TV+
DS40F3
23
-XO¶
&21),'(17,$/
CS61535A
Power Supplies
RGND - Ground, Pin 22.
3RZHUVXSSO\JURXQGIRUDOOVXEFLUFXLWVH[FHSWWKHWUDQVPLWGULYHUW\SLFDOO\9ROWV
RV+ - Power Supply, Pin 21.
3RZHUVXSSO\IRUDOOVXEFLUFXLWVH[FHSWWKHWUDQVPLWGULYHUW\SLFDOO\9ROWV
TGND - Ground, Transmit Driver, Pin 14.
3RZHUVXSSO\JURXQGIRUWKHWUDQVPLWGULYHUW\SLFDOO\9ROWV
TV+ - Power Supply, Transmit Driver, Pin 15.
3RZHUVXSSO\IRUWKHWUDQVPLWGULYHUW\SLFDOO\9ROWV79PXVWQRWH[FHHG59E\PRUHWKDQ
9
Oscillator
XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10.
$0+]RU0+]FU\VWDOVKRXOGEHFRQQHFWHGDFURVVWKHVHSLQV,ID0+]RU
0+]FO RFNLVSURYLGHGRQ$&/.,SLQWKHMLWWHUDWWHQXDWRUPD\EH GLVDEOHGE\W\LQJ
;7$/,13LQWR59WKURXJKDNΩUHVLVWRUDQGIORDWLQJ;7$/2873LQ
2YHUGULYLQJWKHRVFLOODWRUZLWKDQH[WHUQDOFORFNLVQRWVXSSRUWHG See Appendix A for crystal
specifications.
Control
ACLKI - Alternate External Clock Input, Pin 1.
7KH&6$GRHVQRWUHTXLUHDFORFNVLJQDOWREHLQSXWRQ$&/.,ZKHQDFU\VWDOLVFRQQHFWHG
EHWZHHQS LQV DQ G ,ID FOR FNL VQ RWS URYLGHGRQ$& /.,WK LVLQS XWPXV WE HJUR XQGHG,I
$&/.,LVJURXQGHGWKHRVFLOODWRULQWKHMLWWHUDWWHQXDWRULVXVHGWRFDOLEUDWHWKHFORFNUHFRYHU\
FLUFXLWDQG7$26LVQRWDYDLODEOH
CLKE - Clock Edge, Pin 28. (Host Mode)
6HWWLQJ&/.(WRORJ LF FDXVHV5326DQG51(*WREHYDO LGRQWKH IDOOLQJHGJHRI5&/.DQG
6'2WREHYDOLGRQWKHULVLQJHGJHRI6&/.&RQYHUVHO\VHWWLQJ&/.(WRORJLFFDXVHV5326
DQG51(*WREHYDO LGRQWKH ULVLQJHGJHRI5&/.DQG6'2WREHYDO LGRQ WKHIDOOLQJHGJHRI
6&/.
CS - Chip Select, Pin 26. (Host Mode)
7KLVSLQPXVWWUDQVLWLRQIURPKLJKWRORZWRUHDGRUZULWHWKHVHULDOSRUW
INT - Receive Alarm Interrupt, Pin 23. (Host Mode)
*RHVORZZKHQ/26RU'30FKD QJHVWDWHWRIODJWKHKRVWSURFHVVRU,17LVFOHDUHGE\ZULWLQJ
&OHDU/26RU&OHDU'30WRWKHUHJLVWHU,17LVDQR SHQGUDLQRXWSXWDQGVKRXOGEHWLHGWR
WKHSRZHUVXSSO\WKURXJKDUHVLVWRU
24
DS40F3
-XO¶
&21),'(17,$/
CS61535A
LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended
Hardware Modes)
'HWHUPLQHVWKHVKDSHDQGDPSOLWXGHRIWKHWUDQVPLWWHGSXOVHWRDFFRPPRGDWHVHYHUDOFDEOHW\SHV
DQGOHQ JWKV6HH7 DEOHIRULQIR UPDWLRQRQOLQ H OHQJWKV HOHFWLRQ $OVRFRQ WUROVWKH UHFHLYHU
VOLFLQJOHYHODQGWKHOLQHFRGHLQ([WHQGHG+DUGZDUH0RGH
LLOOP - Local Loopback, Pin 27. (Hardware and Extended Hardware Modes)
6HWWLQJ//223WRD ORJLFURXWHVWKHWUDQVPLWFORFNDQGGDWDWKURXJKWRW KHUHFHLYHFORFNDQG
GDWDSLQV732671(*RU7'$7$DUHVWLOOWUDQVPLWWHGXQOHVVRYHUULGGHQE\D7$26UHTXHVW
,QSXWVRQ57,3DQG55,1*DUHLJQRUHG
MODE - Mode Select, Pin 5.
'ULYLQJW KH 02'(S LQ KLJKS XWVW KH &6$OL QH LQWHUIDFHL QW KH +RVW0R GH,Q WK HK RVW
PRGHDVHULDOFRQWUROSRUWLVXVHGWRFRQWUROWKH&6$OLQHLQWHUIDFHDQGGHWHUPLQHLWVVWDWXV
*URXQGLQJWKH 02 '(SLQ SXW VWKH &6 $OL QHL QWHUIDFHLQ WKH +D UGZDUH0 RGHZ KHUH
FRQILJXUDWLRQDQGVWDWXVDUHFRQWUROOHGE\GLVFUHWHSLQV)ORDWLQJWKH02'(SLQRUGULYLQJLWWR
9 SX WVWK H& 6$ LQ ([WHQGHG+DU GZDUH0R GHZKH UHFR QILJXUDWLRQDQG VW DWXVD UH
FRQWUROOHGE\GL VFUHWHSLQV:KHQIORD WLQJ02'(WKH UHVKRXOGEHQRH[W HUQDOORDGRQWKHSLQ
02'(GHILQHVWKHVWDWXVRISLQVVHH7DEOH
PCS - Parallel Chip Select, Pin 18. (Extended Hardware Mode)
6HWWLQJ 3&6K LJKFDX VHVW KH& 6$O LQHLQW HUIDFHWR LJQ RUHW KH 7&2'( 5&2'(/ (1
/(1/(15/223//223DQG7$26LQSXWV
RCODE - Receiver Decoder Select, Pin 17. (Extended Hardware Mode)
6HWWLQJ 5&2'(O RZHQ DEOHV%= 6RU+'% ]H URV XEVWLWXWLRQLQW KHUHF HLYHUGHF RGHU6HW WLQJ
5&2'(KLJKHQDEOHVWKH$0,UHFHLYHUGHFRGHUVHH7DEOH
RLOOP - Remote Loopback, Pin 26. (Hardware and Extended Hardware Modes)
6HWWLQJ5/ 223WRDOR JLF FDXVHVWKH UHFRYHUHG FORFNDQG GDWDWREHV HQWWKUR XJK WKH MLWWHU
DWWHQXDWRULIDFWLYHDQGWKURXJKWKHGULYHUEDFNWRWKHOLQH7KHUHFRYHUHGVLJQDOLVDOVRVHQWWR
5&/.DQG532651(*RU5'$7$$Q\7$26UHTXHVWLVLJQRUHG
6LPXOWDQHRXVO\WDNLQJ5/223DQG//223KLJKIRUDWOHDVWQVLQLWLDWHVDGHYLFHUHVHW
SCLK - Serial Clock, Pin 27. (Host Mode)
&ORFNXVHGWRUHDGRUZULWHWKHVHULDOSRUWUHJLVWHUV6&/.FDQEHHLWKHUKLJKRUORZZKHQWKHOLQH
LQWHUIDFHLVVHOHFWHGXVLQJWKH&6SLQ
SDI - Serial Data Input, Pin 24. (Host Mode)
'DWDIRUWKHRQFKLSUHJLVWHU6DPSOHGRQWKHULVLQJHGJHRI6&/.
SDO - Serial Data Output, Pin 25. (Host Mode)
6WDWXVDQ GFR QWUROLQIR UPDWLRQIURP WKHRQ FKLSUHJL VWHU,I&/ .(LVKL JK6'2LV YDOLGRQWK H
ULVLQJHGJHRI6&/.,I&/.(LVORZ6'2LVYDOLGRQWKHIDOOLQJHGJHRI6&/.7KLVSLQJRHVWR
DKLJKLPSHGDQFHVWDWHZKHQWKHVHULDOSRUWLVEHLQJZULWWHQWRRUDIWHUELW'LVRXWSXW
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25
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CS61535A
TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes)
6HWWLQJ7$26WRDORJLFFDXVHVFRQWLQXRXVRQHVWREHWUDQVPLWWHGDWWKHIUHTXHQF\GHWHUPLQHG
E\$&/.,
TCODE - Transmitter Encoder Select, Pin 4. (Extended Hardware Mode)
6HWWLQJ7&2'(ORZHQDEOHV%=6RU+'%]H URVXEVWLWXWLRQLQWKH WUDQVPLWWHUHQFRGHU6HWWLQJ
7&2'(KLJKHQDEOHVWKH$0,WUDQVPLWWHUHQFRGHU
Data
RCLK - Recovered Clock, Pin 8.
7KHUHFHLYHUUHFRYHUHGFORFNLVRXWSXWRQWKLVSLQ
RDATA - Receive Data - Pin 7. (Extended Hardware Mode)
'DWDUHFRYHUHGIURPWKH57,3DQG55,1*LQSXWVLVRXWSXWDWWKLVSLQDIWHUEHLQJGHFRGHGE\WKH
OLQHFRGHGHFRGHU5'$7$LV15=5'$7$LVVWDEOHDQGYDOLGRQWKHIDOOLQJHGJHRI5&/.
RPOS, RNEG - Receive Positive Data, Receive Negative Data, Pins 6 and 7. (Hardware and
Host Modes)
7KHUHFHLYHUUHFRYHUHG15=GLJLWDOGDWDLVRXWSXWRQWKHVHSLQV,QWKH+DUGZDUH0RGH5326
DQG51(*DUHVWDEOHDQGYDOLGRQWKHULVLQJHGJHRI5&/.,QWKH+RVW0RGH&/.(GHWHUPLQHV
WKHFOR FNHG JHIRUZKL FK5326DQ G51( *DUHVWDEOHDQG YDOLG6HH7DEOH$SRV LWLYHSXOVH
ZLWKUHV SHFWW RJURX QGUHF HLYHGRQ WKH57,3SLQ JHQHUDWHVDOR JLFRQ5326 DQGDSR VLWLYH
SXOVHUHFHLYHGRQWKH55,1*SLQJHQHUDWHVDORJLFRQ51(*
RTIP, RRING - Receive Tip, Receive Ring, Pins 19 and 20.
7KH $0,UHF HLYHV LJQDOLV L QSXWW RW KHVH SLQV$ FHQWHUWDSSHGFH QWHUJURXQGHG VWHSXS
WUDQVIRUPHULVUHTXLUHGRQWKHVHLQSXWVDVVKRZQLQ)LJ XUH$LQ WKHApplicationsVHFWLRQ'DWD
DQGFORFNDUHUHFRYHUHGDQGRXWSXWRQ5&/.DQG532651(*RU5'$7$
TCLK - Transmit Clock, Pin 2.
7KH0+]RU0+]WUDQVPLWFORFNLVLQSXWRQWKLVSLQ732671(*RU7 '$7$DUH
VDPSOHGRQWKHIDOOLQJHGJHRI7&/.
TDATA - Transmit Data, Pin 3. (Extended Hardware Mode)
7UDQVPLWWHU15=LQSXWGDWDZKLFKSDVVHVWKURXJKWKHOLQHFRGHHQFRGHUDQGLVWKHQGULYHQRQWR
WKHOLQHWKURXJK77,3DQG75,1*7'$7$LVVDPSOHGRQWKHIDOOLQJHGJHRI7&/.
TPOS, TNEG - Transmit Positive Data, Transmit Negative Data, Pins 3 and 4. (Hardware and
Host Modes)
,QSXWVIRUFORFNDQGGDWDWREHWUDQVPLWWHG7KHVLJQDOLVGULYHQRQW RWKHOLQHWKURXJK77,3DQG
75,1*7 326D QG 71(*D UHV DPSOHG RQ WKHIDO OLQJH GJHRI 7&/.$ 7326 LQSXW FDXVHV D
SRVLWLYHSXOVHWREHWUDQVPLWWHGZKLOHD71(*LQSXWFDXVHVDQHJDWLYHSXOVHWREHWUDQVPLWWHG
TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13 and 16.
7KH$0,VLJQDOLVGULYHQWRWKHOLQHWKURXJKWKHVHSLQV,QWKH&6$WKLVRXWSXWLVGHVLJQHG
WRGULYHDΩORDG$RUWUDQVIRUPHULVUHTXLUHGDVVKRZQLQ)LJXUH$
26
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Status
AIS - Alarm Indication Signal, Pin 11. (Extended Hardware Mode)
$,6J RHVK LJKZK HQX QIUDPHGD OORQHVF RQGLWLRQE OXHD ODUPL VG HWHFWHGX VLQJ WKHG HWHFWLRQ
FULWHULDRIOHVVWKDQWKUHH]HURVRXWRIELWSHULRGV
BPV- Bipolar Violation Strobe, Pin 6. (Extended Hardware Mode)
%39VWUREHVKLJKZKHQDELSRODUYLRODWLRQLVGHWHFWHGLQWKHUHFHLYHGVLJQDO %=6RU+'%
]HURVXEVWLWXWLRQVDUHQRWIODJJHGDVELSRODUYLRODWLRQVLIWKH%=6RU+'%GHFRGHUKDVEHHQ
HQDEOHG
DPM - Driver Performance Monitor, Pin 11. (Hardware and Host Modes)
'30JRHVKLJKLIQRDFWLYLW\LVGHWHFWHGRQ07,3DQG05,1*
LOS - Loss of Signal, Pin 12.
/26JRHVKLJKZKHQFRQVHFXWLYH]HURVKDYHEHHQUHFHLYHG)RUWKH&6$/26UHWXUQV
ORZZ KHQWKH RQH VG HQVLW\U HDFKHV EDVHGX SRQ ELW SHULRGVVWDUWLQJZ LWKDRQHDQ G
FRQWDLQLQJOHVVWKDQFRQVHFXWLYH]HURVDVSUHVFULEHGE\$16,7
MTIP, MRING - Monitor Tip, Monitor Ring, Pins 17 and 18. (Hardware and Host Modes)
7KHVHSLQVDUHQRUPDOO\FRQQHFWHGWR77,3DQG75,1*DQGPRQLWRUWKHRXWSXWRID&6$
,IWKH,17SLQLQWKHKRVWPRGHLVXVHGDQGWKHPRQLWRULVQRWXVHGZULWLQJ&OHDU'30WRWKH
VHULDOLQWHUIDFHZLOOSUHYHQWDQLQWHUUXSWIURPWKHGULYHUSHUIRUPDQFHPRQLWRU
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MILLIMETERS
INCHES
DIM MIN NOM MAX MIN NOM MAX
3.94 4.32 5.08 0.155 0.170 0.200
A
A1 0.51 0.76 1.02 0.020 0.030 0.040
B
0.36 0.46 0.56 0.014 0.018 0.022
B1 1.02 1.27 1.65 0.040 0.050 0.065
0.20 0.25 0.38 0.008 0.010 0.015
C
36.45 36.83 37.21 1.435 1.450 1.465
D
E1 13.72 13.97 14.22 0.540 0.550 0.560
e1 2.41 2.54 2.67 0.095 0.100 0.105
eA 15.24
15.87 0.600
0.625
L
3.18
0.150
3.81 0.125
0°
15°
15°
0°
∝
15
28
28 pin
Plastic DIP
E1
1
14
D
A
SEATING
PLANE
B1
A1
L
∝
e1
B
CS61535A
C
eA
NOTES:
1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN
0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN
RELATION TO SEATING PLANE AND EACH OTHER.
2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL.
3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.
28-pin PLCC
28
E1 E
DIM
MILLIMETERS
INCHES
MIN NOM MAX
MIN NOM MAX
A
4.20
4.45
4.57 0.165 0.175 0.180
A1
2.29
2.79
3.04 0.090 0.110 0.120
B
0.33
0.41
0.53 0.013 0.016 0.021
D/E 12.32 12.45 12.57 0.485 0.490 0.495
D1
D1/E1 11.43 11.51 11.58 0.450 0.453 0.456
D
D2/E2 9.91 10.41 10.92 0.390 0.410 0.430
e
B
1.19
1.27
1.35 0.047 0.050 0.053
e
A1
A
D2/E2
28
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CS61535A
APPLICATIONS
+5V
+
68 μF
RGND
28
Control
&
Monitor
1
12
11
+
0.1 μF
21
RV+
CLKE
1.0 μF
TGND
15
TV+
SCLK
ACLKI
CS
LOS
INT
DPM
SDI
SDO
RV+
5
Frame
Format
Encoder/
Decoder
RPOS
6
RNEG
8
RCLK
3
4
2
9
XTL
MODE
7
10
DEVICE
CS61535A
CS61535A
IN
HOST
MODE
TPOS
RTIP
XTALOUT
RGND
22
26
μP
Serial
Port
23
24
25
CT 2:1
19
20
MTIP
17
MRING
18
TGND
14
FREQUENCY
MHz
1.544
2.048
2.048
27
RRING
TRING
XTALIN
100 kΩ
R1
TNEG
TCLK
+5V
TTIP
CABLE
Ω
100
120
75
16
R2
RECEIVE
LINE
0.47 μF
TRANSMIT
LINE
13
R1&2
Ω
200
240
150
Transmit
Transformer
1:1.15
1:1.26
1:1
Figure A1. Host Mode Configuration
Line Interface
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IRUL QWHUIDFLQJW KH, &WR DOLQHWKURXJKWUD QVPLW
DQGUHFHLYHWUDQVIRUPHUV
7KHU HFHLYHUWU DQVIRUPHUL VFHQ WHUW DSSHGD QG
FHQWHUJURXQGHGZLWKUHVLVWRUVEHWZHHQWKHFHQWHU
WDSDQGHDFKOHJRQWKH,&VLGH7KHVHUHVLVWRUV
SURYLGHWKHWHUPLQDWLRQIRUWKHOLQH
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FRUHRIWK HWUDQVIRUPHUGXHWRDQ\'&LPEDODQFH
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IRUPHUD' &RI IVHWZ LOOU HVXOWGX ULQJW KH
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ULXP7 KHEOR FNLQJF DSDFLWRUZL OON HHS' &
FXUUHQWIURPIORZLQJLQWKHWUDQVIRUPHU
Selecting an Oscillator Crystal
6SHFLILFFU \VWDOS DUDPHWHUVDU HU HTXLUHGI RU
SURSHURSH UDWLRQRIWK H&6 $ Refer to
29
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CS61535A
+5V
+
68 μF
RGND
Control
&
Monitor
Frame
Format
Encoder/
Decoder
28
TAOS
1
ACLKI
21
RV+
1.0 μF
TGND
15
TV+
26
RLOOP
LEN0
23
27
LLOOP
LEN1
24
12
LOS
LEN2
25
11
DPM
RTIP
19
5
MODE
7
RPOS
6
RNEG
8
RCLK
3
4
2
9
XTL
+
0.1 μF
10
CS61535A
IN
HARDWARE
MODE
20
TPOS
MTIP
17
TNEG
MRING
18
TCLK
TRING
16
TTIP
13
XTALIN
RGND
22
CT 2:1
R1
RRING
XTALOUT
Line
Length
Setting
RECEIVE
LINE
R2
0.47 μF
TRANSMIT
LINE
TGND
14
Figure A2. Hardware Mode Configuration
+5V
+
68 μF
RGND
Control
&
Monitor
Frame
Format
Encoder/
Decoder
17
RCODE
18
PCS
6
21
RV+
1.0 μF
TGND
15
TV+
BPV
LEN0
23
28
TAOS
LEN1
24
1
ACLKI
LEN2
25
RTIP
19
26
RLOOP
27
LLOOP
12
LOS
11
AIS
5
MODE
4
TCODE
7
RDATA
8
RCLK
3
TDATA
2
9
XTL
+
0.1 μF
10
CS61535A
IN
EXTENDED
HARDWARE
MODE
TCLK
RGND
22
CT 2:1
R1
RRING
20
TRING
16
TTIP
13
XTALIN
XTALOUT
Line
Length
Setting
R2
RECEIVE
LINE
0.47 μF
TRANSMIT
LINE
TGND
14
Figure A3. Extended Hardware Mode Configuration
30
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Appendix A for crystal specifications
Interfacing The CS61535A With the CS62180B
T1 Transceiver
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YLFHVD VV KRZQL Q) LJXUH$ ,Q WKL VFDV HWKH
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5&/.RXWSXWGRHVQRWQHHGWREHLQYHUWHGEHIRUH
EHLQJLQSXWWRWKH&6%
TO HOST CONTROLLER
V+
100k
1.544 MHz
CLOCK
SIGNAL
ACLKI
CLKE
TCLK
SCLK
SCLK
TCLK
SDO
TPOS
TPOS
CS
SDI
TNEG
TNEG
SDO
MODE
SDI
RNEG
RNEG
INT
RPOS
RPOS
RGND
V+
100k
CS
RCLK
CS62180B
RCLK
RV+
CS61535A
V+
22k
0V
0.1uF
+5V
68uF
+
Figure A4. Interfacing the CS61535A with the
CS62180B (Host Mode)
CS61534 Compatibility
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LQJ DSSOLFDWLRQV ZKHUHHL JKWEL WVFD QE HG URSSHG
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&6
Using the CS61535A for SONET
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51.84 MHz
Div By
TCLK1
6480 to
193 bit
(or 256 bit)
Mapping
Circuit
Empty
FIFO
Write
Clock
TSER
TSER
CS62180B
RSER
FIFO
RCLK1
TCLK2
TPOS
TNEG
Jitter
Attenuator
Driver
CS61535A
RSER
RPOS
RNEG
RCLK2
Receiver
RCLK2
Figure A5. SONET Application
32
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EHLQSXWWRWKH&6$¶VMLWWHUDWWHQXDWRUZLWK
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FLUFXLWWRRS HUDWH 7KH &6$WKH Q UHPRYHV
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Target Rate
(MHz)
Clock
Divider
Resultant
Rate (MHz)
1.544
1.544
2.048
32
33
25
1.620
1.571
2.074
CS61535A
Transformers
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Maximum Gap
bits
(μs)
6.2
10
3.9
6
3.4
7
FIFO Depth
Required
21
26
34
Table A1. Locked VT FIFO Analysis
Parameter
CS61535A Receiver
CS61535A Transmitter
Turns Ratio
1:2 CT ± 5%
1:1 ± 1.5 % for 75 Ω E1
1:1.15 ± 5 % for 100 Ω T1
1:1.26 ± 1.5 % for 120 Ω E1
Primary Inductance
600 μH min. @ 772 kHz
1.5 mH min. @ 772 kHz
Primary Leakage Inductance
1.3 μH max. @ 772 kHz
0.3 μH max. @ 772 kHz
Secondary Leakage Inductance
0.4 μH max. @ 772 kHz
0.4 μH max. @ 772 kHz
Interwinding Capacitance
23 pF max.
18 pF max.
ET-constant
16 V-μs min. for T1
12 V-μs min. for E1
16 V-μs min. for T1
12 V-μs min. for E1
Table A2. Transformer Specifications
DS40F3
33
-XO¶
&21),'(17,$/
Application
RX:
T1 & E1
Turns
Ratio(s)
1:2CT
CS61535A
Manufacturer
Part Number
Package Type
Pulse Engineering
Schott
Bel Fuse
Pulse Engineering
Schott
Bel Fuse
Pulse Engineering
Schott
Bel Fuse
Pulse Engineering
Bel Fuse
Pulse Engineering
Bel Fuse
PE-65351
67129300
0553-0013-HC
PE-65388
67129310
0553-0013-RC
PE-65389
67129320
0553-0013-SC
PE-65565
0553-0013-7J
PE-65566
0553-0013-8J
1.5 kV through-hole, single
Pulse Engineering
Bel Fuse
Pulse Engineering
Bel Fuse
PE-65765
S553-0013-06
PE-65766
S553-0013-07
TX:
T1
1:1.15
TX:
E1 (75 & 120 Ω)
1:1.26
1:1
RX &TX:
T1
1:2CT
1:1.15
RX &TX:
E1 (75 & 120 Ω)
1:2CT
1:1.26
1:1
RX &TX:
T1
1:2CT
1:1.15
RX &TX:
E1 (75 & 120 Ω)
1:2CT
1:1.26
1:1
RX :
T1 & E1
TX:
E1 (75 & 120 Ω)
1:2CT
Pulse Engineering
PE-65835
1:1.26
1:1
Pulse Engineering
PE-65839
1.5 kV through-hole, single
1.5 kV through-hole, single
1.5 kV through-hole, dual
1.5 kV through-hole, dual
1.5 kVsurface-mount, dual
1.5 kV surface-mount, dual
3 kV through-hole, single
EN60950, EN41003 approved
3 kV through-hole, single
EN60950, EN41003 approved
Table A3. Recommended Transformers For The CS61535A
34
DS40F3
CS61535A
APPENDIX A. RECOMMENDED CRYSTAL SPECIFICATIONS
Cirrus Logic telecommunication devices that offer jitter attenuation require crystals with specifications for
frequency pullability. The crystal oscillation frequency is dictated by capacitive loading, which is controlled by the chip. Therefore, the crystals must meet the following specifications.
6.176 MHz Crystal Performance Specifications
Parameter
Total Frequency Range
Operating Frequency
Cload = 11.6 pF
Cload = 19.0 pF
Cload = 37.0 pF
Min
Typ
Max
Units
(Note 1)
-
370
390
ppm
(Note 2)
(Note 3)
(Note 2)
6.176803
6.175846
-
6.176000
-
6.176154
6.175197
MHz
MHz
MHz
8.192 MHz Crystal Performance Specifications
Parameter
Total Frequency Range
Operating Frequency
Notes:
Cload = 11.6 pF
Cload = 19.0 pF
Cload = 37.0 pF
Min
Typ
Max
Units
(Note 1)
-
210
245
ppm
(Note 2)
(Note 3)
(Note 2)
8.192410
8.191795
-
8.192000
-
8.192205
8.191590
MHz
MHz
MHz
1. With Cload varying from 11.6 to 37.0 pF at a given temperature.
2. Measured at -40 to 85°C.
3. Measured with Saunders 150D meter at 25 °C.
DS40F3
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CS61535A
REVISION HISTORY
Revision
Date
Changes
F3
Jul ’09
Removed development system info. (No longer supported). Removed PDIP option.
Changed PLCC package option to lead-free.
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to http://www.cirrus.com
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives
consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND
CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY
AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR
CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO
FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
36
DS40F3