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LV XVHG DV WKH WUDQVPLWWHU UHIHUHQFH FORFNï 7KH WUDQVFHLYHU FDQ DOVR EH UHVHW IURP WKH +RVW RU +DUGð ZDUH 0RGHï ,Q +RVW 0RGHñ UHVHW LV FRPPDQGHG E\ VLPXOð WDQHRXVO\ ZULWLQJ 5/223 DQG //223 WR WKH UHJLVWHUï ,Q +DUGZDUH 0RGHñ UHVHW LV FRPPDQGHG E\ KROGLQJ 5/223 DQG //223 +LJK VLPXOWDQHRXVO\ IRU ëíí QVï 5HVHW LV LQLð WLDWHG RQ WKH IDOOLQJ HGJH RI WKH UHVHW UHTXHVWï ,Q HLWKHU PRGHñ UHVHW FOHDUV DQG VHWV DOO UHJLVWHUV WR í DQG WKHQ EHJLQV FDOLEUDWLRQï L1 5HFHLYHU The LXT305A receives the signal input from one twistedpair line on each side of a center-grounded transformer. Positive pulses are received at RTIP and negative pulses are received at RRING. Recovered data is output at RPOS and RNEG, and the recovered clock is output at RCLK. Refer to Test Specifications for LXT305A receiver timing. The signal received at RPOS and RNEG is processed through the peak detector and data slicers. The peak detector samples the inputs and determines the maximum value of the received signal. A percentage of the peak value is provided to the data slicers as a threshold level to ensure optimum signal-to-noise ratio. For T1 applications (determined by Equalizer Control inputs EC1 - EC3 ≠ 000 or 001) the threshold is set to 70% of the peak value. This threshold is maintained above 65% for up to 15 successive zeros over the range of specified operating conditions. For E1 applications (EC inputs = 000 or 001) the threshold is 50%. The receiver is capable of accurately recovering signals with up to -13.6 dB of attenuation (from 2.4 V), corresponding to a received signal level of approximately 500 mV. Maximum line length is 1500 feet of ABAM cable (approximately 6 dB of attenuation). Regardless of received signal level, the peak detectors are held above a minimum level of .3 V to provide immunity from impulsive noise. After processing through the data slicers, the received signal is routed to the data and clock recovery sections, and to the receive monitor. The data and clock recovery circuits are highly tolerant with an input jitter tolerance significantly better than required by Pub 62411. Refer to Test Specifications for additional information. The receiver monitor loads a digital counter at the RCLK frequency. The count is incremented each time a zero is received, and reset to zero each time a one (mark) is received. Upon receipt of 175 consecutive zeros the LOS pin goes High, and a smooth transition replaces the RCLK output with the MCLK. Received marks are output regardless of the LOS status, but the LOS pin will not reset until the ones density reaches 12.5%. This level is based on receipt of at least 4 ones in any 32-bit period with no more than 15 consecutive zeros. ëðéê /;7êíè$ ,QWHJUDWHG 7ìî(ì 6KRUWð+DXO 7UDQVFHLYHU ZLWK 7UDQVPLW -$ 7UDQVPLWWHU racy). Series resistors also provide increased surge protection and reduced short circuit current flow. Data received for transmission onto the line is clocked serially into the device at TPOS and TNEG. Input synchronization is supplied by the transmit clock (TCLK). The transmitted pulse shape is determined by Equalizer Control signals EC1 through EC3 as shown in Table 4. Refer to Test Specifications for master and transmit clock timing characteristics. Shaped pulses are applied to the AMI line driver for transmission onto the line at TTIP and TRING. Equalizer Control signals may be hardwired in the Hardware Mode, or input as part of the serial data stream (SDI) in the Host Mode )LJXUH ëã èíø $0, &RGLQJ Pulses can be shaped for either 1.544 or 2.048 Mbps applications. 1.544 Mbps pulses for DSX-1 applications can be programmed to match line lengths from 0 to 655 feet of ABAM cable. The LXT305A also matches FCC and ECSA specifications for CSU applications. 2.048 Mbps pulses can drive coaxial or shielded twisted-pair lines. -LWWHU $WWHQXDWLRQ Jitter attenuation of the LXT305A transmit outputs is provided by a Jitter Attenuation Loop (JAL) and an Elastic Store (ES). An external crystal oscillating at 4 times the bit rate provides clock stabilization. Refer to Application Information for crystal specifications. The ES is a 32 x 2bit register. Transmit data is clocked into the ES with the transmit clock (TCLK) signal, and clocked out of the ES with the dejittered clock from the JAL. When the bit count in the ES is within two bits of overflowing or underflowing, the ES adjusts the output clock by 1/8 of a bit period. The ES produces an average delay of 16 bits in the receive path. 'ULYHU 3HUIRUPDQFH 0RQLWRU 7KH WUDQVFHLYHU LQFRUSRUDWHV D 'ULYHU 3HUIRUPDQFH 0RQLð WRU õ'30ô LQ SDUDOOHO ZLWK 77,3 DQG 75,1* DW WKH RXWSXW WUDQVIRUPHUï 7KH '30 RXWSXW JRHV +LJK XSRQ GHWHFWLRQ RI çê FRQVHFXWLYH ]HURVï ,W LV UHVHW ZKHQ D RQH LV GHWHFWHG RQ WKH WUDQVPLW OLQHñ RU ZKHQ D UHVHW FRPPDQG LV UHFHLYHGï /LQH &RGH %LW &HOO 77,3 ì í ì 75,1* 7DEOH ëã /;7êíè$ 6HULDO 'DWD 2XWSXW %LWV õ6HH )LJXUH éô %LW 'è %LW 'ç %LW 'æ í í í 5HVHW KDV RFFXUUHGñ RU QR SURJUDP LQSXWï í í ì 7$26 LV DFWLYHï í ì í /RFDO /RRSEDFN LV DFWLYHï í ì ì 7$26 DQG /RFDO /RRSEDFN DUH DFWLYHï ì í í 5HPRWH /RRSEDFN LV DFWLYHï ì í ì '30 KDV FKDQJHG VWDWH VLQFH ODVW &OHDU '30 RFFXUUHGï ì ì í /26 KDV FKDQJHG VWDWH VLQFH ODVW &OHDU /26 RFFXUUHGï ì ì ì /26 DQG '30 KDYH ERWK FKDQJHG VWDWH VLQFH ODVW &OHDU '30 DQG &OHDU /26 RFFXUUHGï 6WDWXV 2SHUDWLQJ 0RGHV The LXT305A can be controlled through hard-wired pins (Hardware Mode) or by a microprocessor through a serial interface (Host Mode). The mode of operation is set by the MODE pin logic level. The LXT305A can also be commanded to operate in one of several diagnostic modes. The LXT305A transmits data as a 50% AMI line code as shown in Figure 2. The output driver maintains a constant low output impedance regardless of whether it is driving marks or spaces. This well controlled output impedance provides excellent return loss (> 18 dB) when used with external 9.1 ″ precision (± 1 % accuracy) in series with a transmit transformer with a turns ratio of 1:2.3 (± 2% accu- ëðéé L1 )XQFWLRQDO 'HVFULSWLRQ +RVW 0RGH 2SHUDWLRQ the serial data and receive data output timing. The Clock Edge (CLKE) signal determines when these outputs are valid, relative to the Serial Clock (SCLK) or RCLK as listed in Table 3. To allow a host microprocessor to access and control the LXT305A through the serial interface, MODE is set High. 7DEOH êã 9DOLG &/.( 6HWWLQJV The serial interface (SDI/SDO) uses a 16-bit word consisting of an 8-bit Command/Address byte and an 8-bit Data byte. Figure 3 shows the serial interface data structure and relative timing. The Host Mode provides a latched Interrupt output (INT) which is triggered by a change in the Loss of Signal (LOS) and/or Driver Performance Monitor (DPM) bits. The Interrupt is cleared when the interrupt condition no longer exists, and the host processor enables the respective bit in the serial input data byte. Host Mode also allows control of &/.( 2XWSXW &ORFN 9DOLG (GJH /RZ 5326 51(* 6'2 5&/. 5&/. 6&/. 5LVLQJ 5LVLQJ )DOOLQJ +LJK 5326 51(* 6'2 5&/. 5&/. 6&/. )DOOLQJ )DOOLQJ 5LVLQJ ï )LJXUH êã /;7êíè$ 6HULDO ,QWHUIDFH 'DWD 6WUXFWXUH CS SCLK ADDRESS / COMMAND BYTE R/W SDI/ SDO ADDRESS / COMMAND BYTE A0 A1 0 R/W A2 A3 0 0 A4 0 A0 DATA INPUT / OUTPUT BYTE A5 1 LOS D0 0 DFM D1 X A6 A4 X=DON’T CARE CLEAR INTERRUPTS INPUT DATA BYTE A6 EC1 EC2 EC3 D2 D3 D4 R/W- = 1: Read R/W- = 0: Write D5 D6 D7 127( 2XWSXW GDWD E\WH LV WKH VDPH DV WKH LQSXW GDWD E\WH H[FHSW IRU ELWV 'áèãæ! VKRZQ LQ 7DEOH ëï SET LOOPBACKS OR RESET REMOTE LOCAL D0 (LSB) TAOS D7(MSB) 7DEOH éã (TXDOL]HU &RQWURO ,QSXWV (&ê (&ë (&ì í ì ì ì ì í í í ì í í ì ì í í ì ì í ì í ì í ì í L1 /LQH /HQJWKì &DEOH /RVVë í a ìêê IW $%$0 íïç G% ìêê a ëçç IW $%$0 ìïë G% ëçç a êää IW $%$0 ìïå G% êää a èêê IW $%$0 ëïé G% èêê a çèè IW $%$0 êïí G% ,78 5HFRPPHQGDWLRQ *ïæíê )&& 3DUW çåñ 2SWLRQ $ $SSOLFDWLRQ %LW 5DWH '6;ðì ìïèéé 0ESV (ì ð &RD[ õæè Ωô (ì ð 7ZLVWHGðSDLU õìëí Ωô &68 õ'6ðìô ëïíéå 0ESV ìïèéé 0ESV ëðéè /;7êíè$ ,QWHJUDWHG 7ìî(ì 6KRUWð+DXO 7UDQVFHLYHU ZLWK 7UDQVPLW -$ The LXT305A serial port is addressed by setting bit A4 in the Address/Command byte, corresponding to address 16. The LXT305A contains only a single output data register so no complex chip addressing scheme is required. The register is accessed by causing the Chip Select (CS) input to transition from High to Low. Bit 1 of the serial Address/ Command byte provides Read/Write control when the chip is accessed. A logic 1 indicates a read operation, and a logic 0 indicates a write operation. Table 2 lists serial data output bit combinations for each status. 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Includes device and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load. 2. Functionality of pins 23 and 25 depends on mode. See Host/Hardware Mode descriptions. 3. Output drivers will output CMOS logic levels into CMOS loads. 4. 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