MX66C256 Very Low Power 32k x 8 CMOS SRAM DESCRIPTION FEATURES The MX66C256 is a high performance, very low power CMOS Static Random Access Memory organized as 32,768 words by 8 bits and operates at 5.0V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.4uA and maximum access time of 70ns and 100 ns in 5V operation. Easy memory expansion is provided by an active LOW chip enable(CE), and active LOW output enable (OE) and three-state output drivers. The MX66C256 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The MX66C256 is available in the JEDEC standard 28 pin 330mil Plastic SOP, and 8mmx13.4mm TSOP (normal type). Vcc operation voltage : 5.0V Very low power consumption : 50 mA (Max.) write current 40 mA (Max.) read current 0.4uA (Typ.) CMOS standby current High speed access time : - 70 70ns (Max.) - 100 100ns (Max.) Input levels are CMOS-compatible Automatic power down when chip is deselected Three state outputs Fully static operation Data retention supply voltage as low as 2.0V Easy expansion with CE and OE options PIN CONFIGURATIONS BLOCK DIAGRAM A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 P/N DS0035 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 1 27 2 26 3 25 4 24 5 23 6 22 7 8 28-SOP 21 20 9 19 10 18 11 17 12 13 16 14 15 28-TSOP VCC WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 A5 A6 A7 A12 A14 A13 A8 A9 A11 Address Input Buffer 18 Row 512 Memory Array 512 x 512 Decoder 512 28 27 26 25 24 23 22 21 20 19 18 17 16 15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 8 8 Data Input Buffer Data Output Buffer Column I/O 8 8 Write Driver Sense Amp 64 Column Decoder 12 CE WE OE Vdd Gnd 1 Macronix America Inc. USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 www.macronix.com Control Address Input Buffer A4 A3 A2 A1 A0 A10 Rev. 1.1, Jan., 2000 MX66C256 PIN DESCRIPTIONS A0-A14 Address Input These 15 address input select one of the 32768 x 8-bit words in the RAM CE is active LOW . Chip enable must be active to read from or write to the device. If chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. These 8 bi-directional ports are used to read data from or write data into the RAM. Power Supply Ground CE Chip Enable Input WE Write Enable Input OE Output Enable Input DQ0 - DQ7 Data Input/Output Ports Vcc GND TRUTH TABLE WE CE OE I/O Operation Not Selected MODE X H X High Z Output Disabled Vcc Current ICCSB, ICCSB1 H L H High Z ICC Read H L L DOUT ICC Write L L X DIN ICC ABSOLUTE MAXIMUM RATINGS(1) SYMBOL PARAMETER RATING VTERM Terminal Voltage with Respect to GND TBIAS Temperature Under Bias -40 to +125 OC TSTG Storage Temperature OC PT Power Dissipation 1.0 W IOUT DC Output Current 20 mA -0.5 to +7.0 -60 to +150 OPERATING RANGE UNITS RANGE V COMMERCIAL INDUSTRIAL 0O C to + 70O C Vcc 4.5 ~ 5.5V 4.5 ~ 5.5V -40O C to + 85O C CAPACITANCE(1) (TA = 25O C, f = 1.0 MHz) SYMBOL 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. P/N DS0035 AMBIEN TEMPERATURE 2 Macronix America Inc. USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 www.macronix.com PARAMETER CONDITIONS MAX. UNIT CIN Input Capacitance VIN = 0V 6 pF CDQ Input/Output Capacitance VI/O = 0V 8 pF 1. This parameter is guaranteed and not tested. Rev. 1.1, Jan., 2000 MX66C256 DC ELECTRICAL CHARACTERISTICS ( TA = 0o to + 70oC ) PARAMETER NAME PARAMETER MIN. TEST CONDITIONS IIL Guaranteed Input Low Voltage(2) Guaranteed Input High Voltage(2) Input Leakage Current IOL Output Leakage Current VOL Output Low Voltage Vcc = Max, VIN = 0V to Vcc Vcc = Max, CE = VIH, or OE = VIH, VI/O = 0V to Vcc Vcc = 5.0V, IOL = 2mA VOH Output High Voltage Vcc = 5.0V, IOH = -1mA VIL VIH ICC ICCSB ICCSB1 Operating Power Supply Current Standby Power Supply Current Power Down Supply Current TYP.(1) MAX. UNITS -0.5 0.3VCC V 0.7VCC VCC+0.2 V 1 uA 1 uA 0.4 V 2.4 V CE=VIL, IDQ=0mA, F=Fmax(3) Vcc = 5.0V 50 mA CE=VIL, IDQ=0mA, F=1MHZ Vcc = 5.0V 40 mA CE = VIH, IDQ = 0mA, Vcc = 5.0V 1 mA CE ≥ Vcc-0.2V, VIN ≥ Vcc - 0.2V or VIN ≤ 0.2V Vcc = 5.0V 3 uA 0.4 1. Typical characteristics are at TA = 25oC. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 3. FMAX = 1/tRC . DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC ) SYMBOL VDR ICCDR PARAMETER MIN. TYP.(1) MAX. UNITS TEST CONDITIONS Vcc for Data Retention CE ≥Vcc - 0.2V, VIN ≥ Vcc - 0.2V or VIN ≤0.2V Data Retention Current CE ≥ Vcc -0.2V, VIN ≥ Vcc - 0.2V or VIN ≤ 0.2V tCDR Chip Deselect to Data Retention Time tR Operation Recovery Time 2.0 V 0.01 0.20 uA 0 ns TRC(2) ns See Retention Waveform 1. V cc = 2.0V, TA = + 25OC 2. tRC = Read Cycle Time LOW VCC DATA RETENTION WAVEFORM (1) (CE Controlled) Data Retention Mode VCC Vcc VDR ≥ 2.0V VIH VCC tR t CDR CE ≥ Vcc - 0.2V VIH CE P/N DS0035 3 Macronix America Inc. USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 www.macronix.com Rev. 1.1, Jan., 2000 MX66C256 KEY TO SWITCHING WAVEFORMS AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level 5.0/V0V WAVEFORM 5ns 2.5V INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM H TO L WILL BE CHANGE FROM H TO L MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H AC TEST LOADS AND WAVEFORMS 1923 Ω 1923 Ω 5.0V 5.0V OUTPUT OUTPUT , 100PF INCLUDING JIG AND SCOPE 5PF INCLUDING JIG AND SCOPE 1020Ω 1020 Ω FIGURE 1A FIGURE 1B DON T CARE: ANY CHANGE PERMITTED CHANGE : STATE UNKNOWN DOES NOT APPLY CENTER LINE IS HIGH IMPEDANCE ¡¨OFF ¡¨STATE THEVENIN EQUIVALENT 667 Ω OUTPUT 1.73V ALL INPUT PULSES VCC 10% 90% 90% 10% GND → → ← FIGURE 2 ← 5ns AC ELECTRICAL CHARACTERISTICS (over the operating range) READ CYCLE JEDEC PARAMETER PARAMETER NAME NAME tAVAX tAVQV tELQV tGLQV tELQX tGLQX tEHQZ tGHQZ tAZQX tRC tAA tACS tOE tCLZ tOLZ tCHZ tOHZ tOH DESCRIPTION MX66C256-70 MX66C256-10 MIN. TYP. MAX. MIN. TYP. MAX. 70 Read Cycle Time 100 UNIT Address Access Time 70 100 ns ns Chip Select Access Time 70 100 ns Output Enable to Output Valid 50 50 ns Chip Select to Output Low Z 10 10 Output Enable to Output in Low Z 10 10 Chip Deselect to Output in High Z Output Disable to Output in High Z Output Disable to Output Address Change ns ns 0 35 0 35 ns 0 30 0 30 ns 10 ns 10 1. Typical characteristics are at Vcc = 5.0V, TA = 25oC. SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC ADDRESS t t t OH AA OH D OUT P/N DS0035 4 Macronix America Inc. USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 www.macronix.com Rev. 1.1, Jan., 2000 MX66C256 READ CYCLE2 (1,3,4) CE t ACS (5) t CHZ (5) t CLZ D OUT READ CYCLE3 (1,4) t RC ADDRESS t AA OE t OE t OH t OLZ CE t ACS (5) t OHZ (5) (1,5) t CHZ t CLZ D OUT NOTES: 1. WE is high for read Cycle. 2. Device is continuously selected when CE = VIL . 3. Address valid prior to or coincident with CE transition low . 4. OE = VIL . 5. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. P/N DS0035 5 Macronix America Inc. USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 www.macronix.com Rev. 1.1, Jan., 2000 MX66C256 AC ELECTRICAL CHARACTERISTICS (over the operating range) WRITE CYCLE JEDEC PARAMETER PARAMETER NAME NAME tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tWLQZ tDVWH tWHDX tGHQZ tWHQX tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOHZ tOW DESCRIPTION MX66C256-70 MIN. TYP. MAX. UNIT Write Cycle Time 70 Chip Select to End of Write 70 ns ns 0 ns Address Valid to End of Write 70 ns Write Pulse Width 50 ns Address Set up Time (CE , WE) Write Recovery Time ns 0 Write to Output in High Z 30 Data to Write Time Overlap Data Hold from Write Time Output Disable to Output in High Z 0 End of Write to Output Active 5 ns ns 40 ns 0 30 ns ns 1. Typical characteristics are at Vcc = 5.0V, TA = 25oC. SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t WC ADDRESS t (3) WR OE (5) (11) t CW t WP CE t WE AW t AS (2) (4,10) t OHZ D OUT t t DH DW D IN P/N DS0035 6 Macronix America Inc. USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 www.macronix.com Rev. 1.1, Jan., 2000 MX66C256 WRITE CYCLE2 (1,6) t WC ADDRESS (11) t CW (5) CE t AW t WP (2) WE t t AS DH (4,10) t WHZ D OUT (7) (8) t DW t DH (8) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with CL = 5pF as shown in Figure 1b. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE going low to the end of write. P/N DS0035 7 Macronix America Inc. USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 www.macronix.com Rev. 1.1, Jan., 2000 MX66C256 ORDERING INFORMATION SPEED (ns) ORDERING PART NUMBER PACKAGE 70 MX66C256MC- 70 100 MX66C256MC-10 SOP-28PIN SOP-28PIN SOP-28PIN SOP-28PIN TSOP-28PIN TSOP-28PIN TSOP-28PIN TSOP-28PIN 70 MX66C256MI- 70 100 MX66C256MI-10 70 MX66C256TC- 70 100 MX66C256TC- 10 70 MX66C256TI- 70 100 MX66C256TI-10 TYPE TEMPERATURE RANGE 0O C to + 70O C 0O C to + 70O C -40O C to + 85O C -40O C to + 85O C 0O C to + 70O C 0O C to + 70O C -40O C to + 85O C -40O C to + 85O C n PACKAGE DIMENSIONS P/N DS0035 8 Macronix America Inc. USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 www.macronix.com Rev. 1.1, Jan., 2000 MX66C256 n PACKAGE DIMENSIONS (continued) P/N DS0035 9 Macronix America Inc. USA 1338 Ridder Park Dr., San Jose, CA 95131 Tel (408)453-8088 Fax (408)451-0876 www.macronix.com Rev. 1.1, Jan., 2000