LTM4637 20A DC/DC µModule Step-Down Regulator FEATURES DESCRIPTION Complete 20A Switch Mode Power Supply 4.5V to 20V Input Voltage Range 0.6V to 5.5V Output Voltage Range ±1.5% Total DC Output Voltage Error (–40°C to 125°C) n Differential Remote Sense Amplifier for Precision Regulation for (VOUT ≤ 3.3V) n Current Mode Control/Fast Transient Response n Parallel Current Sharing (Up to 80A) n Frequency Synchronization n Selectable Pulse-Skipping or Burst Mode® Operation n Soft-Start/Voltage Tracking n Up to 88% Efficiency (12V , 1.8V IN OUT) n Overcurrent Foldback Protection n Output Overvoltage Protection n Internal Temperature Monitor n Overtemperature Protection n15mm × 15mm × 4.32mm LGA Package The LTM®4637 is a complete 20A output high efficiency switch mode step-down DC/DC µModule (micromodule) regulator. Included in the package are the switching controller, power FETs, inductor and compensation components. Operating over an input voltage range from 4.5V to 20V, the LTM4637 supports an output voltage range of 0.6V to 5.5V, set by a single external resistor. Only a few input and output capacitors are needed. n n n n APPLICATIONS n n n n Telecom Servers and Networking Equipment Industrial Equipment Medical Systems High Ambient Temperature Systems Current mode operation allows precision current sharing of up to four LTM4637 regulators to obtain up to 80A output. High switching frequency and a current mode architecture enable a very fast transient response to line and load changes without sacrificing stability. The device supports frequency synchronization, multiphase/current sharing, Burst Mode operation and output voltage tracking for supply rail sequencing. A diode-connected PNP transistor is available for use as an internal temperature monitor. The LTM4637 is offered in a 15mm × 15mm × 4.32mm LGA package. The LTM4637 is RoHS compliant. The LTM4637 is pin compatible with the LTM4627, a 15A DC/DC µModule regulator. L, LT, LTC, LTM, PolyPhase, Burst Mode, µModule, Linear Technology, the Linear logo are registered trademarks and LTpowerCAD is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 5481178, 5847554, 6580258, 6304066, 6476589, 6774611, 6677210. TYPICAL APPLICATION 12VIN, 1.2VOUT, 20A DC/DC µModule® Regulator 12VIN Efficiency vs Load Current 2.2µF 22µF 16V ×4 1.2VOUT 250kHz CCM 95 10k 0.1µF VIN EXTVCC INTVCC PGOOD COMP VOUT VOUT_LCL TRACK/SS RUN DIFF_OUT VOSNS+ MODE_PLLIN VOSNS– TEMP * SEE TABLE 5 ** SEE TABLE 1 LTM4637 fSET SGND GND VFB VOUT 1.2V 20A 330pF 100µF* + 6.3V ×2 470µF 6.3V ×2 90 EFFICIENCY (%) VIN 12V 100 85 80 75 70 RFB** 60.4k 4637 TA01a 65 0 2 4 6 8 10 12 14 16 18 20 OUTPUT CURRENT (A) 4637 TA01b 4637f For more information www.linear.com/LTM4637 1 LTM4637 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Note 1) VIN.............................................................. –0.3V to 22V VOUT.............................................................. –0.3V to 6V INTVCC, VOUT_LCL, PGOOD, EXTVCC............. –0.3V to 6V MODE_PLLIN, fSET, TRACK/SS, VOSNS –, VOSNS+, DIFF_OUT.................... –0.3V to INTVCC VFB, COMP (Note 7) .................................. –0.3V to 2.7V RUN (Note 5)................................................ –0.3V to 5V TEMP......................................................... –0.3V to 0.8V INTVCC Peak Output Current (Note 6)...................100mA Internal Operating Temperature Range (Note 2)................................................... –40°C to 125°C Storage Temperature Range................... –55°C to 125°C Reflow (Peak Body) Temperature........................... 245°C TOP VIEW 1 2 3 VIN MODE_PLLIN INTVCC TRACK/SS 4 5 6 7 8 9 10 COMP 11 12 A VIN RUN fSET B C INTVCC D F TEMP EXTVCC PGOOD VFB G PGOOD E GND SGND H VOUT J VOSNS+ K DIFF_OUT L VOUT_LCL M VOSNS– LGA PACKAGE 133-LEAD (15mm × 15mm × 4.32mm) TJ(MAX) = 125°C, θJA = 9.5°C/W, θJCbottom = 4°C/W, θJCtop = 6.7°C/W, θJB = 4.5°C/W θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS; WEIGHT = 2.9g θ VALUES DETERMINED PER JESD51-12 ORDER INFORMATION LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION 133-Lead (15mm × 15mm × 4.32mm) LGA –40°C to 125°C 133-Lead (15mm × 15mm × 4.32mm) LGA –40°C to 125°C LTM4637EV#PBF LTM4637EV#PBF LTM4637V LTM4637IV#PBF LTM4637IV#PBF LTM4637V TEMPERATURE RANGE Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/ ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full internal operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 12V, per the typical application in Figure 22. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VIN Input DC Voltage l 4.5 20 V VOUT Range VOUT Range l 0.6 5.5 V VOUT(DC) Output Voltage, Total CIN = 22µF × 3 Variation with Line and Load COUT = 100µF Ceramic, 470µF POSCAP RFB = 40.2k, MODE_PLLIN = GND VIN = 5V to 20V, IOUT = 0A to 20A (Note 4) l 1.477 1.50 1.523 V 1.1 1.25 1.4 Input Specifications VRUN RUN Pin On Threshold VRUNHYS RUN Pin On Hysteresis VRUN Rising 130 V mV 4637f 2 For more information www.linear.com/LTM4637 LTM4637 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full internal operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 12V, per the typical application in Figure 22. SYMBOL PARAMETER CONDITIONS IQ(VIN) Input Supply Bias Current VIN = 12V, VOUT = 1.5V, Burst Mode Operation, IOUT = 0.1A VIN = 12V, VOUT = 1.5V, Pulse-Skipping Mode, IOUT = 0.1A VIN = 12V, VOUT = 1.5V, Switching Continuous, IOUT = 0.1A Shutdown, RUN = 0, VIN = 12V IS(VIN) Input Supply Current VIN = 5V, VOUT = 1.5V, IOUT = 20A VIN = 12V, VOUT = 1.5V, IOUT = 20A MIN TYP MAX 17 25 54 40 UNITS mA mA mA µA 6.8 2.87 A A Output Specifications IOUT(DC) Output Continuous Current Range VIN = 12V, VOUT = 1.5V (Note 4) 0 20 A ∆VOUT (Line) VOUT Line Regulation Accuracy VOUT = 1.5V, VIN from 4.5V to 20V IOUT = 0A l 0.02 0.06 %/V ∆VOUT (Load) VOUT Load Regulation Accuracy VOUT = 1.5V, IOUT = 0A to 20A, VIN = 12V (Note 4) l 0.2 0.45 % VOUT(AC) Output Ripple Voltage IOUT = 0A, COUT = 100µF Ceramic, 470µF POSCAP VIN = 12V, VOUT = 1.5V 30 mVP-P ∆VOUT(START) Turn-On Overshoot COUT = 100µF Ceramic, 470µF POSCAP, VOUT = 1.5V, IOUT = 0A, VIN = 12V 15 mV tSTART Turn-On Time COUT = 100µF Ceramic, 470µF POSCAP, No Load, TRACK/SS = 0.001µF, VIN = 12V 0.6 ms ∆VOUTLS Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load COUT = 100µF × 2 Ceramic, 470µF × 3 POSCAP, VIN = 12V, VOUT = 1.5V 50 mV tSETTLE Settling Time for Dynamic Load Step Load: 0% to 50% to 0% of Full Load, VIN = 5V, COUT = 100µF × 2 Ceramic, 470µF × 3 POSCAP 50 µs IOUTPK Output Current Limit VIN = 12V, VOUT = 1.5V VIN = 5V, VOUT = 1.5V 30 30 A A Control Section VFB Voltage at VFB Pin IOUT = 0A, VOUT = 1.5V IFB Current at VFB Pin (Note 7) VOVL Feedback Overvoltage Lockout ITRACK/SS Track Pin Soft-Start Pull-Up Current TRACK/SS = 0V tON(MIN) Minimum On-Time (Note 3) RFBHI Resistor Between VOUT_LCL and VFB Pins l l 0.594 0.60 0.606 V –12 –25 nA 0.65 0.67 0.69 V 1.0 1.2 1.4 µA 100 60.05 60.40 ns 60.75 kΩ Remote Sense Amplifier VOSNS+, VOSNS– CM RANGE Common Mode Input Range VIN = 12V, Run > 1.4V VDIFF_OUT(MAX) Maximum DIFF_OUT Voltage IDIFF_OUT = 300µA VOS Input Offset Voltage VOSNS+ = VDIFF_OUT = 1.5V, IDIFF_OUT = 100µA AV Differential Gain (Note 7) 1 V/V SR Slew Rate (Note 6) 2 V/µs GBP Gain Bandwidth Product (Note 6) 3 MHz CMRR Common Mode Rejection (Note 7) 60 dB IDIFF_OUT DIFF_OUT Current Sourcing 0 3.6 INTVCC – 1.4 V 2 2 V mV mA 4637f For more information www.linear.com/LTM4637 3 LTM4637 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full internal operating temperature range (Note 2), otherwise specifications are at TA = 25°C. VIN = 12V, per the typical application in Figure 22. SYMBOL PARAMETER CONDITIONS PSRR Power Supply Rejection Ratio 5V < VIN < 20V (Note 7) MIN TYP 100 MAX UNITS dB RIN Input Resistance VOSNS+ to GND 80 kΩ VPGOOD PGOOD Trip Level VFB With Respect to Set Output VFB Ramping Negative VFB Ramping Positive –10 10 % % VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V 5 5.2 V PGOOD Output INTVCC Linear Regulator VINTVCC Internal VCC Voltage VINTVCC Load Reg INTVCC Load Regulation External VCC Switchover VEXTVCC VLDO Ext EXTVCC Voltage Drop 6V < VIN < 20V 4.8 ICC = 0 to 50mA 0.5 EXTVCC Ramping Positive l 4.5 ICC = 25mA, VEXTVCC = 5V % 4.7 50 V 100 mV 800 kHz Oscillator and Phase-Locked Loop fSYNC Frequency Sync Capture Range MODE_PLLIN Clock Duty Cycle = 50% 250 fNOM Nominal Frequency VfSET = 1.2V 450 500 550 kHz fLOW Lowest Frequency VfSET = 0V 210 250 290 kHz fHIGH Highest Frequency VfSET ≥ 2.4V 700 770 850 kHz IFREQ Frequency Set Current 10 11 RMODE_PLLIN MODE_PLLIN Input Resistance VIH_MODE_PLLIN Clock Input Level High VIL_MODE_PLLIN Clock Input Level Low 9 250 µA kΩ 2.0 V 0.8 V Temperature Diode VTEMP TEMP Diode Voltage TC VTEMP Temperature Coefficient ITEMP = 100µA l Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTM4637 is tested under pulsed load conditions such that TJ ≈ TA. The LTM4637E is guaranteed to meet performance specifications over the 0°C to 125°C internal operating temperature range. Specifications over the full –40°C to 125°C internal operating temperature range are assured by design, characterization and correlation with statistical process controls. The LTM4637I is guaranteed to meet specifications over the full –40°C to 125°C internal operating temperature range. Note that the maximum ambient temperature consistent with these specifications is 0.6 V –2.2 mV/°C determined by specific operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. Note 3: The minimum on-time condition is specified for a peak-to-peak inductor ripple current of ~40% of IMAX Load. (See the Applications Information section) Note 4: See output current derating curves for different VIN, VOUT and TA. Note 5: Limit current into the RUN pin to less than 2mA. Note 6: Guaranteed by design. Note 7: 100% tested at wafer level. 4637f 4 For more information www.linear.com/LTM4637 LTM4637 TYPICAL PERFORMANCE CHARACTERISTICS Efficiency vs Load Current with 8VIN (Limit 5V Output to 15A) 100 95 95 95 90 90 90 85 80 1VOUT, 250kHz, CCM 1.2VOUT, 250kHz, CCM 1.5VOUT, 350kHz, CCM 1.8VOUT, 350kHz, CCM 2.5VOUT, 450kHz, CCM 3.3VOUT, 600kHz, CCM 70 65 0 2 4 85 80 1VOUT, 250kHz, CCM 1.2VOUT, 250kHz, CCM 1.5VOUT, 350kHz, CCM 1.8VOUT, 350kHz, CCM 2.5VOUT, 450kHz, CCM 3.3VOUT, 600kHz, CCM 5VOUT, 600kHz, CCM 75 70 65 6 8 10 12 14 16 18 20 OUTPUT CURRENT (A) 0 2 4 85 80 1VOUT, 250kHz, CCM 1.2VOUT, 250kHz, CCM 1.5VOUT, 350kHz, CCM 1.8VOUT, 350kHz, CCM 2.5VOUT, 450kHz, CCM 3.3VOUT, 600kHz, CCM 5VOUT, 600kHz, CCM 75 70 6 8 10 12 14 16 18 20 OUTPUT CURRENT (A) 4637 G01 65 0 95 95 90 90 EFFICIENCY (%) 75 OUTPUT TRANSIENT 50mV/DIV 200µs/DIV 80 LOAD STEP 5A/DIV 75 VIN = 12V 200µs/DIV VOUT = 1V IOUT = 0A TO 10A, CFF = 330pF OUTPUT CAPACITORS: 3 × 470µF POSCAP CAPACITORS 2 × 100µF CERAMIC CAPACITORS 70 5VIN, 1.8VOUT, 350kHz 8VIN, 1.8VOUT, 350kHz 12VIN, 1.8VOUT, 350kHz 70 0 0.5 1 1.5 2 OUTPUT CURRENT (A) 2.5 5VIN, 1.8VOUT, 350k 8VIN, 1.8VOUT, 350k 12VIN, 1.8VOUT, 350k 65 3 60 0 0.5 1 1.5 2 OUTPUT CURRENT (A) 2.5 4637 G04 3 1.5V Transient Response 1.8V Transient Response OUTPUT TRANSIENT 50mV/DIV 200µs/DIV OUTPUT TRANSIENT 50mV/DIV 200µs/DIV OUTPUT TRANSIENT 50mV/DIV 200µs/DIV LOAD STEP 5A/DIV LOAD STEP 5A/DIV LOAD STEP 5A/DIV 4637 G07 4637 G06 4637 G05 1.2V Transient Response VIN = 12V 200µs/DIV VOUT = 1.2V IOUT = 0A TO 10A, CFF = 330pF OUTPUT CAPACITORS: 3 × 470µF POSCAP CAPACITORS 2 × 100µF CERAMIC CAPACITORS 6 8 10 12 14 16 18 20 OUTPUT CURRENT (A) 1V Transient Response 85 80 4 4637 G03 Pulse-Skipping Mode Efficiency vs Load Current 85 2 4637 G02 Burst Mode Efficiency vs Load Current 65 EFFICIENCY (%) 100 75 EFFICIENCY (%) Efficiency vs Load Current with 12VIN (Limit 5V Output to 15A) 100 EFFICIENCY (%) EFFICIENCY (%) Efficiency vs Load Current with 5VIN VIN = 12V 200µs/DIV VOUT = 1.5V IOUT = 0A TO 10A, CFF = 330pF OUTPUT CAPACITORS: 3 × 470µF POSCAP CAPACITORS 2 × 100µF CERAMIC CAPACITORS 4637 G08 VIN = 12V 200µs/DIV VOUT = 1.8V IOUT = 0A TO 10A, CFF = 330pF OUTPUT CAPACITORS: 3 × 470µF POSCAP CAPACITORS 2 × 100µF CERAMIC CAPACITORS 4637 G09 4637f For more information www.linear.com/LTM4637 5 LTM4637 TYPICAL PERFORMANCE CHARACTERISTICS 2.5V Transient Response 5V Transient Response 3.3V Transient Response OUTPUT TRANSIENT 50mV/DIV 200µs/DIV OUTPUT TRANSIENT 50mV/DIV 200µs/DIV OUTPUT TRANSIENT 100mV/DIV 200µs/DIV LOAD STEP 5A/DIV LOAD STEP 5A/DIV LOAD STEP 5A/DIV VIN = 12V 200µs/DIV VOUT = 2.5V IOUT = 0A TO 10A, CFF = 330pF OUTPUT CAPACITORS: 3 × 470µF POSCAP CAPACITORS 2 × 100µF CERAMIC CAPACITORS 4637 G10 VIN = 12V 200µs/DIV VOUT = 3.3V IOUT = 0A TO 10A, CFF = 330pF OUTPUT CAPACITORS: 3 × 470µF POSCAP CAPACITORS 2 × 100µF CERAMIC CAPACITORS Turn-On No Load VIN = 12V 200µs/DIV VOUT = 5V IOUT = 0A TO 10A, CFF = 330pF OUTPUT CAPACITORS: 3 × 470µF POSCAP CAPACITORS 2 × 100µF CERAMIC CAPACITORS 4637 G12 Turn-On 20A Load VIN 2V/DIV 20ms/DIV VIN 2V/DIV 20ms/DIV VOUT 200mV/DIV 20ms/DIV VOUT 200mV/DIV 20ms/DIV 20ms/DIV 12V to 1.5V AT 0A LOAD TRACK/SS = 0.1µF 4637 G11 4637 G13 20ms/DIV 12V to 1.5V AT 20A LOAD TRACK/SS = 0.1µF Short-Circuit Protection with 20A Load Short-Circuit Protection No Load VOUT 500mV/DIV 200µs/DIV 4637 G14 VOUT 500mV/DIV 200µs/DIV INPUT CURRENT 1A/DIV INPUT CURRENT 200mA/DIV 200µs/DIV 12V to 1.5V AT 0A LOAD TRACK/SS = 0.1µF 4637 G15 200µs/DIV 12V to 1.5V AT 20A LOAD TRACK/SS = 0.1µF 4637 G16 4637f 6 For more information www.linear.com/LTM4637 LTM4637 PIN FUNCTIONS PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY. VIN (A1-A6, B1-B6, C1-C6): Power Input Pins. Apply input voltage between these and GND pins. Recommend placing input decoupling capacitance directly between VIN and GND pins. VOUT (J1-J10, K1-K11, L1-L11, M1-M11): Power Output Pins. Apply output load between these and GND pins. Recommend placing output decoupling capacitance between these pins and GND pins. Review Table 5. GND (B7, B9, C7, C9, D1-D6, D8, E1-E7, E9, F1-F9, G1-G9, H1-H9): Power Ground Pins for Both Input and Output. PGOOD (F11, G12): Output Voltage Power Good Indicator. Open-drain logic output is pulled to ground when the output voltage exceeds a ±10% regulation window. Both pins are tied together internally. SGND (G11, H11, H12): Signal Ground Pin. Return ground path for all analog and low power circuitry. Tie a single connection to the output capacitor GND. See layout guidelines in Figure 21. TEMP (D10): Temperature Monitor. See Applications Information section. MODE_PLLIN (A8): Forced Continuous Mode, Burst Mode Operation, or Pulse-Skipping Mode Selection Pin and External Synchronization Input to Phase Detector Pin. Connect this pin to INTVCC to enable pulse-skipping mode. Connect to ground to enable forced continuous mode. Floating this pin will enable Burst Mode operation. A clock on this pin will enable synchronization with forced continuous operation. See the Applications Information section. fSET (B12): A resistor can be applied from this pin to ground to set the operating frequency, or a DC voltage can be applied to set the frequency. See the Applications Information section. TRACK/SS (A9): Output Voltage Tracking Pin and SoftStart Inputs. The pin has a 1.2µA pull-up current source. A capacitor from this pin to ground will set a soft-start ramp rate. In tracking, the regulator output can be tracked to a different voltage. See the Applications Information section. VFB (F12): The Negative Input of the Error Amplifier. Internally, this pin is connected to VOUT_LCL with a 60.4k precision resistor. Different output voltages can be programmed with an additional resistor between VFB and ground pins. In PolyPhase® operation, tying the VFB pins together allows for parallel operation. See the Applications Information section. COMP (A11): Current Control Threshold and Error Amplifier Compensation Point. The current comparator threshold increases with this control voltage. Tie all COMP pins together for parallel operation. The device is internally compensated. RUN: (A10) Run Control Pin. A voltage above 1.4V will turn on the module. A 5.1V Zener diode to ground is internal to the module for limiting the voltage on the RUN pin to 5V, and allowing a pull-up resistor to VIN for enabling the device. Limit current into the RUN pin to ≤ 2mA. INTVCC: (A7, D9) Internal 5V LDO for Driving the Control Circuitry and the Power MOSFET Drivers. Both pins are internally connected. The 5V LDO has a 100mA current limit. INTVCC is controlled and enabled when RUN is activated high. EXTVCC (E12): External power input to an internal control switch allows an external source greater than 4.7V, but less than 6V to supply IC power and bypass the internal INTVCC LDO. EXTVCC must be less than VIN at all times during power-on and power-off sequences. See the Applications Information section. 5V output application can connect the 5V output to this pin to improve efficiency. The 5V output is connected to EXTVCC in the 5V derating curves. VOUT_LCL: (L12) This pin connects to VOUT through a 1M resistor, and to VFB with a 60.4k resistor. The remote sense amplifier output DIFF_OUT is connected to VOUT_LCL, and drives the 60.4k top feedback resistor in remote sensing applications. When the remote sense amplifier is used, DIFF_OUT effectively eliminates the 1MΩ from VOUT to VOUT_LCL. When the remote sense amplifier is not used, then connect VOUT_LCL to VOUT directly. 4637f For more information www.linear.com/LTM4637 7 LTM4637 PIN FUNCTIONS VOSNS+: (J12) (+) Input to the Remote Sense Amplifier. This pin connects to the output remote sense point. The remote sense amplifier can be used for VOUT ≤ 3.3V. Connect to ground when not used. DIFF_OUT: (K12) Output of the Remote Sense Amplifier. This pin connects to the VOUT_LCL pin for remote sense applications. Otherwise float when not used. The remote sense amplifier can be used for VOUT ≤ 3.3V. VOSNS–: (M12) (–) Input to the Remote Sense Amplifier. This pin connects to the ground remote sense point. The remote sense amplifier can be used for VOUT ≤ 3.3V. Connect to ground when not used. MTP1, MTP2, MTP3, MTP4, MTP5, MTP6, MTP7, (A12, B11, C10, C11, C12, D11, D12): Extra mounting pads used for increased solder integrity strength. Leave floating. BLOCK DIAGRAM PTC + OTP ~135°C – VOUT_LCL 1M VIN R1 > 1.4V = ON < 1.1V = OFF MAX = 5V VOUT 499k INTVCC + 400mV 10k PGOOD VIN RUN 5.1V R2 + 1.5µF 60.4k PNP M1 INTERNAL COMP 0.6µH SGND 10µF M2 fSET INTERNAL LOOP FILTER + 2.2Ω SGND INTVCC MODE_PLLIN + 250k DIFF AMP – INTVCC + TRACK/SS 2.2µF COUT VOUT 1V 20A GND – C SOFT-START VOUT POWER CONTROL VFB RfSET 50k CIN TEMP COMP RFB 90.9k VIN 4.5V TO 20V C VOSNS– VOSNS+ DIFF_OUT EXTVCC 4637 F01 Figure 1. Simplified LTM4637 Block Diagram 8 For more information www.linear.com/LTM4637 4637f LTM4637 DECOUPLING REQUIREMENTS TA = 25°C. Use Figure 1 configuration. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS CIN External Input Capacitor Requirement (VIN = 4.5V to 20V, VOUT = 1.5V) IOUT = 20A, 4× 22µF Ceramic X7R Capacitors (See Table 5) 88 µF COUT External Output Capacitor Requirement (VIN = 4.5V to 20V, VOUT = 1.5V) IOUT = 20A (See Table 5) 400 µF OPERATION Power Module Description The LTM4637 is a high performance single output standalone nonisolated switching mode DC/DC power supply. It can provide a 20A output with few external input and output capacitors. This module provides precisely regulated output voltages programmable via external resistors from 0.6VDC to 5.5VDC over a 4.5V to 20V input range. The typical application schematic is shown in Figure 22. The LTM4637 has an integrated constant-frequency current mode regulator, power MOSFETs, 0.6µH inductor, and other supporting discrete components. The switching frequency range is from 250kHz to 770kHz, and the typical operating frequency is shown in Table 5 for each VOUT. For switching noise-sensitive applications, it can be externally synchronized from 250kHz to 800kHz, subject to minimum on-time limitations. A single resistor is used to program the frequency. See the Applications Information section. With current mode control and internal feedback loop compensation, the LTM4637 module has sufficient stability margins and good transient performance with a wide range of output capacitors, even with all ceramic output capacitors. Current mode control provides cycle-by-cycle fast current limit in an overcurrent condition. An internal overvoltage monitor protects the output voltage in the event of an overvoltage >10%. The top MOSFET is turned off and the bottom MOSFET is turned on until the output is cleared. Overtemperature protection will turn off the regulator’s RUN pin at ~130°C to 137°C. See Applications Information. Pulling the RUN pin below 1.1V forces the regulator into a shutdown state. The TRACK/SS pin is used for programming the output voltage ramp and voltage tracking during start-up. See the Application Information section. The LTM4637 is internally compensated to be stable over all operating conditions. Table 5 provides a guideline for input and output capacitances for several operating conditions. LTpowerCAD™ is available for transient and stability analysis. The VFB pin is used to program the output voltage with a single external resistor to ground. A remote sense amplifier is provided for accurately sensing output voltages ≤3.3V at the load point. Multiphase operation can be easily employed with the synchronization inputs using an external clock source. See application examples. High efficiency at light loads can be accomplished with selectable Burst Mode operation using the MODE_PLLIN pin. These light load features will accommodate battery operation. Efficiency graphs are provided for light load operation in the Typical Performance Characteristics section. A TEMP pin is provided to allow the internal device temperature to be monitored using an onboard diode connected PNP transistor. 4637f For more information www.linear.com/LTM4637 9 LTM4637 APPLICATIONS INFORMATION The typical LTM4637 application circuit is shown in Figure 22. External component selection is primarily determined by the maximum load current and output voltage. Refer to Table 5 for specific external capacitor requirements for particular applications. VIN to VOUT Step-Down Ratios There are restrictions in the VIN to VOUT step-down ratio that can be achieved for a given input voltage. The duty cycle is 94% typical at 500kHz operation. The VIN to VOUT minimum dropout is a function of load current and operation at very low input voltage and high duty cycle applications. At very low duty cycles the minimum 100ns on-time must be maintained. See the Frequency Adjustment section and temperature derating curves. Input Capacitors The LTM4637 module should be connected to a low ACimpedance DC source. Additional input capacitors are needed for the RMS input ripple current rating. The ICIN(RMS) equation which follows can be used to calculate the input capacitor requirement. Typically 22µF X7R ceramics are a good choice with RMS ripple current ratings of ~ 2A each. A 47µF to 100µF surface mount aluminum electrolytic bulk capacitor can be used for more input bulk capacitance. This bulk input capacitor is only needed if the input source impedance is compromised by long inductive leads, traces or not enough source capacitance. If low impedance power planes are used, then this bulk capacitor is not needed. For a buck converter, the switching duty cycle can be estimated as: Output Voltage Programming The PWM controller has an internal 0.6V ±1% reference voltage. As shown in the Block Diagram, a 60.4k internal feedback resistor connects the VOUT_LCL and VFB pins together. When the remote sense amplifier is used, then DIFF_OUT is connected to the VOUT_LCL pin. If the remote sense amplifier is not used, then VOUT_LCL connects to VOUT. The output voltage will default to 0.6V with no feedback resistor. Adding a resistor RFB from VFB to ground programs the output voltage: VOUT = 0.6V • 60.4k +RFB RFB RFB (k) 0.6 1.0 1.2 1.5 1.8 2.5 3.3 5.0 Open 90.9 60.4 40.2 30.1 19.1 13.3 8.25 For parallel operation of N LTM4637s, the following equation can be used to solve for RFB: RFB = VOUT VIN Without considering the inductor ripple current, for each output the RMS current of the input capacitor can be estimated as: I CIN(RMS)= IOUT(MAX) η% • D •(1–D) where η% is the estimated efficiency of the power module. The bulk capacitor can be a switcher-rated aluminum electrolytic capacitor or a Polymer capacitor. Output Capacitors Table 1. VFB Resistor Table vs Various Output Voltages VOUT (V) D= 60.4k / N VOUT –1 0.6V Tie the VFB pins together for each parallel output. The COMP pins must be tied together also. The LTM4637 is designed for low output voltage ripple noise. The bulk output capacitors defined as COUT are chosen with low enough effective series resistance (ESR) to meet the output voltage ripple and transient requirements. COUT can be a low ESR tantalum capacitor, low ESR Polymer capacitor or ceramic capacitors. The typical output capacitance range is from 200µF to 800µF. Additional output filtering may be required by the system designer if further reduction of output ripple or dynamic transient spikes is required. Table 5 shows a matrix of different output voltages and output capacitors to minimize the voltage droop and overshoot during a 10A/µs transient. The table optimizes total equivalent ESR and total bulk capacitance 4637f 10 For more information www.linear.com/LTM4637 LTM4637 APPLICATIONS INFORMATION to optimize the transient performance. Stability criteria are considered in the Table 5 matrix, and LTpowerCAD is available for stability analysis. Multiphase operation will reduce effective output ripple as a function of the number of phases. Application Note 77 discusses this noise reduction versus output ripple current cancellation, but the output capacitance should be considered carefully as a function of stability and transient response. LTpowerCAD can be used to calculate the output ripple reduction as the number of implemented phases increase by N times. Burst Mode Operation The LTM4637 is capable of Burst Mode operation in which the power MOSFETs operate intermittently based on load demand, thus saving quiescent current. For applications where maximizing the efficiency at very light loads is a high priority, Burst Mode operation should be applied. To enable Burst Mode operation, simply float the MODE_PLLIN pin. During Burst Mode operation, the peak current of the inductor is set to approximately 30% of the maximum peak current value in normal operation even though the voltage at the COMP pin indicates a lower value. The voltage at the COMP pin drops when the inductor’s average current is greater than the load requirement. As the COMP voltage drops below 0.5V, the burst comparator trips, causing the internal sleep line to go high and turn off both power MOSFETs. In sleep mode, the internal circuitry is partially turned off, reducing the quiescent current. The load current is now being supplied from the output capacitors. When the output voltage drops, causing COMP to rise, the internal sleep line goes low, and the LTM4637 resumes normal operation. The next oscillator cycle will turn on the top power MOSFET and the switching cycle repeats. Pulse-Skipping Mode Operation In applications where low output ripple and high efficiency at intermediate currents are desired, pulse-skipping mode should be used. Pulse-skipping operation allows the LTM4637 to skip cycles at low output loads, thus increasing efficiency by reducing switching loss. Tying the MODE_PLLIN pin to INTVCC enables pulse-skipping operation. With pulse-skipping mode at light load, the internal current comparator may remain tripped for several cycles, thus skipping operation cycles. This mode has lower ripple than Burst Mode operation and maintains a higher frequency operation than Burst Mode operation. Forced Continuous Operation In applications where fixed frequency operation is more critical than low current efficiency, and where the lowest output ripple is desired, forced continuous operation should be used. Forced continuous operation can be enabled by tying the MODE_PLLIN pin to ground. In this mode, inductor current is allowed to reverse during low output loads, the COMP voltage is in control of the current comparator threshold throughout, and the top MOSFET always turns on with each oscillator pulse. During start-up, forced continuous mode is disabled and inductor current is prevented from reversing until the LTM4637’s output voltage is in regulation. Multiphase Operation For outputs that demand more than 20A of load current, multiple LTM4637 devices can be paralleled to provide more output current without increasing input and output ripple voltage. The MODE_PLLIN pin allows the LTM4637 to be synchronized to an external clock and the internal phase-locked loop allows the LTM4637 to lock onto input clock phase as well. The fSET resistor is selected for normal frequency, then the incoming clock can synchronize the device over the specified range. See Figure 24 for a synchronizing example circuit. A multiphase power supply significantly reduces the amount of ripple current in both the input and output capacitors. The RMS input ripple current is reduced by, and the effective ripple frequency is multiplied by, the number of phases used (assuming that the input voltage is greater than the number of phases used times the output voltage). The output ripple amplitude is also reduced by the number of phases used. See Application Note 77. The LTM4637 device is an inherently current mode controlled device, so parallel modules will have good current sharing. This will balance the thermals in the design. Tie the COMP and VFB pins of each LTM4637 together to share the current evenly. Figure 24 shows a schematic of the parallel design. 4637f For more information www.linear.com/LTM4637 11 LTM4637 APPLICATIONS INFORMATION Input RMS Ripple Current Cancellation Application Note 77 provides a detailed explanation of multiphase operation. The input RMS ripple current cancellation mathematical derivations are presented, and a graph is displayed representing the RMS ripple current reduction as a function of the number of interleaved phases (see Figure 2). inductor current to about 30% to 40% of maximum load current. For output voltages from 1.5V to 1.8V, 350kHz is optimal. For output voltages from 2.5V to 5V, 500kHz is optimal. See efficiency graphs for optimal frequency set point. Limit 5V output to 15A. The LTM4637 can be synchronized from 250kHz to 800kHz with an input clock that has a high level above 900 PLL, Frequency Adjustment and Synchronization FREQ 1 RfSET = + 0.2V 10µA 500kHz / V 0.55 0.50 700 600 500 400 300 200 100 The relationship of fSET voltage to switching frequency is shown in Figure 3. For low output voltages from 0.6V to 1.2V, 250kHz operation is an optimal frequency for the best power conversion efficiency while maintaining the 0.60 SWITCHING FREQUENCY (kHz) The LTM4637 switching frequency is set by a resistor (RfSET) from the fSET pin to signal ground. A 10µA current (IFREQ) flowing out of the fSET pin through RfSET develops a voltage on fSET. RfSET can be calculated as: 800 0 0 0.5 1 1.5 fSET PIN VOLTAGE (V) 2 2.5 4637 F03 Figure 3. Relationship Between Switching Frequency and Voltage at the fSET Pin 1 PHASE 2 PHASE 3 PHASE 4 PHASE 6 PHASE RMS INPUT RIPPLE CURRENT DC LOAD CURRENT 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 DUTY CYCLE (VOUT/VIN) 4637 F02 Figure 2. Normalized Input RMS Ripple Current vs Duty Cycle for One to Six µModule Regulators (Phases) 4637f 12 For more information www.linear.com/LTM4637 LTM4637 APPLICATIONS INFORMATION 2V and a low level below 0.8V. See the Typical Applications section for synchronization examples. The LTM4637 minimum on-time is limited to approximately 100ns. Guardband the on-time to 110ns. The on-time can be calculated as: 1 V OUT t ON(MIN)= • FREQ VIN Output Voltage Tracking Output voltage tracking can be programmed externally using the TRACK/SS pin. The output can be tracked up and down with another regulator. The master regulator’s output is divided down with an external resistor divider that is the same as the slave regulator’s feedback divider to implement coincident tracking. The LTM4637 uses an accurate 60.4k resistor internally for the top feedback resistor. Figure 4 shows an example of coincident tracking. 60.4k VOUT(SLAVE) = 1+ •V R TA TRACK VTRACK is the track ramp applied to the slave’s track pin. VTRACK has a control range of 0V to 0.6V, or the internal reference voltage. When the master’s output is divided down with the same resistor values used to set the slave’s output, then the slave will coincident track with the master until it reaches its final value. The master will continue to its final value from the slave’s regulation point (see Figure 5). Voltage tracking is disabled when VTRACK is more than 0.6V. RTA in Figure 4 will be equal to RFB for coincident tracking. The TRACK/SS pin of the master can be controlled by an external ramp or the soft-start function of that regulator can be used to develop that master ramp. The LTM4637 can be used as a master by setting the ramp rate on its track pin using a soft-start capacitor. A 1.2µA current source is used to charge the soft-start capacitor. The following equation can be used: C t SOFT-START = 0.6V • SS 1.2µA Ratiometric tracking can be achieved by a few simple calculations and the slew rate value applied to the master’s TRACK/SS pin. As mentioned above, the TRACK/SS pin has a control range from 0V to 0.6V. The master’s TRACK/SS pin slew rate is directly equal to the master’s output slew rate in volts/time. The equation: MR • 60.4k = R TB SR where MR is the master’s output slew rate and SR is the slave’s output slew rate in volts/time. When coincident tracking is desired, then MR and SR are equal, thus RTB is equal to 60.4k. RTA is derived from equation: R TA = 0.6V V FB V FB V TRACK + – 60.4k RFB R TB where VFB is the feedback voltage reference of the regulator, and VTRACK is 0.6V. Since RTB is equal to the 60.4k top feedback resistor of the slave regulator in equal slew rate or coincident tracking, then RTA is equal to RFB with VFB = VTRACK. Therefore RTB = 60.4k, and RTA = 60.4k in Figure 4. In ratiometric tracking, a different slew rate maybe desired for the slave regulator. RTB can be solved for when SR is slower than MR. Make sure that the slave supply slew rate is chosen to be fast enough so that the slave output voltage will reach its final value before the master output. For example, MR = 1.5V/ms, and SR = 1.2V/ms. Then RTB = 75k. Solve for RTA to equal 51.1k. For applications that do not require tracking or sequencing, simply tie the TRACK/SS pin to INTVCC to let RUN control the turn on/off. When the RUN pin is below its threshold or the VIN undervoltage lockout, then TRACK/SS is pulled low. Overcurrent and Overvoltage Protection The LTM4637 has overcurrent protection (OCP) in a short circuit. The internal current comparator threshold folds back during a short to reduce the output current. An overvoltage condition (OVP) above 10% of the regulated output voltage will force the top MOSFET off and the bottom MOSFET on until the condition is cleared. Foldback current limiting is disabled during soft-start or tracking start-up. For more information www.linear.com/LTM4637 4637f 13 LTM4637 APPLICATIONS INFORMATION 2.2µF VIN 4.5V TO 16V CIN1 22µF 16V ×4 R2 10k SOFT-START CAPACITOR CSS VIN EXTVCC INTVCC PGOOD COMP VOUT RUN R4 75k DIFF_OUT LTM4637 fSET VOSNS+ MODE_PLLIN VOSNS– TEMP + VOUT_LCL TRACK/SS SGND VFB GND 330pF C8 470µF 6.3V ×2 C11 100µF 6.3V ×2 C4 470µF 6.3V ×2 C6 100µF 6.3V ×2 VOUT2 1.5V 20A RFB1 40.2k 2.2µF VIN 4.5V TO 16V CIN2 22µF 16V ×4 MASTER RAMP OR OUTPUT R1 10k RTB 60.4k RTA 60.4k VIN EXTVCC INTVCC PGOOD COMP VOUT RUN R3 50k LTM4637 DIFF_OUT fSET VOSNS+ MODE_PLLIN VOSNS– TEMP + VOUT_LCL TRACK/SS SGND VFB GND 330pF VOUT1 1.2V 20A RFB 60.4k 4637 F04 Figure 4. Dual Outputs (1.5V and 1.2V) with Tracking Temperature Monitoring MASTER OUTPUT OUTPUT VOLTAGE SLAVE OUTPUT Measuring the absolute temperature of a diode is possible due to the relationship between current, voltage and temperature described by the classic diode equation: V ID = IS • e D η • VT or TIME 4637A F05 Figure 5. Output Voltage Coincident Tracking Characteristics I VD = η • VT • ln D IS where ID is the diode current, VD is the diode voltage, η is the ideality factor (typically close to 1.0) and IS (saturation current) is a process dependent parameter. VT can be broken out to: 14 VT = k•T q For more information www.linear.com/LTM4637 4637f LTM4637 APPLICATIONS INFORMATION where T is the diode junction temperature in Kelvin, q is the electron charge and k is Boltzmann’s constant. VT is approximately 26mV at room temperature (298K) and scales linearly with Kelvin temperature. It is this linear temperature relationship that makes diodes suitable temperature sensors. The IS term in the equation above is the extrapolated current through a diode junction when the diode has zero volts across the terminals. The IS term varies from process to process, varies with temperature, and by definition must always be less than ID. Combining all of the constants into one term: KD = η•k q To obtain a linear voltage proportional to temperature we cancel the IS variable in the natural logarithm term to remove the IS dependency from the following equation. This is accomplished by measuring the diode voltage at two currents I1, and I2, where I1 = 10 • I2), Subtracting we get: ∆VD = T(KELVIN) • KD • ln Combining like terms, then simplifying the natural log terms yields: ∆VD = T(KELVIN) • KD • In(10) where KD = 8.62−5, and knowing ln(ID/IS) is always positive because ID is always greater than IS, leaves us with the equation that: and redefining constant: K'D = KD • ln(10) = 198µV K I VD = T(KELVIN) • KD • ln D IS yields: where VD appears to increase with temperature. It is common knowledge that a silicon diode biased with a current source has an approximate –2mV/°C temperature relationship (Figure 6), which is at odds with the equation. In fact, the IS term increases with temperature, reducing the ln(ID/IS) absolute value yielding an approximate –2mV/°C composite diode voltage slope. Solving for temperature: ∆VD = K'D • T(KELVIN) 1.0 DIODE VOLTAGE (V) ID = 100µA ID = 10µA 0.8 ∆VD 0.6 0.4 –173 I1 I − T(KELVIN) • KD • ln 2 IS IS –73 27 TEMPERATURE (°C) 127 4636 F06 T(KELVIN) = ∆VD , K'D T(KELVIN) = [°C]+ 273.15, [°C] = T(KELVIN) − 273.15 means that if we take the difference in voltage across the diode measured at two currents with a ratio of 10, the resulting voltage is 198µV per Kelvin of the junction with a zero intercept at 0 Kelvin. The diode connected PNP transistor at the TEMP pin can be used to monitor the internal temperature of the LTM4637. A general temperature monitor can be implemented by connecting a resistor between TEMP and VIN to set the current to 100µA, and then monitoring the diode voltage drop with temperature. A more accurate temperature monitor can be achieved with a circuit injecting two currents that are at a 10:1 ratio. See Figure 22 for an example. Figure 6. Diode Voltage VD vs Temperature T(°C) for Different Bias Currents 4637f For more information www.linear.com/LTM4637 15 LTM4637 APPLICATIONS INFORMATION Overtemperature Protection Thermal Considerations and Output Current Derating The internal overtemperature protection monitors the internal temperature of the module and shuts off the regulator at ~130°C to 137°C. Once the regulator cools down the regulator will restart. The thermal resistances reported in the Pin Configuration section of the data sheet are consistent with those parameters defined by JESD51-12 and are intended for use with finite element analysis (FEA) software modeling tools that leverage the outcome of thermal modeling, simulation, and correlation to hardware evaluation performed on a µModule package mounted to a hardware test board. The motivation for providing these thermal coefficients in found in JESD 51-12 (“Guidelines for Reporting and Using Electronic Package Thermal Information”). Run Enable The RUN pin is used to enable the power module or sequence the power module. The threshold is 1.25V, and the pin has an internal 5.1V Zener to protect the pin. The RUN pin can be used as an undervoltage lockout (UVLO) function by connecting a resistor divider from the input supply to the RUN pin: VUVLO = ((R1+R2)/R2) • 1.25V See Figure 1, Simplified Block Diagram. INTVCC Regulator The LTM4637 has an internal low dropout regulator from VIN called INTVCC. This regulator output has a 2.2µF ceramic capacitor internal. An additional 2.2µF ceramic capacitor is needed on this pin to ground. This regulator powers the internal controller and MOSFET drivers. The gate driver current is ~20mA for 750kHz operation. The regulator loss can be calculated as: (VIN – 5V) • 20mA = PLOSS EXTVCC external voltage source ≥ 4.7V can be applied to this pin to eliminate the internal INTVCC LDO power loss and increase regulator efficiency. A 5V supply can be applied to run the internal circuitry and power MOSFET driver. If unused, leave pin floating. EXTVCC must be less than VIN at all times during power-on and power-off sequences. Stability Compensation The LTM4637 has already been internally compensated for all output voltages. Table 5 is provided for most application requirements. LTpowerCAD is available for other control loop optimization. Many designers may opt to use laboratory equipment and a test vehicle such as the demo board to predict the µModule regulator’s thermal performance in their application at various electrical and environmental operating conditions to compliment any FEA activities. Without FEA software, the thermal resistances reported in the Pin Configuration section are, in and of themselves, not relevant to providing guidance of thermal performance; instead, the derating curves provided in this data sheet can be used in a manner that yields insight and guidance pertaining to one’s application-usage, and can be adapted to correlate thermal performance to one’s own application. The Pin Configuration section gives four thermal coefficients explicitly defined in JESD 51-12; these coefficients are quoted or paraphrased below: 1 θJA, the thermal resistance from junction to ambient, is the natural convection junction-to-ambient air thermal resistance measured in a one cubic foot sealed enclosure. This environment is sometimes referred to as “still air” although natural convection causes the air to move. This value is determined with the part mounted to a 95mm × 76mm PCB with four layers. 2 θJCbottom, the thermal resistance from junction to the bottom of the product case, is determined with all of the component power dissipation flowing through the bottom of the package. In the typical µModule regulator, the bulk of the heat flows out the bottom of the package, but there is always heat flow out into the ambient environment. As a result, this thermal resistance value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 4637f 16 For more information www.linear.com/LTM4637 LTM4637 APPLICATIONS INFORMATION 3 θJCtop, the thermal resistance from junction to top of the product case, is determined with nearly all of the component power dissipation flowing through the top of the package. As the electrical connections of the typical µModule regulator are on the bottom of the package, it is rare for an application to operate such that most of the heat flows from the junction to the top of the part. As in the case of θJCbottom, this value may be useful for comparing packages but the test conditions don’t generally match the user’s application. 4 θJB, the thermal resistance from junction to the printed circuit board, is the junction-to-board thermal resistance where almost all of the heat flows through the bottom of the µModule package and into the board, and is really the sum of the θJCbottom and the thermal resistance of the bottom of the part through the solder joints and a portion of the board. The board temperature is measured a specified distance from the package. A graphical representation of the aforementioned thermal resistances is given in Figure 7; blue resistances are contained within the µModule regulator, whereas green resistances are external to the µModule package. As a practical matter, it should be clear to the reader that no individual or sub-group of the four thermal resistance parameters defined by JESD 51-12 or provided in the Pin Configuration section replicates or conveys normal operating conditions of a µModule regulator. For example, in normal board-mounted applications, never does 100% of the device’s total power loss (heat) thermally conduct exclusively through the top or exclusively through bottom of the µModule package—as the standard defines for θJCtop and θJCbottom, respectively. In practice, power loss is thermally dissipated in both directions away from the package—granted, in the absence of a heat sink and airflow, a majority of the heat flow is into the board. Within the LTM4637, be aware there are multiple power devices and components dissipating power, with a consequence that the thermal resistances relative to different junctions of components or die are not exactly linear with respect to total package power loss. To reconcile this complication without sacrificing modeling simplicity—but also not ignoring practical realities—an approach has been taken using FEA software modeling along with laboratory testing in a controlled-environment chamber to reasonably define and correlate the thermal resistance values supplied in this data sheet: (1) Initially, FEA software is used to accurately build the mechanical geometry of the LTM4637 and the specified PCB with all of the correct material coefficients along with accurate power loss source definitions; (2) this model simulates a software-defined JEDEC environment consistent with JESD51-12 to predict power loss heat flow and temperature readings at different interfaces that enable the calculation of the JEDEC-defined thermal resistance values; (3) the model and FEA software is used to evaluate the LTM4637 with heat sink and airflow; (4) having solved for and analyzed these thermal resistance values and simulated various operating conditions in the software model, a thorough laboratory evaluation replicates the simulated conditions with thermocouples JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS JUNCTION-TO-CASE (TOP) RESISTANCE CASE (TOP)-TO-AMBIENT RESISTANCE JUNCTION-TO-BOARD RESISTANCE JUNCTION JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD (BOTTOM) RESISTANCE RESISTANCE At BOARD-TO-AMBIENT RESISTANCE 4637 F07 µMODULE DEVICE Figure 7. Graphical Representation of JESD 51-12 Thermal Coefficients 4637f For more information www.linear.com/LTM4637 17 LTM4637 APPLICATIONS INFORMATION within a controlled-environment chamber while operating the device at the same power loss as that which was simulated. The outcome of this process and due diligence yields the set of derating curves shown in this data sheet. The 1V, 2.5V and 5V power loss curves in Figures 8 to 10 can be used in coordination with the load current derating curves in Figures 11 to 20 for calculating an approximate θJA thermal resistance for the LTM4637 with various heat sinking and airflow conditions. The power loss curves are taken at room temperature, and are increased with multiplicative factors according to the ambient temperature. These approximate factors are: 1 for 40°C; 1.05 for 50°C; 1.1 for 60°C; 1.15 for 70°C; 1.2 for 80°C; 1.25 for 90°C; 1.3 for 100°C; 1.35 for 110°C and 1.4 for 120°C. The derating curves are plotted with the output current starting at 20A and the ambient temperature at ~40°C. The output voltages are 1V, 2.5V and 5V. These are chosen to include the lower, middle and higher output voltage ranges for correlating the thermal resistance. Thermal models are derived from several temperature measurements in a controlled temperature chamber along with thermal modeling analysis. The junction temperatures are monitored while ambient temperature is increased with and without airflow. The power loss increase with ambient temperature change is factored into the derating curves. The junctions are maintained at ~115°C maximum while lowering output current or power with increasing ambient temperature. The decreased output current will decrease the internal 5.0 4.5 3.5 4.0 3.0 2.5 12V TO 1V PLOSS 2.0 1.5 5V TO 1V PLOSS 1.0 7 6 3.5 3.0 2.5 12V TO 2.5V PLOSS 2.0 5V TO 2.5V PLOSS 1.5 1.0 0.5 10 5 15 OUTPUT CURRENT (A) 20 4637 F08 Figure 8. 1VOUT Power Loss 0 5 4 12V TO 5V PLOSS 3 8V TO 5V PLOSS 2 1 0.5 0 POWER LOSS (W) 4.0 POWER LOSS (W) POWER LOSS (W) 4.5 0 module loss as ambient temperature is increased. The monitored junction temperature of 115°C minus the ambient operating temperature specifies how much module temperature rise can be allowed. As an example in Figure 13 the load current is derated to ~17A at ~80°C with no air or heat sink and the power loss for the 12V to 1.0V at 17A output is about 3.36W. The 3.36W loss is calculated with the ~2.8W room temperature loss from the 12V to 1.0V power loss curve at 17A, and the 1.2 multiplying factor at 80°C ambient. If the 80°C ambient temperature is subtracted from the 115°C junction temperature, then the difference of 35°C divided by 3.36W equals a 10°C/W θJA thermal resistance. Table 2 specifies a 9.5°C/W value which is very close. Table 2 provides equivalent thermal resistances for 1.0V, 2.5V and 5V outputs with and without airflow and heat sinking. The derived thermal resistances in Tables 2 thru 4 for the various conditions can be multiplied by the calculated power loss as a function of ambient temperature to derive temperature rise above ambient, thus maximum junction temperature. Room temperature power loss can be derived from the efficiency curves in the Typical Performance Characteristics section and adjusted with the above ambient temperature multiplicative factors. The printed circuit board is a 1.6mm thick four layer board with two ounce copper for the two outer layers and one ounce copper for the two inner layers. The PCB dimensions are 95mm × 76mm. The BGA heat sinks are listed in Table 6. 0 10 5 15 OUTPUT CURRENT (A) 20 4637 F09 Figure 9. 2.5VOUT Power Loss 0 0 5 10 15 OUTPUT CURRENT (A) 20 4637 F10 Figure 10. 5VOUT Power Loss 4637f 18 For more information www.linear.com/LTM4637 LTM4637 25 25 20 20 20 15 10 5 0 10 0 70 80 90 100 110 120 130 TEMPERATURE (°C) 60 15 5 0 LFM 200 LFM 400 LFM 40 50 OUTPUT CURRENT (A) 25 OUTPUT CURRENT (A) OUTPUT CURRENT (A) APPLICATIONS INFORMATION 60 0 70 80 90 100 110 120 130 TEMPERATURE (°C) 4637 F11 20 20 0 50 60 15 10 5 0 LFM 200 LFM 400 LFM 40 IOUT(MAX) (A) 20 IOUT(MAX) (A) 25 5 70 80 90 100 110 120 TEMPERATURE (°C) 0 40 50 90 100 110 120 60 70 80 AMBIENT TEMPERATURE (°C) 25 20 20 15 10 0 0 LFM 200 LFM 400 LFM 40 50 90 100 110 120 60 70 80 AMBIENT TEMPERATURE (°C) 90 100 110 120 60 70 80 AMBIENT TEMPERATURE (°C) 10 0 0 LFM 200 LFM 400 LFM 40 4637 F17 Figure 17. 12VIN to 2.5VOUT No Heat Sink Figure 16. 5VIN to 2.5VOUT with Heat Sink 15 5 0 LFM 200 LFM 400 LFM 50 10 4637 F16 Figure 15. 5VIN to 2.5VOUT No Heat Sink 25 40 70 80 90 100 110 120 TEMPERATURE (°C) 4637 F15 IOUT(MAX) (A) IOUT(MAX) (A) Figure 14. 12VIN to 1.0VOUT with Heat Sink 0 60 15 5 0 LFM 200 LFM 400 LFM 4637 F14 5 50 Figure 13. 12VIN to 1.0VOUT No Heat Sink Figure 12. 5VIN to 1.0VOUT with Heat Sink 25 10 40 4637 F13 25 15 0 LFM 200 LFM 400 LFM 4637 F12 Figure 11. 5VIN to 1.0VOUT No Heat Sink OUTPUT CURRENT (A) 10 5 0 LFM 200 LFM 400 LFM 40 50 15 50 90 100 110 120 60 70 80 AMBIENT TEMPERATURE (°C) 4637 F18 Figure 18. 12VIN to 2.5VOUT with Heat Sink 4637f For more information www.linear.com/LTM4637 19 LTM4637 25 25 20 20 IOUT(MAX) (A) IOUT(MAX) (A) APPLICATIONS INFORMATION 15 10 5 0 15 10 5 0 LFM 200 LFM 400 LFM 0 20 30 40 50 50 70 80 90 100 110 120 AMBIENT TEMPERATURE (°C) 0 LFM 200 LFM 400 LFM 20 30 40 50 50 70 80 90 100 110 120 AMBIENT TEMPERATURE (°C) 4637 F19 4637 F20 Figure 19. 12VIN to 5VOUT No Heat Sink, EXTVCC = 5V (Limit 5V Output to 15A) Figure 20. 12VIN to 5VOUT with Heat Sink, EXTVCC = 5V (Limit 5V Output to 15A) Table 2. 1V Output DERATING CURVE VIN POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA (°C/W) Figures 11, 13 5V, 12V Figure 8 0 None 9.5 Figures 11, 13 5V, 12V Figure 8 200 None 7.5 Figures 11, 13 5V, 12V Figure 8 400 None 6.5 Figures 12, 14 5V, 12V Figure 8 0 BGA Heat Sink 8 Figures 12, 14 5V, 12V Figure 8 200 BGA Heat Sink 6.0 Figures 12, 14 5V, 12V Figure 8 400 BGA Heat Sink 5.0 POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA (°C/W) Table 3. 2.5V Output DERATING CURVE VIN Figures 15, 17 5V, 12V Figure 9 0 None 9.5 Figures 15, 17 5V, 12V Figure 9 200 None 7.5 Figures 15, 17 5V, 12V Figure 9 400 None 6.5 Figures 16, 18 5V, 12V Figure 9 0 BGA Heat Sink 8 Figures 16, 18 5V, 12V Figure 9 200 BGA Heat Sink 6.0 Figures 16, 18 5V, 12V Figure 9 400 BGA Heat Sink 5.0 Table 4. 5V Output (5V Output Connected to EXTVCC Pin) DERATING CURVE VIN POWER LOSS CURVE AIRFLOW (LFM) HEAT SINK θJA (°C/W) Figures 19 12V Figure 10 0 None 9.5 Figures 19 12V Figure 10 200 None 8.0 Figures 19 12V Figure 10 400 None 7.0 Figures 20 12V Figure 10 0 BGA Heat Sink 8.0 Figures 20 12V Figure 10 200 BGA Heat Sink 6.5 Figures 20 12V Figure 10 400 BGA Heat Sink 5.5 4637f 20 For more information www.linear.com/LTM4637 LTM4637 APPLICATIONS INFORMATION Table 5. Output Voltage Response vs Component Matrix (Refer to Figure 22) 0A to 10A Load Step COUT1 AND COUT2 CERAMIC VENDOR VALUE PART NUMBER COUT1 AND COUT2 BULK VENDOR VALUE PART NUMBER TDK 100µF 6.3V C4532X5ROJ107MZ Sanyo POSCAP 1000µF 2.5V 2R5TPD1000M5 Murata 100µF 6.3V GRM32ER60J107M CIN VENDOR VALUE PART NUMBER Sanyo 56µF 25V 25SVP56M Sanyo POSCAP 470µF 2.5V 2R5TPD470M5 TDK 22µF 16V C3216X651C226M Sanyo POSCAP 470µF 6.3V 6TPD470M5 Murata VOUT CIN CIN COUT2 (CERAMIC) CFF (V) (CERAMIC) (BULK)† AND COUT1 (BULK) (pF) 1 56µF 22µF × 4 100µF × 2, 470µF × 3 330 1.2 56µF 22µF × 4 100µF × 2, 470µF × 3 330 1.5 56µF 22µF × 4 100µF × 2, 470µF × 3 330 1.8 56µF 22µF × 4 100µF × 2, 470µF × 3 330 2.5 56µF 22µF × 4 100µF × 2, 470µF × 3 330 3.3 56µF 22µF × 4 100µF × 2, 470µF × 3 330 5 56µF 22µF × 4 100µF × 2, 470µF × 3 330 1 56µF 22µF × 4 100µF × 2, 470µF × 3 330 1.2 56µF 22µF × 4 100µF × 2, 470µF × 3 330 1.5 56µF 22µF × 4 100µF × 2, 470µF × 3 330 1.8 56µF 22µF × 4 100µF × 2, 470µF × 3 330 2.5 56µF 22µF × 4 100µF × 2, 470µF × 3 330 3.3 56µF 22µF × 4 100µF × 2, 470µF × 3 330 5 56µF 22µF × 4 100µF × 2, 470µF × 3 330 1 56µF 22µF × 4 100µF × 2, 470µF × 2 330 1.2 56µF 22µF × 4 100µF × 2, 470µF × 2 330 1.5 56µF 22µF × 4 100µF × 2, 470µF × 2 330 1.8 56µF 22µF × 4 100µF × 2, 470µF × 2 330 2.5 56µF 22µF × 4 100µF × 2, 470µF × 2 330 3.3 56µF 22µF × 4 100µF × 2, 470µF × 2 330 5 56µF 22µF × 4 100µF × 2, 470µF × 2 330 1 56µF 47 22µF × 4 100µF × 4, 470µF × 1 1.2 56µF 47 22µF × 4 100µF × 4, 470µF × 1 1.5 56µF 47 22µF × 4 100µF × 4, 470µF × 1 1.8 56µF 47 22µF × 4 100µF × 4, 470µF × 1 2.5 56µF 47 22µF × 4 100µF × 4, 470µF × 1 3.3 56µF 47 22µF × 4 100µF × 4, 470µF × 1 5 56µF 47 22µF × 4 100µF × 4, 470µF × 1 1 56µF 47 22µF × 4 100µF × 5 1.2 56µF 47 22µF × 4 100µF × 5 1.5 56µF 47 22µF × 4 100µF × 5 1.8 56µF 47 22µF × 4 100µF × 5 2.5 56µF 47 22µF × 4 100µF × 5 3.3 56µF 47 22µF × 4 100µF × 5 5 56µF 47 22µF × 4 100µF × 5 †Bulk capacitance is optional if V has very low input impedance. IN CCOMP (pF) 150 150 150 150 150 150 150 None None None None None None None None None None None None None None None None None None None None None None None None None None None None VIN (V) 5,12 5,12 5,12 5,12 5,12 5,12 7,12 5,12 5,12 5,12 5,12 5,12 5,12 7,12 5,12 5,12 5,12 5,12 5,12 5,12 7,12 5,12 5,12 5,12 5,12 5,12 5,12 7,12 5,12 5,12 5,12 5,12 5,12 5,12 7,12 DROP (mV) 65 65 65 65 65 75 100 50 50 50 65 65 70 85 75 75 70 65 65 70 100 95 95 90 95 100 125 155 100 100 100 112 125 170 225 22µF 16V GRM31CR61C226KE15L PEAK-TO-PEAK DEVIATION RECOVERY (mV) TIME (µs) 123 30 123 30 120 50 120 60 130 70 150 75 195 80 100 30 100 30 100 50 110 60 120 70 130 75 165 80 150 30 150 30 140 50 130 60 130 70 140 75 190 80 190 30 190 30 180 50 190 60 200 70 250 75 310 80 200 35 200 35 200 35 225 35 250 40 340 40 450 60 LOAD STEP (A/µs) 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 RFB (kΩ) 90.6 60.4 40.2 30.1 19.1 13.3 8.25 90.6 60.4 40.2 30.1 19.1 13.3 8.25 90.6 60.4 40.2 30.1 19.1 13.3 8.25 90.6 60.4 40.2 30.1 19.1 13.3 8.25 90.6 60.4 40.2 30.1 19.1 13.3 8.25 FREQ (kHz) 250 250 350 350 450 600 600 250 250 350 350 450 600 600 250 250 350 350 450 600 600 250 250 350 350 450 600 600 250 250 350 350 450 600 600 4637f For more information www.linear.com/LTM4637 21 LTM4637 APPLICATIONS INFORMATION Table 6. Recommended Heat Sinks HEAT SINK MANUFACTURER PART NUMBER WEBSITE AAVID Thermalloy 375424B00034G www.aavidthermalloy.com Cool Innovations 4-050503P to 4-050508P www.coolinnovations.com Safety Considerations The LTM4637 does not provide galvanic isolation from VIN to VOUT. There is no internal fuse. If required, a slow blow fuse with a rating twice the maximum input current needs to be provided to protect each unit from catastrophic failure. The fuse or circuit breaker should be selected to limit the current to the regulator during overvoltage in case of an internal top MOSFET fault. If the internal top MOSFET fails, then turning it off will not resolve the overvoltage, thus the internal bottom MOSFET will turn on indefinitely trying to protect the load. Under this fault condition, the input voltage will source very large currents to ground through the failed internal top MOSFET and enabled internal bottom MOSFET. This can cause excessive heat and board damage depending on how much power the input voltage can deliver to this system. A fuse or circuit breaker can be used as a secondary fault protector in this situation. The LTM4637 does support overvoltage protection, overcurrent protection and overtemperature protection. Layout Checklist/Example The high integration of the LTM4637 makes the PCB board layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations are still necessary. • Use large PCB copper areas for high current paths, including VIN, GND and VOUT. It helps to minimize the PCB conduction loss and thermal stress. • Place high frequency ceramic input and output capacitors next to the VIN, GND and VOUT pins to minimize high frequency noise. • Place a dedicated power ground layer underneath the unit. • To minimize the via conduction loss and reduce module thermal stress, use multiple vias for interconnection between top layer and other power layers. • Do not put vias directly on the pad, unless they are capped or plated over. • Place test points on signal pins for testing. • Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND to GND underneath the unit. • For parallel modules, tie the COMP and VFB pins together. Use an internal layer to closely connect these pins together. Figure 21 gives a good example of the recommended layout. 4637f 22 For more information www.linear.com/LTM4637 LTM4637 APPLICATIONS INFORMATION VIN CIN CONTROL CIN CONTROL GND SIGNAL GROUND CONTROL COUT COUT VOUT VOUT 4637 F21 Figure 21. Recommended PCB Layout TYPICAL APPLICATIONS INTVCC 0.1µF VCC D+ 470pF 1.8V LTC2997 D– VIN 4.5V TO 20V VREF GND VPTAT 4mV/K INTVCC CIN 22µF 25V ×4 2.2µF C7 R1 10k 0.1µF VIN EXTVCC INTVCC PGOOD COMP VOUT RUN R3 CONTINUOUS MODE 75k LTM4637 DIFF_OUT fSET VOSNS+ MODE_PLLIN VOSNS– TEMP + VOUT_LCL TRACK/SS SGND GND VFB CFF 330pF COUT1* 470µF 6.3V ×2 COUT2* 100µF 6.3V ×2 VOUT 1.5V 20A RFB 40.2k *SEE TABLE 5 Figure 22. 4.5V to 20VIN, 1.5V at 20A Design For more information www.linear.com/LTM4637 4627 F22 4637f 23 24 R1 200k 500kHz C14 1µF SET MOD OUT1 LTC6908-1 OUT2 GND V+ INTVCC VIN 5V TO 16V R2 10k C9 22µF 16V C10 22µF 16V C13 0.1µF For more information www.linear.com/LTM4637 C1 22µF 16V C2 22µF 16V 100k 100k VIN DIFF_OUT RUN SGND GND VFB MODE_PLLIN TEMP VOSNS VOSNS– fSET + VOUT_LCL TRACK/SS LTM4637 VOUT 2.2µF VFB COMP GND EXTVCC INTVCC PGOOD SGND VOSNS VOSNS– VIN TEMP MODE_PLLIN fSET + DIFF_OUT RUN LTM4637 VOUT_LCL VOUT EXTVCC INTVCC PGOOD TRACK/SS COMP INTVCC Figure 23. 3.3V at 40A, Two Parallel Outputs with 2-Phase Operation CLOCK SYNC 180 PHASE C3 22µF 16V CLOCK SYNC 0 PHASE C7 22µF 16V 2.2µF 4627 F23 + C4 220µF 6.3V RFB1 6.65k 330pF + C6 100µF 6.3V ×2 C8 220µF 6.3V C11 100µF 6.3V ×2 3.3V 40A LTM4637 TYPICAL APPLICATIONS 4637f LTM4637 TYPICAL APPLICATIONS 2.2µF VIN 5V TO 16V C20 22µF 16V INTVCC C22 22µF 16V C28 R1 10k VIN 0.1µF VOUT COMP RUN 4-PHASE CLOCK V C2 1µF + VOSNS+ MODE_PLLIN VOSNS– TEMP OUT1 OUT2 SGND VFB GND SET GND 470pF C21 470µF 6.3V ×2 C24 100µF 6.3V ×2 RFB2 15k R2 200k 2.2µF LTC6902 MOD DIV PH DIFF_OUT LTM4637 fSET INTVCC + VOUT_LCL TRACK/SS 50k VOUT 1.2V AT 80A EXTVCC INTVCC PGOOD 22µF 25V C14 22µF 16V C18 22µF 16V VIN OUT4 EXTVCC INTVCC PGOOD VOUT COMP VOUT_LCL TRACK/SS OUT3 RUN 50k DIFF_OUT LTM4637 fSET VOSNS+ MODE_PLLIN VOSNS– TEMP SGND + C15 470µF 6.3V ×2 C18 100µF 6.3V ×2 VFB GND 2.2µF C7 22µF 16V C9 22µF 16V VIN EXTVCC INTVCC PGOOD VOUT COMP 50k TRACK/SS VOUT_LCL RUN DIFF_OUT LTM4637 fSET VOSNS+ MODE_PLLIN VOSNS– TEMP SGND + C8 470µF 6.3V ×2 C11 100µF 6.3V ×2 VFB GND 2.2µF 22µF 25V C3 22µF 16V C1 22µF 16V VIN EXTVCC INTVCC PGOOD VOUT COMP 50k TRACK/SS VOUT_LCL RUN DIFF_OUT LTM4637 fSET VOSNS+ MODE_PLLIN VOSNS– TEMP SGND GND + C4 470µF 6.3V ×2 C6 100µF 6.3V ×2 VFB 4637 F24 Figure 24. 1.2V, 80A, Current Sharing with 4-Phase Operation 4637f For more information www.linear.com/LTM4637 25 LTM4637 PACKAGE DESCRIPTION PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY. Pin Assignment Table (Arranged by Pin Number) PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION A1 VIN B1 VIN C1 VIN D1 GND E1 GND F1 GND A2 VIN B2 VIN C2 VIN D2 GND E2 GND F2 GND A3 VIN B3 VIN C3 VIN D3 GND E3 GND F3 GND A4 VIN B4 VIN C4 VIN D4 GND E4 GND F4 GND A5 VIN B5 VIN C5 VIN D5 GND E5 GND F5 GND A6 VIN B6 VIN C6 VIN D6 GND E6 GND F6 GND A7 INTVCC B7 GND C7 GND D7 – E7 GND F7 GND A8 MODE_PLLIN B8 – C8 – D8 GND E8 – F8 GND A9 TRACK/SS B9 GND C9 GND D9 INTVCC E9 GND F9 GND A10 RUN B10 – C10 MTP3 D10 TEMP E10 – F10 – A11 COMP B11 MTP2 C11 MTP4 D11 MTP6 E11 – F11 PGOOD A12 MTP1 B12 fSET C12 MTP5 D12 MTP7 E12 EXTVCC F12 VFB PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION PIN ID FUNCTION G1 GND H1 GND J1 VOUT K1 VOUT L1 VOUT M1 VOUT G2 GND H2 GND J2 VOUT K2 VOUT L2 VOUT M2 VOUT G3 GND H3 GND J3 VOUT K3 VOUT L3 VOUT M3 VOUT G4 GND H4 GND J4 VOUT K4 VOUT L4 VOUT M4 VOUT G5 GND H5 GND J5 VOUT K5 VOUT L5 VOUT M5 VOUT G6 GND H6 GND J6 VOUT K6 VOUT L6 VOUT M6 VOUT G7 GND H7 GND J7 VOUT K7 VOUT L7 VOUT M7 VOUT G8 GND H8 GND J8 VOUT K8 VOUT L8 VOUT M8 VOUT G9 GND H9 GND J9 VOUT K9 VOUT L9 VOUT M9 VOUT G10 – H10 – J10 VOUT K10 VOUT L10 VOUT M10 VOUT G11 SGND H11 SGND J11 – K11 VOUT L11 VOUT M11 VOUT G12 PGOOD H12 SGND J12 VOSNS+ K12 DIFF_OUT L12 VOUT_LCL M12 VOSNS– PACKAGE PHOTO 4637f 26 For more information www.linear.com/LTM4637 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representaFor more information www.linear.com/LTM4637 tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 6.9850 5.7150 4.4450 3.1750 1.9050 0.6350 0.0000 0.6350 1.9050 3.1750 4.4450 5.7150 6.9850 3.1750 3.54 BSC 0.630 SUGGESTED PCB LAYOUT TOP VIEW 1.9050 PACKAGE TOP VIEW 0.6350 0.0000 0.6350 4 1.9050 PAD 1 CORNER 15 BSC 3.1750 2.18 BSC 4.4450 15 BSC Y 0.630 X 8.42 BSC 3.29 BSC DETAIL B 4.22 – 4.42 DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE LAND DESIGNATION PER JESD MO-222, SPP-010 SYMBOL TOLERANCE aaa 0.15 bbb 0.10 eee 0.05 6. THE TOTAL NUMBER OF PADS: 133 5. PRIMARY DATUM -Z- IS SEATING PLANE 4 3 2. ALL DIMENSIONS ARE IN MILLIMETERS 3 PADS SEE NOTES M TRAY PIN 1 BEVEL COMPONENT PIN “A1” 1.27 BSC 13.97 BSC 0.12 – 0.28 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994 DETAIL A 0.27 – 0.37 SUBSTRATE eee S X Y DETAIL B 0.630 ±0.025 SQ. 133x aaa Z 3.95 – 4.05 MOLD CAP Z 5.7150 4.4450 5.7150 6.9850 (Reference LTC DWG # 05-08-1906 Rev Ø) bbb Z aaa Z 6.9850 LGA Package 133-Lead (15mm × 15mm × 4.32mm) L K G F E LTMXXXXXX µModule PACKAGE BOTTOM VIEW H D C B LGA 133 0811 REV Ø A DETAIL A PACKAGE IN TRAY LOADING ORIENTATION J 13.97 BSC 1 2 3 4 5 6 7 8 9 10 11 12 C(0.30) PAD 1 LTM4637 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 4637f 27 LTM4637 TYPICAL APPLICATION 1.8V at 20A Design 5V CIN 22µF 25V ×4 C7 0.1µF R1 10k R3 75k CONTINUOUS MODE VIN EXTVCC INTVCC PGOOD COMP VOUT TRACK/SS VOUT_LCL RUN DIFF_OUT LTM4637 fSET VOSNS+ MODE_PLLIN VOSNS– TEMP SGND GND VFB 47pF C4 100µF 6.3V X5R ×2 + C6 470µF 6V VOUT 1.8V 20A RFB 30.1k 4627 TA02 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTM4609 Buck-Boost DC/DC µModule Family All Pin Compatible; Up to 5A; Up to 36VIN, 34VOUT 15mm × 15mm × 2.82mm LTM4612 Ultralow Noise High VOUT DC/DC µModule Regulator 5A, 5V ≤ VIN ≤ 36V, 3.3V ≤ VOUT ≤ 15V, 15mm × 15mm × 2.82mm Package LTM4627 15A DC/DC µModule Regulator 4.5V ≤ VIN ≤ 20V, 0.6V ≤ VOUT ≤ 5V, LGA and BGA Packages LTM4620 Dual 13A, Single 26A DC/DC µModule Regulator Up to 100A with Four in Parallel, 4.5V ≤ VIN ≤ 16V, 0.6V ≤ VOUT ≤ 2.5V DESIGN RESOURCES SUBJECT DESCRIPTION µModule Design and Manufacturing Resources Design: • Selector Guides • Demo Boards and Gerber Files • Free Simulation Tools µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet. Manufacturing: • Quick Start Guide • PCB Design, Assembly and Manufacturing Guidelines • Package and Board Level Reliability 2. Search using the Quick Power Search parametric table. TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products. Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that offer essential functions, including power supply monitoring, supervision, margining and sequencing, and feature EEPROM for storing user configurations and fault logging. 4637f 28 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTM4637 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTM4637 LT 0413 • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2013