SN54LVT646, SN74LVT646 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS140D – MAY 1992 – REVISED JULY 1995 D D D D D D D description These bus transceivers and registers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. SN54LVT646 . . . JT OR W PACKAGE SN74LVT646 . . . DB, DW, OR PW PACKAGE (TOP VIEW) CLKAB SAB DIR A1 A2 A3 A4 A5 A6 A7 A8 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC CLKBA SBA OE B1 B2 B3 B4 B5 B6 B7 B8 SN54LVT646 . . . FK PACKAGE (TOP VIEW) DIR SAB CLKAB NC VCC CLKBA SBA D State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Bus-Hold Data Inputs Eliminate the Need for External Pullup Resistors Support Live Insertion Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Packages, and Ceramic (JT) DIPs A1 A2 A3 NC A4 A5 A6 5 4 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 19 11 12 13 14 15 16 17 18 OE B1 B2 NC B3 B4 B5 A7 A8 GND NC B8 B7 B6 D NC – No internal connection The ’LVT646 consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ′LVT646. Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The direction control (DIR) determines which bus receives data when OE is low. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LVT646, SN74LVT646 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS140D – MAY 1992 – REVISED JULY 1995 description (continued) Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVT646 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LVT646 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74LVT646 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE INPUTS DATA I/Os OE DIR CLKAB CLKBA SAB SBA A1– A8 B1– B8 X X ↑ X X X Input Unspecified† Input OPERATION OR FUNCTION Store A, B unspecified† Store B, A unspecified† X X X ↑ X X Unspecified† H X ↑ ↑ X X Input Input Store A and B data H X H or L H or L X X Input disabled Input disabled Isolation, hold storage L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus L H X X L X Input Output Real-time A data to B bus L H H or L X H X Input Output Stored A data to B bus † The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition of the clock inputs. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVT646, SN74LVT646 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 21 OE L 3 DIR L 1 23 CLKAB CLKBA X X 2 SAB X BUS B BUS A BUS A BUS B SCBS140D – MAY 1992 – REVISED JULY 1995 22 SBA L 21 OE L 3 DIR H REAL-TIME TRANSFER BUS B TO BUS A 3 DIR X X X 1 23 CLKAB CLKBA X ↑ X ↑ ↑ ↑ 2 SAB X X X 23 CLKBA X 2 SAB L 22 SBA X BUS A BUS B REAL-TIME TRANSFER BUS A TO BUS B BUS B BUS A 21 OE X X H 1 CLKAB X 22 SBA X X X STORAGE FROM A, B, OR A AND B 21 OE L L 3 DIR L H 1 CLKAB X H or L 23 CLKBA H or L X 2 SAB X H 22 SBA H X TRANSFER STORED DATA TO A AND/OR B Figure 1. Bus-Management Functions Pin numbers shown are for the DB, DW, JT, PW, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LVT646, SN74LVT646 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS140D – MAY 1992 – REVISED JULY 1995 logic symbol† 21 OE DIR CLKBA SBA CLKAB SAB A1 3 23 22 1 G3 3 EN1 [BA] 3 EN2 [AB] C4 G5 C6 G7 2 ≥1 4 1 5 6D 7 1 5 4D 5 A4 A5 A6 A7 A8 2 7 19 6 18 7 17 8 16 9 15 10 14 11 13 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, PW, and W packages. 4 B1 1 ≥1 A2 A3 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 B2 B3 B4 B5 B6 B7 B8 SN54LVT646, SN74LVT646 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS140D – MAY 1992 – REVISED JULY 1995 logic diagram (positive logic) OE DIR CLKBA SBA CLKAB SAB 21 3 23 22 1 2 One of Eight Channels 1D C1 A1 4 20 B1 1D C1 To Seven Other Channels Pin numbers shown are for the DB, DW, JT, PW, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LVT646, SN74LVT646 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS140D – MAY 1992 – REVISED JULY 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . – 0.5 V to 7 V Current into any output in the low state, IO: SN54LVT646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVT646 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVT646 . . . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVT646 . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . . 0.65 W DW package . . . . . . . . . . . . . . . . . . . 1.7 W PW package . . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions (see Note 4) SN54LVT646 SN74LVT646 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 0.8 V Input voltage 5.5 5.5 V IOH IOL High-level output current – 24 – 32 mA Low-level output current 48 64 mA ∆t /∆v Input transition rise or fall rate 10 ns / V 85 °C High-level input voltage 2 Outputs enabled TA Operating free-air temperature NOTE 4: Unused control inputs must be held high or low to prevent them from floating. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2 10 – 55 125 – 40 V V SN54LVT646, SN74LVT646 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS140D – MAY 1992 – REVISED JULY 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VCC = 2.7 V, VCC = MIN to MAX‡, II = –18 mA IOH = –100 µA VCC = 2.7 V, IOH = – 8 mA IOH = – 24 mA VCC = 3 V VCC = 2 2.7 7V VOL VCC = 3 V VCC = 3.6 V, VCC = 0 or MAX‡, II VCC = 3.6 V Ioff VCC = 0, II(hold) I(h ld) VCC = 3 V IOZH IOZL VCC = 3.6 V, VCC = 3.6 V, ICC SN54LVT646 TYP† MAX TEST CONDITIONS VCC = 3.6 V, VI = VCC or GND MIN –1.2 VCC – 0.2 2.4 –1.2 VCC – 0.2 2.4 IOH = – 32 mA IOL = 100 µA 0.2 IOL = 24 mA IOL = 16 mA 0.5 0.5 0.4 0.4 IOL = 32 mA IOL = 48 mA 0.5 0.5 VI = 5.5 V VI = 5.5 V VI = VCC VI = 0 VI or VO = 0 to 4.5 V VI = 0.8 V VI = 2 V VO = 3 V V 0.55 0.55 Control inputs A or B ports§ ±1 ±1 10 10 100 20 1 1 –5 –5 ± 100 A or B ports 75 75 –75 –75 –1 µA –1 µA 0.13 0.39 0.13 0.19 Outputs low 8.8 14 8.8 12 0.13 0.39 0.13 0.19 VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = 3 V or 0 VO = 3 V or 0 µA 1 Outputs high Outputs disabled µA µA 1 VO = 0.5 V IO = 0, V 2 0.2 IOL = 64 mA VI = VCC or GND UNIT V 2 ∆ICC¶ Cio SN74LVT646 TYP† MAX MIN 0.3 0.2 mA mA 4.5 4.5 pF 11 11 pF † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. § Unused terminals at VCC or GND ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54LVT646, SN74LVT646 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS140D – MAY 1992 – REVISED JULY 1995 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) SN54LVT646 VCC = 3.3 V ± 0.3 V fclock tw tsu Setu time, A or B before CLKAB↑ or Setup CLKBA↑ th Hold time, A or B after CLKAB↑ or CLKBA↑ VCC = 2.7 V VCC = 2.7 V MIN MAX MIN MAX MIN MAX MIN MAX 0 150 0 150 0 150 0 150 Clock frequency Pulse duration, CLK high or low SN74LVT646 VCC = 3.3 V ± 0.3 V 3.3 3.3 3.3 3.3 Data high 1.5 1.5 1.3 1.3 Data low 2.5 3.0 2 2.4 0.9 0.9 0.4 0.4 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 2) SN54LVT646 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ SN74LVT646 VCC = 2.7 V MAX MIN MAX 150 CLKBA or CLKAB A or B A or B B or A SBA or SAB‡ A or B OE A or B OE A or B DIR A or B VCC = 3.3 V ± 0.3 V MIN TYP† MAX VCC = 2.7 V MIN MAX 150 MHz 1.2 5.9 6.9 1.8 3.8 5.7 6.7 1.2 5.9 6.6 2.1 3.8 5.7 6.4 0.8 4.9 5.6 1.3 2.8 4.7 5.4 0.6 4.8 5.5 1 2.7 4.6 5.3 1 6.4 7.4 1.4 3.7 6.2 7.2 1 6.4 7 1.4 3.8 6.2 6.8 0.6 6 7.4 1 3 5.8 7.2 0.6 6.2 7.5 1 3.2 6 7.3 1.4 6.7 7.1 2.3 4.3 6.5 6.9 1.4 6.4 6.5 2.2 3.8 5.8 5.9 0.6 6.7 7.7 1 3.4 6.5 7.5 0.8 6.5 7.3 1.2 3.4 6.3 7.1 0.8 7.4 8.3 1.7 4.1 7.2 DIR A or B tPLZ 1 6.7 7 1.5 3.5 5.8 † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ These parameters are measured with the internal output state of the storage register opposite to that of the bus input. 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT 8.1 6.3 ns ns ns ns ns ns ns SN54LVT646, SN74LVT646 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS140D – MAY 1992 – REVISED JULY 1995 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 500 Ω 2.7 V LOAD CIRCUIT FOR OUTPUTS 1.5 V Timing Input 0V tw tsu 2.7 V Input 1.5 V th 2.7 V 1.5 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 1.5 V 0V 1.5 V 1.5 V VOL tPLH tPHL VOH Output 1.5 V 1.5 V VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 6 V (see Note B) VOH Output 1.5 V tPZL tPHL tPLH 2.7 V Output Control Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V tPZH 3V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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