SN54LVTH652, SN74LVTH652 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS706D – AUGUST 1997 – REVISED APRIL 1999 D D D D D D D description These bus transceivers and registers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. SN54LVTH652 . . . JT OR W PACKAGE SN74LVTH652 . . . DB, DGV, DW, OR PW PACKAGE (TOP VIEW) CLKAB SAB OEAB A1 A2 A3 A4 A5 A6 A7 A8 GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC CLKBA SBA OEBA B1 B2 B3 B4 B5 B6 B7 B8 SN54LVTH652 . . . FK PACKAGE (TOP VIEW) OEAB SAB CLKAB NC VCC CLKBA SBA D State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Ioff and Power-Up 3-State Support Hot Insertion Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC ) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Thin Very Small-Outline (DGV) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Ceramic (JT) DIPs A1 A2 A3 NC A4 A5 A6 5 4 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 19 11 12 13 14 15 16 17 18 OEBA B1 B2 NC B3 B4 B5 A7 A8 GND NC B8 B7 B6 D NC – No internal connection The ’LVTH652 devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between real-time and stored data. A low input selects real-time data and a high input selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ’LVTH652 devices. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LVTH652, SN74LVTH652 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS706D – AUGUST 1997 – REVISED APRIL 1999 description (continued) Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input; therefore, when all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH652 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LVTH652 is characterized for operation from –40°C to 85°C. FUNCTION TABLE DATA I/O† INPUTS OPERATION OR FUNCTION OEAB OEBA CLKAB CLKBA SAB SBA A1–A8 B1–B8 L H H or L H or L X X Input Input Isolation L H ↑ ↑ X X Input Input Store A and B data X H ↑ H or L X Input Unspecified‡ Store A, hold B H H ↑ ↑ X X‡ X Store A in both registers X H or L ↑ X Input Hold A, store B L L ↑ ↑ X X X‡ Input Unspecified‡ Output L Output Input Store B in both registers L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus H H X X L X Input Output Real-time A data to B bus H H H or L X H X Input Output Stored A data to B bus Output Stored A data to B bus and stored B data to A bus H L H or L H or L H H Output † The data-output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always are enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs. ‡ Select control = L; clocks can occur simultaneously. Select control = H; clocks must be staggered to load both registers. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVTH652, SN74LVTH652 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 3 21 OEAB OEBA L L 1 23 2 CLKAB CLKBA SAB X X X BUS B BUS A BUS A BUS B SCBS706D – AUGUST 1997 – REVISED APRIL 1999 22 SBA L 3 21 OEAB OEBA H H 21 1 X L L H X H ↑ X ↑ 23 2 CLKBA SAB X ↑ ↑ X X X 2 SAB L 22 SBA X BUS B BUS A BUS A 3 OEAB OEBA CLKAB 23 CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A 1 CLKAB X 22 3 SBA 21 OEAB OEBA X X X H L 1 23 2 22 CLKAB CLKBA SAB SBA H or L H or L H H TRANSFER STORED DATA TO A AND/OR B STORAGE FROM A, B, OR A AND B Pin numbers shown are for the DB, DGV, DW, JT, PW, and W packages. Figure 1. Bus-Management Functions POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LVTH652, SN74LVTH652 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS706D – AUGUST 1997 – REVISED APRIL 1999 logic symbol† OEBA OEAB CLKBA SBA CLKAB SAB A1 21 3 23 22 1 EN1 [BA] EN2 [AB] C4 G5 2 C6 G7 4 ≥1 5 1 6D 4D 20 B1 5 1 7 ≥1 2 1 7 A2 A3 A4 A5 A6 A7 A8 5 19 6 18 7 17 8 16 9 15 10 14 11 13 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DGV, DW, JT, PW, and W packages. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 B2 B3 B4 B5 B6 B7 B8 SN54LVTH652, SN74LVTH652 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS706D – AUGUST 1997 – REVISED APRIL 1999 logic diagram (positive logic) OEBA OEAB CLKBA SBA CLKAB SAB 21 3 23 22 1 2 One of Eight Channels 1D C1 A1 4 20 B1 1D C1 To Seven Other Channels Pin numbers shown are for the DB, DGV, DW, JT, PW, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LVTH652, SN74LVTH652 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS706D – AUGUST 1997 – REVISED APRIL 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Current into any output in the low state, IO: SN54LVTH652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVTH652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVTH652 . . . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVTH652 . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) SN54LVTH652 SN74LVTH652 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 0.8 V Input voltage 5.5 5.5 V IOH IOL High-level output current –24 –32 mA Low-level output current 48 64 mA ∆t /∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 High-level input voltage 2 Outputs enabled 2 10 V 10 –40 ns/V µs/V 200 125 V 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVTH652, SN74LVTH652 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS706D – AUGUST 1997 – REVISED APRIL 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VCC = 2.7 V, VCC = 2.7 V to 3.6 V, II = –18 mA IOH = –100 µA VCC = 2.7 V, IOH = –8 mA IOH = –24 mA VCC = 3 V VCC = 2 2.7 7V VOL VCC = 3 V Control inputs VCC = 3.6 V, VCC = 0 or 3.6 V, II A or B ports‡ Ioff II(hold) ( ) VCC = 3.6 V VCC = 0, A or B ports SN54LVTH652 TYP† MAX TEST CONDITIONS VCC = 3 V MIN –1.2 VCC–0.2 2.4 –1.2 VCC–0.2 2.4 IOH = –32 mA IOL = 100 µA UNIT V V 2 2 0.2 0.2 IOL = 24 mA IOL = 16 mA 0.5 0.5 0.4 0.4 IOL = 32 mA IOL = 48 mA 0.5 0.5 V 0.55 IOL = 64 mA VI = VCC or GND 0.55 VI = 5.5 V VI = 5.5 V VI = VCC VI = 0 VI or VO = 0 to 4.5 V VI = 0.8 V VI = 2 V VI = 0 to 3.6 V ±1 ±1 10 10 20 20 1 1 –5 –5 ±100 75 75 –75 –75 µA µA µA ±500 IOZPU VCC = 3.6 V§ VCC = 0 to 1.5 V, VO = 0.5 to 3 V, OE/OE = don’t care IOZPD VCC = 1.5 V to 0, VO = 0.5 to 3 V, OE/OE = don’t care ICC VCC = 3.6 3 6 V, V IO = 0, 0 VI = VCC or GND ∆ICC¶ VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = 3 V or 0 VO = 3 V or 0 Outputs high Cio SN74LVTH652 TYP† MAX MIN Outputs low Outputs disabled ±100∗ ±100 µA ±100∗ ±100 µA 0.19 0.19 5 5 0.19 0.19 0.2 0.2 mA mA 4 4 pF 9 9 pF ∗ On products compliant to MIL-PRF-38535, this parameter is not production tested. † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ Unused terminals at VCC or GND § This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54LVTH652, SN74LVTH652 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS706D – AUGUST 1997 – REVISED APRIL 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) SN54LVTH652 VCC = 3.3 V ± 0.3 V MIN fclock tw Clock frequency MAX VCC = 2.7 V MIN 150 Pulse duration, CLK high or low SN74LVTH652 VCC = 3.3 V ± 0.3 V MAX MIN 150 MAX VCC = 2.7 V MIN 150 3.3 3.3 3.3 Data high 1.3 1.6 1.2 1.5 Data low 1.9 2.6 1.6 2.2 1.2 1.2 0.8 0.8 tsu Setup time,, A or B before CLKAB↑ or CLKBA↑ th Hold time, A or B after CLKAB↑ or CLKBA↑ MAX 150 3.3 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 2) SN54LVTH652 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ VCC = 2.7 V MAX 150 CLKBA or CLKAB A or B A or B B or A SBA or SAB‡ A or B OEBA A OEBA A OEAB B OEAB B SN74LVTH652 MIN MAX 150 VCC = 3.3 V ± 0.3 V MIN VCC = 2.7 V TYP† MAX 150 MAX 150 MHz 1.7 5 5.9 1.8 3.1 4.7 5.6 1.7 5 5.9 1.8 3.1 4.7 5.6 1.2 3.7 4.3 1.3 2.3 3.5 4.1 1.2 3.7 4.3 1.3 2.4 3.5 4.1 1.4 5.2 6.3 1.5 3.1 4.9 6 1.4 5.2 6.3 1.5 3.4 4.9 6 1 5.4 6.7 1.1 2.9 5.2 6.5 1 5.4 6.7 1.1 3.1 5.2 6.5 2.2 5.9 6.5 2.3 3.5 5.5 6.1 2.2 5.9 6.3 2.3 3.7 5.5 5.9 1.2 4.9 5.9 1.3 3 4.7 5.7 1.2 4.9 5.9 1.3 3.3 4.7 5.7 1.4 5.8 7 1.5 3.6 5.6 6.7 tPLZ 1.4 5.9 6.6 1.5 3.7 5.6 † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ These parameters are measured with the internal output state of the storage register opposite that of the bus input. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 8 MIN POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT 6.3 ns ns ns ns ns ns ns SN54LVTH652, SN74LVTH652 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS706D – AUGUST 1997 – REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT 1.5 V Timing Input 0V tw tsu 2.7 V Input 1.5 V 1.5 V th 2.7 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 1.5 V 0V tPLH tPHL VOH 1.5 V Output 1.5 V VOL tPHL tPLH VOH Output 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 2.7 V Output Control Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) 1.5 V 1.5 V 0V tPZL tPLZ 3V 1.5 V tPZH VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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