SN54ABT652, SN74ABT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS070D – JULY 1991 – REVISED JULY 1994 • • • • • • State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Drive Outputs (– 32-mA IOH, 64-mA IOL ) Package Options Include Plastic Small-Outline ((DW)) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs SN54ABT652 . . . JT PACKAGE SN74ABT652 . . . DB, DW, OR NT PACKAGE (TOP VIEW) CLKAB SAB OEAB A1 A2 A3 A4 A5 A6 A7 A8 GND 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC CLKBA SBA OEBA B1 B2 B3 B4 B5 B6 B7 B8 OEAB SAB CLKAB NC VCC CLKBA SBA A1 A2 A3 NC A4 A5 A6 4 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 OEBA B1 B2 NC B3 B4 B5 A7 A8 GND NC B8 B7 B6 Output-enable (OEAB and OEBA) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select whether real-time or stored data is transferred. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input selects real-time data, and a high input selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ′ABT652. 24 2 SN54ABT652 . . . FK PACKAGE (TOP VIEW) description These devices consist of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. 1 NC – No internal connection Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) inputs regardless of the select- or enable-control pins. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state. To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver (B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver (A to B). The SN74ABT652 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. Copyright 1994, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–1 SN54ABT652, SN74ABT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS070D – JULY 1991 – REVISED JULY 1994 description (continued) The SN54ABT652 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ABT652 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE DATA I/O† INPUTS OEAB OEBA CLKAB CLKBA L H H or L L H ↑ X H H OPERATION OR FUNCTION SAB SBA A1 THRU A8 B1 THRU B8 H or L X X Input Input Isolation ↑ X X Input Input Store A and B data ↑ H or L X Input Unspecified‡ Store A, hold B H ↑ ↑ X X‡ X Input Output Store A in both registers L X H or L ↑ X Unspecified‡ Input Hold A, store B L L ↑ ↑ X X X‡ Output Input Store B in both registers L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus H H X X L X Input Output Real-time A data to B bus H H H or L X H X Input Output Stored A data to B bus H L H or L H or L H H Output Output Stored A data to B bus and stored B data to A bus † The data output functions may be enabled or disabled by a variety of level combinations at the OEAB or OEBA inputs. Data input functions are always enabled; i.e., data at the bus pins is stored on every low-to-high transition on the clock inputs. ‡ Select control = L; clocks can occur simultaneously. Select control = H; clocks must be staggered in order to load both registers. 2–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT652, SN74ABT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS 3 21 OEAB OEBA L L 1 23 2 CLKAB CLKBA SAB X X X BUS B BUS A BUS A BUS B SCBS070D – JULY 1991 – REVISED JULY 1994 22 SBA L 3 21 OEAB OEBA H H 21 OEBA H X H 1 23 2 CLKAB CLKBA SAB ↑ X ↑ X ↑ ↑ X X X 2 SAB L 22 SBA X BUS B BUS A BUS A 3 OEAB X L L 23 CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A 1 CLKAB X 22 SBA X X X STORAGE FROM A, B, OR A AND B 3 OEAB H 21 OEBA L 1 CLKAB 23 CLKBA 2 SAB 22 SBA L L H H TRANSFER STORED DATA TO A AND/OR B Figure 1. Bus-Management Functions Pin numbers shown are for the DB, DW, JT, and NT packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3 SN54ABT652, SN74ABT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS070D – JULY 1991 – REVISED JULY 1994 logic symbol† OEBA OEAB CLKBA SBA CLKAB SAB A1 21 3 23 22 1 EN1 [BA] EN2 [AB] C4 G5 2 C6 G7 4 ≥1 1 7 1 A3 A4 A5 A6 A7 A8 ≥1 B1 2 7 5 19 6 18 7 17 8 16 9 15 10 14 11 13 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, and NT packages. 2–4 20 5 1 6D A2 4D 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 B2 B3 B4 B5 B6 B7 B8 SN54ABT652, SN74ABT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS070D – JULY 1991 – REVISED JULY 1994 logic diagram (positive logic) OEBA OEAB CLKBA SBA CLKAB SAB 21 3 23 22 1 2 One of Eight Channels 1D C1 A1 4 20 B1 1D C1 To Seven Other Channels Pin numbers shown are for the DB, DW, JT, and NT packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–5 SN54ABT652, SN74ABT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS070D – JULY 1991 – REVISED JULY 1994 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . – 0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT652 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . . 0.65 W DW package . . . . . . . . . . . . . . . . . . . 1.7 W NT package . . . . . . . . . . . . . . . . . . . . 1.3 W Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils, except for the NT package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B. recommended operating conditions (see Note 3) SN54ABT652 SN74ABT652 MIN MAX MIN MAX 4.5 5.5 4.5 5.5 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage IOH IOL High-level output current VCC – 24 Low-level output current 48 64 mA ∆t /∆v Input transition rise or fall rate 5 5 ns / V 85 °C High-level input voltage 2 0.8 Input voltage 0 TA Operating free-air temperature NOTE 3: Unused or floating pins (input or I/O) must be held high or low. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 2–6 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 – 55 125 V 0.8 0 – 40 V VCC – 32 V V mA SN54ABT652, SN74ABT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS070D – JULY 1991 – REVISED JULY 1994 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = – 3 mA VCC = 5 V, VCC = 4 4.5 5V SN54ABT652 MIN –1.2 MAX SN74ABT652 MIN –1.2 2.5 IOH = – 3 mA IOH = – 24 mA 3 3 3 2 2 IOH = – 32 mA IOL = 48 mA 2* VCC = 5.5 V,, VI = VCC or GND IOZH‡ IOZL‡ VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.5 V Ioff ICEX IO§ VCC = 0, VCC = 5.5 V, VI or VO ≤ 4.5 V VO = 5.5 V Outputs high VCC = 5.5 V, VO = 2.5 V 5 5 V, V VCC = 5.5 VI = VCC or GND 0 IO = 0, IOL = 64 mA V V 0.55 0.55* A or B ports 0.55 ±1 ±1 ±1 ±100 ±100 ±100 Control inputs µA 50 50 50 µA – 50 – 50 µA ±100 µA 50 –100 V – 50 ±100 – 50 UNIT 2 0.55 II MAX –1.2 2.5 VCC = 4 4.5 5V –180 50 – 50 –180 – 50 50 µA –180 mA Outputs high 250 250 250 µA Outputs low 30 30 30 mA 250 250 250 µA 1.5 1.5 1.5 mA Outputs disabled ∆ICC¶ VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND Ci VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V Cio TA = 25°C TYP† MAX 2.5 VOL ICC MIN Control inputs A or B ports 7 pF 12 pF * On products compliant to MIL-STD-883, Class B, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ The parameters IOZH and IOZL include the input leakage current. § Not more than one output should be tested at a time, and the duration of the test should not exceed one second. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 2) VCC = 5 V, TA = 25°C SN54ABT652 SN74ABT652 MIN MAX MIN MAX MIN MAX 125 0 125 0 125 UNIT fclock tw Clock frequency 0 Pulse duration, CLK high or low 4 4 4 ns tsu th Setup time, A or B before CLKAB↑ or CLKBA↑ 3.5 3.5 3.5 ns 0 0 0 ns Hold time, A or B after CLKAB↑ or CLKBA↑ MHz PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–7 SN54ABT652, SN74ABT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS070D – JULY 1991 – REVISED JULY 1994 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, TA = 25°C SN54ABT652 MIN TYP 125 200 2.2 5.3 6.8 2.2 8.2 2.2 7.8 1.7 5.9 7.4 1.7 8.8 1.7 8.4 1.5 4.4 5.7 1.5 7 1.5 6.7 1.5 4.4 5.7 1.5 7 1.5 6.7 1.5 4.6 5.9 1.5 7.4 1.5 6.9 1.5 5.4 6.7 1.5 8 1.5 7.7 1.3 3.3 4.6 1.3 6 1.3 5.8 2.5 4.5 6.8 2.5 8.9 2.5 8.5 1.5 6.2 7.7 1.5 8.3 1.5 8.2 1.5 5 6.3 1.5 7.1 1.5 6.8 1.8 3.8 6.1 1.8 6.9 1.8 6.5 2.9 4.9 6.5 2.9 7.6 2.9 7.4 1.5 4.5 5.7 1.5 7.1 1.5 OEAB B tPLZ 1.5 4.1 5.3 1.5 6.6 1.5 † These parameters are measured with the internal output state of the storage register opposite to that of the bus input. 6.9 fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ CLK B or A A or B B or A SAB or SBA† B or A OEBA A OEBA A OEAB B PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 2–8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MIN MIN MAX SN74ABT652 125 MIN UNIT MAX 125 MHz 6.2 ns ns ns ns ns ns ns SN54ABT652, SN74ABT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS070D – JULY 1991 – REVISED JULY 1994 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT FOR OUTPUTS 3V Timing Input 1.5 V 0V tw tsu 3V Input 1.5 V th 3V 1.5 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Input (see Note B) 1.5 V 0V VOH 1.5 V Output 1.5 V VOL VOH Output 1.5 V 1.5 V VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 7 V (see Note C) tPLH tPHL 1.5 V tPZL tPHL tPLH 3V Output Control 1.5 V Output Waveform 2 S1 at Open (see Note C) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V tPZH 3.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. D. The outputs are measured one at a time with one transition per measurement. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–9 SN54ABT652, SN74ABT652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS070D – JULY 1991 – REVISED JULY 1994 2–10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated