MICRON MT28F321P20

PRELIMINARY‡
2 MEG x 16
PAGE FLASH MEMORY
FLASH MEMORY
MT28F321P20
MT28F321P18
Low Voltage, Extended Temperature
0.18µm Process Technology
FEATURES
BALL ASSIGNMENT
48-Ball FBGA
• Flexible dual-bank architecture
Support for true concurrent operation with zero
latency
Read bank a during program bank b and vice
versa
Read bank a during erase bank b and vice versa
• Basic configuration:
Seventy-one erasable blocks
Bank a (4Mb for data storage)
Bank b (28Mb for program storage)
• VCC, VCCQ, VPP voltages*
1.70V (MIN), 1.90V (MAX) VCC, VCCQ
(MT28F321P18)
1.80V (MIN), 2.20V (MAX) VCC, VCCQ
(MT28F321P20)
0.9V (MIN) VPP (in-system PROGRAM/ERASE)
12V ±5% (HV) VPP tolerant (factory
programming compatibility)
• Random access time: 70ns and 80ns @ 1.80V VCC*
• Page Mode read access*
Eight-word page
Interpage read access: 70ns/80ns @ 1.80V
Intrapage read access: 30ns @ 1.80V
• Low power consumption (VCC = 2.20V)
Asynchronous READ < 15mA
Standby < 50µA
Automatic power save (APS) feature
• Enhanced write and erase suspend options
ERASE-SUSPEND-to-READ within same bank
PROGRAM-SUSPEND-to-READ within same bank
ERASE-SUSPEND-to-PROGRAM within same bank
• Dual 64-bit chip protection registers for security
purposes
• Cross-compatible command support
Extended command set
Common flash interface
• PROGRAM/ERASE cycle
100,000 WRITE/ERASE cycles per block
1
2
3
4
5
6
7
8
A
A13
A11
A8
VPP
WP#
A19
A7
A4
B
A14
A10
WE#
RST#
A18
A17
A5
A2
C
A15
A12
A9
NC
A20
A6
A3
A1
D
A16
DQ14
DQ5
DQ11
DQ2
DQ8
CE#
A0
E
VCCQ
DQ15
DQ6
DQ12
DQ3
DQ9
DQ0
VSS
F
VSS
DQ7
DQ13
DQ4
VCC
DQ10
DQ1
OE#
Top View
(Ball Down)
NOTE: See page 7 for Ball Description Table.
See page 33 for mechanical drawing.
OPTIONS
MARKING
• Timing
70ns access
80ns access
90ns access
• Boot Block Configuration
Top
Bottom
• Package
48-ball FBGA (6 x 8 ball grid)
• Operating Temperature Range
Extended (-40ºC to +85ºC)
* Data based on MT28F321P20 device.
-70
-80
-90
T
B
FG
ET
Part Number Example:
MT28F321P20FG-70 TET
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
1
‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR
©2002, Micron Technology, Inc.
EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
ARCHITECTURE AND MEMORY
ORGANIZATION
GENERAL DESCRIPTION
The MT28F321P20 and MT28F321P18 are highperformance, high-density, nonvolatile memory
solutions that can significantly improve system performance. This new architecture features a two-memorybank configuration that supports background
operation with no latency.
A high-performance bus interface allows a fast page
mode, data transfer; a conventional asynchronous bus
interface is provided as well.
The devices allow soft protection for blocks, as read
only, by configuring soft protection registers with dedicated command sequences. For security purposes, two
64-bit chip protection registers are provided.
The embedded WORD WRITE and BLOCK ERASE
functions are fully automated by an on-chip write state
machine (WSM). Two on-chip status registers, one for
each of the two memory partitions, can be used to monitor the WSM status and to determine the progress of
the program/erase task.
The erase/program suspend functionality allows
compatibility with existing EEPROM emulation software packages.
The device is manufactured using 0.18µm process
technology.
Please refer to Micron’s Web site (www.micron.com/
flash) for the latest data sheet.
The Flash devices contain two separate banks of
memory (bank a and bank b) for simultaneous READ
and WRITE operations.
The Flash memory devices are available in the following bank segmentation configuration:
• Bank a comprises one-eighth of the memory
and contains 8 x 4K-word parameter blocks;
the remainder of bank a is split into 7 x 32Kword blocks.
• Bank b represents seven-eighths of the
memory, is equally sectored, and contains 48
x 32K-word blocks.
Figures 2 and 3 show the bottom and top memory
organizations.
DEVICE MARKING
Due to the size of the package, Micron’s standard
part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to Micron part numbers in Table 1.
Table 1
Cross Reference for Abbreviated Device Marks
PART NUMBER
MT28F321P20FG-70 BET
MT28F321P20FG-70 TET
MT28F321P20FG-80 BET
MT28F321P20FG-80 TET
MT28F321P18FG-90 BET
MT28F321P18FG-90 TET
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
PRODUCT
MARKING
SAMPLE
MARKING
MECHANICAL
SAMPLE MARKING
FW818
FW819
FW810
FW811
FW820
FW821
FX818
FX819
FX810
FX811
FX820
FX821
FY818
FY819
FY810
FY811
FY820
FY821
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
PART NUMBERING INFORMATION
Micron’s low-power devices are available with several different combinations of features (see Figure 1).
Valid combinations of features and their corresponding part numbers are listed in Table 2.
Figure 1
Part Number Chart
MT 28F 321 P20FG-70 T ET
Micron Technology
Operating Temperature Range
ET = Extended (-40ºC to +85ºC)
Flash Family
Boot Block Starting Address
28F = Dual-Supply Flash
B = Bottom boot
T = Top boot
Density/Organization/Banks
Access Time
321 = 32Mb (2,048K x 16)
bank a = 1/8; bank b = 7/8
-70 = 70ns
-80 = 80ns
-90 = 90ns
Read Mode Operation
P = Asynchronous/Page Read
Package Code
FG = 48-ball FBGA (6 x 8 grid)
Operating Voltage Range
18 = 1.70V–1.90V
20 = 1.80V–2.20V
Table 2
Valid Part Number Combinations
PART NUMBER
ACCESS
TIME (ns)
BOOT BLOCK
STARTING
ADDRESS
OPERATING
TEMPERATURE
RANGE
70
70
80
80
90
90
Bottom
Top
Bottom
Top
Bottom
Top
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
-40oC to +85oC
MT28F321P20FG-70 BET
MT28F321P20FG-70 TET
MT28F321P20FG-80 BET
MT28F321P20FG-80 TET
MT28F321P18FG-90 BET
MT28F321P18FG-90 TET
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
FUNCTIONAL BLOCK DIAGRAM
PR Lock
PR Lock
Query
Query/OTP
OTP
DQ0–DQ15
Manufacturer’s ID
Data Input
Buffer
X DEC
Bank 1 Blocks
Y/Z DEC
Y/Z Gating/Sensing
Device ID
Block Lock
RCR
Data
Register
ID Reg.
RST#
CE#
WE#
Status
Reg.
CSM
OE#
WSM
Program/
Erase
Pump Voltage
Generators
DQ0–DQ15
Output
Multiplexer
I/O Logic
A0–A20
Output
Buffer
Address
Input
Buffer
Address
CNT WSM
Address Latch
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
Address
Multiplexer
4
Y/Z DEC
Y/Z Gating/Sensing
X DEC
Bank 2 Blocks
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
Figure 2
Bottom Boot Block Device
Block
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Bank b = 28Mb
Block Size
(K-bytes/K-words)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
Address Range
(x16)
1F8000h-1FFFFFh
1F0000h-1F7FFFh
1E8000h-1EFFFFh
1E0000h-1E7FFFh
1D8000h-1DFFFFh
1D0000h-1D7FFFh
1C8000h-1CFFFFh
1C0000h-1C7FFFh
1B8000h-1BFFFFh
1B0000h-1B7FFFh
1A8000h-1AFFFFh
1A0000h-1A7FFFh
198000h-19FFFFh
190000h-197FFFh
188000h-18FFFFh
180000h-187FFFh
178000h-17FFFFh
170000h-177FFFh
168000h-16FFFFh
160000h-167FFFh
158000h-15FFFFh
150000h-157FFFh
148000h-14FFFFh
140000h-147FFFh
138000h-13FFFFh
130000h-137FFFh
128000h-12FFFFh
120000h-127FFFh
118000h-11FFFFh
110000h-117FFFh
108000h-10FFFFh
100000h-107FFFh
0F8000h-0FFFFFh
0F0000h-0F7FFFh
0E8000h-0EFFFFh
0E0000h-0E7FFFh
0D8000h-0DFFFFh
0D0000h-0D7FFFh
0C8000h-0CFFFFh
0C0000h-0C7FFFh
0B8000h-0BFFFFh
0B0000h-0B7FFFh
0A8000h-0AFFFFh
0A0000h-0A7FFFh
098000h-097FFFh
090000h-097FFFh
088000h-087FFFh
080000h-087FFFh
078000h-07FFFFh
070000h-077FFFh
068000h-067FFFh
060000h-067FFFh
058000h-05FFFFh
050000h-057FFFh
048000h-04FFFFh
040000h-047FFFh
Block
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
5
Bank a = 4Mb
Block Size
(K-bytes/K-words)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
Address Range
(x16)
038000h-03FFFFh
030000h-037FFFh
028000h-02FFFFh
020000h-027FFFh
018000h-01FFFFh
010000h-017FFFh
008000h-00FFFFh
007000h-007FFFh
006000h-006FFFh
005000h-005FFFh
004000h-004FFFh
003000h-003FFFh
002000h-002FFFh
001000h-001FFFh
000000h-000FFFh
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
Figure 3
Top Boot Block Device
Block
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
Bank a = 4Mb
Block Size
(K-bytes/K-words)
8/4
8/4
8/4
8/4
8/4
8/4
8/4
8/4
64/32
64/32
64/32
64/32
64/32
64/32
64/32
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
Address Range
(x16)
1FF000h-1FFFFFh
1FE000h-1FEFFFh
1FD000h-1FDFFFh
1FC000h-1FCFFFh
1FB000h-1FBFFFh
1FA000h-1FAFFFh
1F9000h-1F9FFFh
1F8000h-1F8FFFh
1F0000h-1F7FFFh
1E8000h-1EFFFFh
1E0000h-1E7FFFh
1D8000h-1DFFFFh
1D0000h-1D7FFFh
1C8000h-1CFFFFh
1C0000h-1C7FFFh
Block
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
6
Bank b = 28Mb
Block Size
(K-bytes/K-words)
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
Address Range
(x16)
1B8000h-1BFFFFh
1B0000h-1B7FFFh
1A8000h-1AFFFFh
1A0000h-1A7FFFh
198000h-19FFFFh
190000h-197FFFh
188000h-18FFFFh
180000h-187FFFh
178000h-17FFFFh
170000h-177FFFh
168000h-16FFFFh
160000h-167FFFh
158000h-15FFFFh
150000h-157FFFh
148000h-14FFFFh
140000h-147FFFh
138000h-13FFFFh
130000h-137FFFh
128000h-12FFFFh
120000h-127FFFh
118000h-11FFFFh
110000h-117FFFh
108000h-10FFFFh
100000h-107FFFh
0F8000h-0FFFFFh
0F0000h-0F7FFFh
0E8000h-0EFFFFh
0E0000h-0E7FFFh
0D8000h-0DFFFFh
0D0000h-0D7FFFh
0C8000h-0CFFFFh
0C0000h-0C7FFFh
0B8000h-0BFFFFh
0B0000h-0B7FFFh
0A8000h-0AFFFFh
0A0000h-0A7FFFh
098000h-09FFFFh
090000h-097FFFh
088000h-08FFFFh
080000h-087FFFh
078000h-07FFFFh
070000h-077FFFh
068000h-06FFFFh
060000h-067FFFh
058000h-05FFFFh
050000h-057FFFh
048000h-04FFFFh
040000h-047FFFh
038000h-03FFFFh
030000h-037FFFh
028000h-02FFFFh
020000h-027FFFh
018000h-01FFFFh
010000h-017FFFh
008000h-00FFFFh
000000h-007FFFh
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
BALL DESCRIPTIONS
48-BALL FBGA
NUMBERS
SYMBOL
TYPE
DESCRIPTION
D8, C8, B8, C7,
A8, B7, C6, A7,
A3, C3, B2, A2,
C2, A1, B1, C1,
D1, B6, B5, A6,
C5
A0–A20
Input
Address Inputs: Inputs for the address during READ and WRITE
operations. Addresses are internally latched during READ and WRITE
cycles.
D7
CE#
Input
Chip Enable: Activates the device when LOW. When CE# is HIGH, the
device is disabled and goes into standby power mode.
F8
OE#
Input
Output Enable: Enables the output buffer when LOW. When OE# is
HIGH, the output buffers are disabled.
B3
WE#
Input
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is
LOW, the cycle is either a WRITE to the command state machine
(CSM) or to the memory array.
B4
RST#
Input
Reset: When RST# is a logic LOW, the device is in reset mode, which
drives the outputs to High-Z and resets the write state machine
(WSM). When RST# is at logic HIGH, the device is in standard
operation. When RST# transitions from logic LOW to logic HIGH, the
device resets all blocks to locked and defaults to the read array
mode.
A5
WP#
Input
Write Protect: Controls the lock down function of the flexible locking
feature.
A4
VPP
Input
Program/Erase Enable: [0.9V–2.2V or 11.4V–12.6V] Operates as input
at logic levels to control complete device protection. Provides factory
programming compatibility when driven to 11.4V–12.6V.
E7, F7, D5, B5, DQ0–DQ15
F4, D3, E3, F2,
D6, 36, F6, D4,
E4, F3, D2, E2
Input/
Output
Data Inputs/Outputs: Input array data on the second CE# and WE#
cycle during PROGRAM command. Input commands to the
command user interface when CE# and WE# are active. DQ0–DQ15
output data when CE# and OE# are active.
E8, F1
VSS
Supply
Do not float any ground ball.
F5
VCC
Supply
Device Power Supply: [1.70V–1.90V (MT28F321P18) or 1.80V–2.20V
(MT28F321P20)] Supplies power for device operation.
E1
VCCQ
Supply
I/O Power Supply: [1.70V–1.90V (MT28F321P18) or 1.80V–2.20V
(MT28F321P20)] Supplies power for input/output buffers.
C4
NC
–
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
Internally not connected.
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
COMMAND STATE MACHINE (CSM)
Commands are issued to the command state machine (CSM) using standard microprocessor write timings. The CSM acts as an interface between external
microprocessors and the internal WSM. The available
commands are listed in Table 3, their definitions are
given in Table 4, and their descriptions in Table 5.
Program and erase algorithms are automated by an
on-chip WSM. For more specific information about the
CSM transition states, see Micron technical note
TN-28-33, “Command State Machine Description and
Command Definition.”
Once a valid PROGRAM/ERASE command is entered, the WSM executes the appropriate algorithm,
which generates the necessary timing signals to control the device internally and accomplish the requested
operation. A command is valid only if the exact sequence of WRITEs is completed. After the WSM completes its task, the WSM status bit (SR7) (see Table 7) is
set to a logic HIGH level (1), allowing the CSM to respond to the full command set again.
level (VIL), and WE# and RST# must be at logic HIGH
(VIH).
Table 6 shows the bus operations for all the modes:
write, read, reset, standby, and output disable.
When the device is powered up, internal reset circuitry initializes the chip to a read array mode of operation. Changing the mode of operation requires that a
command code be entered into the CSM. For each one
of the two memory partitions, an on-chip status register is available. These two registers allow the progress
of the various operations that can take place on a
memory bank to be monitored. One of the two status
registers is interrogated by entering a READ STATUS
REGISTER command onto the CSM (cycle 1), specifying an address within the memory partition boundary,
and reading the register data on I/Os DQ0–DQ7
(cycle 2). Status register bits SR0-SR7 correspond to
DQ0–DQ7 (see Table 7).
COMMAND DEFINITION
Once a specific command code has been entered,
the WSM executes an internal algorithm, generating
the necessary timing signals to program, erase, and
verify data. See Table 4 for the CSM command definitions and data for each of the bus cycles.
OPERATIONS
Device operations are selected by entering a standard JEDEC 8-bit command code with conventional
microprocessor timings into an on-chip CSM through
I/Os DQ0–DQ7. The number of bus cycles required to
activate a command is typically one or two. The first
operation is always a WRITE. Control signals CE# and
WE# must be at a logic LOW level (VIL), and OE# and
RST# must be at logic HIGH (VIH). The second operation, when needed, can be a WRITE or a READ depending upon the command. During a READ operation,
control signals CE# and OE# must be at a logic LOW
STATUS REGISTER
The status register allows the user to determine
whether the state of a PROGRAM/ERASE operation is
pending or complete. The status register is monitored
by toggling OE# and CE#, and reading the resulting
status code on I/Os DQ0–DQ7. The high-order I/Os
(DQ8–DQ15) are set to 00h internally, so only the low-
Table 3
Command State Machine Codes For Device Mode Selection
COMMAND DQ0–DQ7
40h/10h
CODE ON DEVICE MODE
Program setup/alternate program setup
20h
50h
60h
70h
90h
Block erase setup
Clear status register
Protection configuration setup
Read status register
Read protection configuration register
98h
B0h
C0h
D0h
FFh
Read query
Program/erase suspend
Protection register program/lock
Program/erase resume – erase confirm
Read array
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
order I/Os (DQ0–DQ7) need to be interpreted. Address
lines select the status register pertinent to the selected
memory partition.
Register data is updated and latched on the falling
edge of OE# or CE#, whichever occurs last. Latching the
data prevents errors from occurring if the register input
changes during a status register read.
The status register provides the internal state of the
WSM to the external microprocessor. During periods
when the WSM is active, the status register can be polled
to determine the WSM status. Table 7 defines the status register bits.
After monitoring the status register during a
PROGRAM/ERASE operation, the data appearing on
DQ0–DQ7 remains as status register data until a new
command is issued to the CSM. To return the device to
other modes of operation, a new command must be
issued to the CSM.
CSM OPERATIONS
The CSM decodes instructions for read array, read
protection configuration register, read query, read status register, clear status register, program, erase, erase
suspend, erase resume, program suspend, program
resume, lock block, unlock block, and lock down block,
chip protection program, and set read configuration
register. The 8-bit command code is input to the device
on DQ0–DQ7 (see Table 3 for CSM codes and Table 4
for command definitions). During a PROGRAM or
ERASE cycle, the CSM informs the WSM that a PROGRAM or ERASE cycle has been requested.
During a PROGRAM cycle, the WSM controls the
program sequences and the CSM responds to a PROGRAM SUSPEND command only.
During an ERASE cycle, the CSM responds to an
ERASE SUSPEND command only. When the WSM has
completed its task, the WSM status bit (SR7) is set to a
logic HIGH level and the CSM responds to the full com-
Table 4
Command Definitions
FIRST BUS CYCLE
SECOND BUS CYCLE
OPERATION
ADDRESS1
READ ARRAY
WRITE
WA
FFh
READ PROTECTION CONFIGURATION REGISTER
READ STATUS REGISTER
WRITE
WRITE
IA
BA
90h
70h
READ
READ
IA
X
ID
SRD
CLEAR STATUS REGISTER
READ QUERY
BLOCK ERASE SETUP
WRITE
WRITE
WRITE
BA
QA
BA
50h
98h
20h
READ
WRITE
QA
BA
QD
D0h
PROGRAM SETUP/ALTERNATE PROGRAM SETUP
PROGRAM/ERASE SUSPEND
PROGRAM/ERASE RESUME - ERASE CONFIRM
LOCK BLOCK
UNLOCK BLOCK
WRITE
WRITE
WRITE
WRITE
WRITE
WA
BA
BA
BA
BA
40h/10h
B0h
D0h
60h
60h
WRITE
WA
WD
WRITE
WRITE
BA
BA
01h
D0h
LOCK DOWN BLOCK
PROTECTION REGISTER PROGRAM
PROTECTION REGISTER LOCK
WRITE
WRITE
WRITE
BA
PA
LPA
60h
C0h
C0h
WRITE
WRITE
WRITE
BA
PA
LPA
2Fh
PD
FFFDh
COMMAND
DATA
OPERATION ADDRESS1
DATA1
NOTE: 1. BA: Address within the block
IA: Identification code address
ID: Identification code data
LPA: Lock protection register address
PA: Protection register address
PD: Data to be written at the location PA
QA: Query code address
QD: Query code data
SRD: Data read from the status register
WA: Word address of memory location to be written, or read
WD: Data to be written at the location WA
X: “Don’t Care”
2 Meg x 16 Page Flash Memory
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Table 5
Command Descriptions
CODE DEVICE MODE
BUS CYCLE
DESCRIPTION
10h
Alt. Program Setup
First
Operates the same as a PROGRAM SETUP command.
20h
Erase Setup
First
Prepares the CSM for an ERASE CONFIRM command. If the next
command is not an ERASE CONFIRM command, the command will
be ignored, and the bank will go to read status mode and wait for
another command.
40h
Program Setup
First
A two-cycle command: The first cycle prepares for a PROGRAM
operation, and the second cycle latches addresses and data and
initiates the WSM to execute the program algorithm. The Flash
device outputs status register data on the falling edge of OE# or CE#,
whichever occurs first.
50h
Clear Status
Register
First
The WSM can set the block lock status (SR3), program status (SR4),
and erase status (SR5) bits in the status register to “1,” but it cannot
clear them to “0.” Issuing this command clears those bits to “0.”
60h
Protection
Configuration
Setup
First
Prepares the CSM for changes to the block locking status. If the next
command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK
DOWN, the command will be ignored, and the device will go to read
status mode.
70h
Read Status
Register
First
Places the device into read status register mode. Reading the device
will output the contents of the status register for the addressed bank.
The device will automatically enter this mode for the addressed bank
after a PROGRAM or ERASE operation has been initiated.
90h
Read Protection
Configuration
First
Puts the device into the read protection configuration mode so that
reading the device will output the manufacturer/device codes or
block lock status.
98h
Read Query
First
Puts the device into the read query mode so that reading the device
will output common flash interface information.
B0h
Program/Erase
Suspend
First
Suspends the currently executing PROGRAM/ERASE operation. The
status register will indicate when the operation has been successfully
suspended by setting either the program suspend (SR2) or erase
suspend (SR6), and the WSM status bit (SR7) to a “1” (ready). The
WSM will continue to idle in the suspend state, regardless of the state
of all input control signals except RST#, which will immediately shut
down the WSM and the remainder of the chip if RST# is driven to VIL.
C0h
Program Device
Protection Register
First
Writes a specific code into the device protection register.
Lock Device
Protection Register
First
Locks the device protection register; data can no longer be changed.
(continued on the next page)
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Table 5
Command Descriptions (continued)
CODE DEVICE MODE
D0h
BUS CYCLE
DESCRIPTION
Erase Confirm
Second
If the previous command was an ERASE SETUP command, then the
CSM will close the address and data latches, and it will begin erasing
the block indicated on the address balls. During programming/erase,
the device will respond only to the READ STATUS REGISTER,
PROGRAM SUSPEND, or ERASE SUSPEND commands and will output
status register data on the falling edge of OE# or CE#, whichever
occurs last.
Program/Erase
Resume
First
If a PROGRAM or ERASE operation was previously suspended, this
command will resume the operation.
During the array mode, array data will be output on the data bus.
FFh
Read Array
First
01h
Lock Block
Second
If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM will latch the address and lock the block indicated on the
address bus.
2Fh
Lock Down
Second
If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM will latch the address and lock down the block indicated on
the address bus.
D0h
Unlock Block
Second
If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM will latch the address and unlock the block indicated on the
address bus. If the block had been previously set to lock down, this
operation will have no effect.
00h
Invalid /Reserved
Unassigned command that should not be used.
be at a logic LOW level (VIL), and WE# and RST# must be
at logic HIGH level (VIH) to read data from the array.
Data is available on DQ0–DQ15. Any valid address
within any of the blocks selects that address and allows
data to be read from that address. Upon initial powerup or device reset, the device defaults to the read array
mode.
mand set. The CSM stays in the current command state
until the microprocessor issues another command.
The WSM successfully initiates an ERASE or PROGRAM operation only when VPP is within its correct voltage range.
CLEAR STATUS REGISTER
The internal circuitry can set, but not clear, the block
lock status bit (SR1), the VPP status bit (SR3), the program status bit (SR4), and the erase status bit (SR5) of
the status register. The CLEAR STATUS REGISTER command (50h) allows the external microprocessor to clear
these status bits and synchronize to the internal operations. When the status bits are cleared, the device
returns to the read array mode.
READ PROTECTION CONFIGURATION DATA
The chip identification mode outputs three types
of information: the manufacturer/device identifier, the
block locking status, and the protection register. Two
bus cycles are required for this operation: the chip identification data is read by entering the command code
90h on DQ0–DQ7 to the bank containing address 00h
and the identification code address on the address
lines. Control signals CE# and OE# must be at a logic
LOW level (VIL), and WE# and RST# must be at a logic
HIGH level (VIH) to read data from the protection configuration register. Data is available on DQ0–DQ15.
After data is read from the protection configuration
register, the READ ARRAY command, FFh, must be issued to the bank containing address 00h prior to issuing other commands. See Table 9 for further details.
READ OPERATIONS
The following READ operations are available: READ
ARRAY, READ PROTECTION CONFIGURATION REGISTER, READ QUERY and READ STATUS REGISTER.
READ ARRAY
The array is read by entering the command code
FFh on DQ0–DQ7. Control signals CE# and OE# must
2 Meg x 16 Page Flash Memory
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READ QUERY
The read query mode outputs common flash interface (CFI) data when the device is read (see Table 11).
Two bus cycles are required for this operation. It is
possible to access the query by writing the read query
command code 98h on DQ0–DQ7 to the bank containing address 0h. Control signals CE# and OE# must be at
a logic LOW level (VIL), and WE# and RST# must be at a
logic HIGH level (VIH) to read data from the query. The
CFI data structure contains information such as block
size, density, command set, and electrical specifications. To return to read array mode, write the read array
command code FFh on DQ0–DQ7.
Taking RST# to VIL during programming aborts the
PROGRAM operation. During programming, VPP must
remain in the appropriate VPP voltage range as shown
in the recommended operating conditions table.
ERASE OPERATIONS
An ERASE operation must be used to initialize all
bits in an array block to “1s.” After BLOCK ERASE confirm is issued, the CSM responds only to an ERASE
SUSPEND command until the WSM completes its task.
Block erasure inside the memory array sets all bits
within the address block to logic 1s. Erase is accomplished only by blocks; data at single address locations
within the array cannot be erased individually. The
block to be erased is selected by using any valid address within that block. Block erasure is initiated by a
command sequence to the CSM: BLOCK ERASE setup
(20h) followed by BLOCK ERASE CONFIRM (D0h) (see
Figure 6). A two-command erase sequence protects
against accidental erasure of memory contents.
When the BLOCK ERASE CONFIRM command is
complete, the WSM automatically executes a sequence
of events to complete the block erasure. During this
sequence, the block is programmed with logic 0s, data
is verified, all bits in the block are erased, and finally
verification is performed to ensure that all bits are correctly erased. The ERASE operation may be monitored
through the status register (see the Status Register
section).
During the execution of an ERASE operation the
ERASE SUSPEND command (B0h) can be entered to
direct the WSM to suspend the ERASE operation. Once
the WSM has reached the suspend state, it allows
the CSM to respond only to the READ ARRAY, READ
STATUS REGISTER, READ QUERY, READ CHIP PROTECTION CONFIGURATION, PROGRAM SETUP, PROGRAM RESUME, ERASE RESUME and LOCK SETUP
(see the Block Locking section). During the ERASE SUSPEND operation, array data must be read from a block
other than the one being erased. To resume the ERASE
operation, an ERASE RESUME command (D0h) must
be issued to cause the CSM to clear the suspend state
previously set (see Figure 7). It is also possible to suspend an ERASE in any bank and initiate a WRITE to
another block in the same bank. After the completion
of a WRITE, an ERASE can be resumed by writing an
ERASE RESUME command.
READ STATUS REGISTER
The status register is read by entering the command
code 70h on DQ0–DQ7. Two bus cycles are required for
this operation: one to enter the command code and the
block address and a second to read the status register.
In a READ cycle, the address is latched and register
data is updated on the falling edge of OE# or CE#,
whichever occurs last. Register data is updated and
latched on the falling edge of OE# or CE#, whichever
occurs last.
PROGRAMMING OPERATIONS
There are two CSM commands for programming:
PROGRAM SETUP and ALTERNATE PROGRAM SETUP
(see Table 3).
After the desired command code is entered (10h or
40h command code on DQ0–DQ7), the WSM takes over
and correctly sequences the device to complete the
PROGRAM operation. The WRITE operation may be
monitored through the status register (see the Status
Register section). During this time, the CSM will only
respond to a PROGRAM SUSPEND command until the
PROGRAM operation has been completed, after which
time all commands to the CSM become valid again.
The PROGRAM operation can be suspended by issuing
a PROGRAM SUSPEND command (B0h). Once the WSM
reaches the suspend state, it allows the CSM to respond only to READ ARRAY, READ STATUS REGISTER,
READ PROTECTION CONFIGURATION, READ QUERY,
PROGRAM SETUP, or PROGRAM RESUME. During the
PROGRAM SUSPEND operation, array data should be
read from an address other than the one being programmed. To resume the PROGRAM operation, a PROGRAM RESUME command (D0h) must be issued to
cause the CSM to clear the suspend state previously
set (see Figure 4 for programming operation and Figure
5 for program suspend and program resume).
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
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Table 6
Bus Operations
MODE
RST#
CE#
OE#
WE#
ADDRESS DQ0–DQ15
Read (array, status registers,
device identification register, or
query)
VIH
VIL
VIL
VIH
X
DOUT
Standby
VIH
VIH
X
X
X
High-Z
Output Disable
VIH
VIH
X
X
X
High-Z
Reset
VIL
X
X
X
X
High-Z
Write
VIH
VIL
VIH
VIL
X
DIN
Table 7
Status Register Bit Definition
WSMS
ESS
ES
PS
VPPS
PSS
BLS
R
7
6
5
4
3
2
1
0
STATUS
BIT # STATUS REGISTER BIT
DESCRIPTION
SR7
WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
Check write state machine bit first to determine word
program or block erase completion, before checking
program or erase status bits.
SR6
ERASE SUSPEND STATUS (ESS)
1 = BLOCK ERASE Suspended
0 = BLOCK ERASE in
Progress/Completed
When ERASE SUSPEND is issued, WSM halts execution and
sets both WSMS and ESS bits to “1.” ESS bit remains set to
“1” until an ERASE RESUME command is issued.
SR5
ERASE STATUS (ES)
1 = Error in Block Erasure
0 = Successful BLOCK ERASE
When this bit is set to “1,” WSM has applied the maximum
number of erase pulses to the block and is still unable to
verify successful block erasure.
SR4
PROGRAM STATUS (PS)
1 = Error in PROGRAM
0 = Successful PROGRAM
When this bit is set to “1,” WSM has attempted but failed
to program a word.
SR3
VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP = OK
The VPP status bit does not provide continuous indication
of the VPP level. The WSM interrogates the VPP level only
after the program or erase command sequences have been
entered and informs the system if VPP < 0.9V. The VPP level
is also checked before the PROGRAM/ERASE operation is
verified by the WSM.
SR2
PROGRAM SUSPEND STATUS (PSS)
1 = PROGRAM Suspended
0 = PROGRAM in Progress/Completed
When PROGRAM SUSPEND is issued, WSM halts execution
and sets both WSMS and PSS bits to “1.” PSS bit remains
set to “1” until a PROGRAM RESUME command is issued.
SR1
BLOCK LOCK STATUS (BLS)
1 = PROGRAM/ERASE Attempted on a
Locked Block; Operation Aborted
0 = No Operation to Locked Blocks
If a PROGRAM or ERASE operation is attempted to one of
the locked blocks, this is set by the WSM. The operation
specified is aborted and the device is returned to read
status mode.
SR0
RESERVED FOR FUTURE
ENHANCEMENT
This bit is reserved for future use.
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
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Figure 4
Automated Word Programming
Flowchart
BUS
OPERATION COMMAND COMMENTS
WRITE
WRITE
PROGRAM
SETUP
Data =
Addr =
40h or 10h
Address of word to be
programmed
WRITE
WRITE
DATA
Data =
Word to be
programmed
Address of word to be
programmed
Start
Issue PROGRAM SETUP
Command and
Word Address
Addr =
READ
Status register data
Toggle OE# or CE# to
update status register.
Standby
Check SR7
1 = Ready, 0 = Busy
Issue Word Address
and Word Data
PROGRAM
SUSPEND Loop
Read Status Register
Bits
Repeat for subsequent words.
Write FFh after the last word programming operation
to reset the device to read array mode.
NO
NO
PROGRAM
SUSPEND?
SR7 = 1?
YES
YES
Full Status Register
Check (optional)1
Word Program
Completed
BUS
OPERATION COMMAND COMMENTS
FULL STATUS REGISTER CHECK FLOW
Read Status Register
Bits
SR1 = 0?
NO PROGRAM Attempted
on a Locked Block
YES
NO
SR3 = 0?
Standby
Check SR1
1 = Detect locked block
Standby
Check SR32
1 = Detect VPP LOW
Standby
Check SR43
1 = Word program error
VPP Range Error
YES
NO
SR4 = 0?
Word Program Failed
YES
Word Program Passed
NOTE: 1. Full status register check can be done after each word or after a sequence of words.
2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR4 is cleared only by the CLEAR STATUS REGISTER command, but it does not prevent additional program operation
attempts.
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
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Figure 5
PROGRAM SUSPEND/
PROGRAM RESUME Flowchart
BUS
OPERATION COMMAND COMMENTS
WRITE
Start
Issue PROGRAM
SUSPEND Command
Status register data
Toggle OE# or CE# to update
status register.
Standby
Check SR7
1 = Ready
Standby
Check SR2
1 = Suspended
READ
ARRAY
READ
WRITE
NO
SR7 = 1?
Data = B0h
READ
WRITE
Read Status Register
Bits
PROGRAM
SUSPEND
Data = FFh
Read data from block other
than that being programmed.
PROGRAM
RESUME
Data = D0h
YES
NO
SR2 = 1?
PROGRAM
Complete
YES
Issue READ ARRAY
Command
Finished
Reading
?
NO
YES
Issue PROGRAM
RESUME Command
PROGRAM Resumed
NOTE: 1. Full status register check can be done after each word or after a sequence of words.
2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full
status is checked.
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
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Figure 6
BLOCK ERASE Flowchart
BUS
OPERATION COMMAND COMMENTS
WRITE
WRITE
ERASE
SETUP
Data = 20h
Block Addr = Address
within block to be erased
WRITE
ERASE
Data = D0h
Block Addr = Address
within block to be erased
Start
Issue ERASE SETUP
Command and
Block Address
READ
Status register data
Toggle OE# or CE# to
update status register.
Standby
Check SR7
1 = Ready, 0 = Busy
Issue BLOCK ERASE
CONFIRM Command
and Block Address
ERASE
SUSPEND Loop
Read Status Register
Bits
Repeat for subsequent blocks.
Write FFh after the last BLOCK ERASE operation to
reset the device to read array mode.
NO
NO
ERASE
SUSPEND?
SR 7 = 1?
YES
YES
Full Status Register
Check (optional)1
BLOCK ERASE
Completed
BUS
OPERATION COMMAND COMMENTS
FULL STATUS REGISTER CHECK FLOW
Read Status Register
Bits
NO
SR1 = 0?
ERASE Attempted
on a Locked Block
YES
NO
SR3 = 0?
Standby
Check SR1
1 = Detect locked block
Standby
Check SR32
1 = Detect VPP block
Standby
Check SR53
1 = BLOCK ERASE error
VPP Range Error
YES
NO
SR5 = 0?
BLOCK ERASE Failed
YES
BLOCK ERASE Passed
NOTE: 1. Full status register check can be done after each block or after a sequence of blocks.
2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full
status is checked.
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
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Figure 7
ERASE SUSPEND/ERASE RESUME
Flowchart
BUS
OPERATION COMMAND COMMENTS
WRITE
Start
Issue ERASE
SUSPEND Command
Read Status Register
Bits
ERASE
SUSPEND
Data = B0h
READ
Status register data
Toggle OE# or CE# to
update status register.
Standby
Check SR7
1 = Ready
Standby
Check SR6
1 = Suspended
WRITE
READ
ARRAY
READ
Data = FFh
Read data from block
other than that being
erased.
NO
SR7 = 1?
WRITE
ERASE
RESUME
YES
Data = D0h
NO
SR6 = 1?
YES
READ or
PROGRAM?
ERASE
Complete
PROGRAM
READ
Issue READ ARRAY
Command
PROGRAM
Loop
(Note 1)
NO
READ or
PROGRAM
Complete?
YES
Issue ERASE
RESUME Command
ERASE Continued2
NOTE: 1. See BLOCK ERASE Flowchart for complete erasure procedure.
2. See Word Programming Flowchart for complete programming procedure.
2 Meg x 16 Page Flash Memory
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Figure 8
READ-While-WRITE Concurrency
READ-WHILE-WRITE/ERASE
CONCURRENCY
It is possible for the device to read from one bank
while erasing/writing to another bank. Once a bank
enters the WRITE/ERASE operation, the other bank
automatically enters read array mode. For example,
during a READ CONCURRENCY operation, if a PROGRAM/ERASE command is issued in bank a, then bank
a changes to the read status mode and bank b defaults
to the read array mode. The device will read from bank
b if the latched address resides in bank b (see Figure 8).
Similarly, if a PROGRAM/ERASE command is issued in
bank b, then bank b changes to read status mode and
bank a defaults to read array mode. When returning to
bank a, the device will read PROGRAM/ERASE status if
the latched address resides in bank a. A correct bank
address must be specified to read status register after
returning from concurrent read in the other bank.
When reading the CFI or the chip protection register, concurrent operation is not allowed on the top boot
device. Concurrent READ of the CFI or the chip protection register is only allowed when a PROGRAM or ERASE
operation is performed on bank b on the bottom boot
device. For a bottom boot device, reading of the CFI
table or the chip protection register is only allowed if
bank b is in read array mode. For a top boot device,
reading of the CFI table or the chip protection register
is only allowed if bank a is in read array mode.
2 Meg x 16 Page Flash Memory
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Bank a
1 - Erasing/writing to bank a
2 - Erasing in bank a can be
suspended, and a WRITE to
another block in bank a
can be initiated.
3 - After the WRITE in that block
is complete, an ERASE can
be resumed by writing an
ERASE RESUME command.
Bank b
1 - Reading bank a
1 - Erasing/writing to bank b
2 - Erasing in bank b can be
suspended, and a WRITE to
another block in bank b
can be initiated.
3 - After the WRITE in that block
is complete, an ERASE can
be resumed by writing an
ERASE RESUME command.
1 - Reading from bank b
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BLOCK LOCKING
LOCKED DOWN STATE
Blocks that are locked down (state [011]) are protected from PROGRAM and ERASE operations, but
their protection status cannot be changed using software commands alone. A locked or unlocked block can
be locked down by writing the lock down command
sequence, 60h followed by 2Fh. Locked down blocks
revert to the locked state when the device is reset or
powered down.
The LOCK DOWN function is dependent on the
WP# input. When WP# = 0, blocks in lock down [011] are
protected from program, erase, and lock status
changes. When WP# = 1, the lock down function is disabled ([111]), and locked down blocks can be individually unlocked by a software command to the [110] state,
where they can be erased and programmed. These
blocks can then be relocked [111] and unlocked [110]
as desired while WP# remains HIGH. When WP# goes
LOW, blocks that were previously locked down return
to the locked down state [011] regardless of any changes
made while WP# was HIGH. Device reset or powerdown resets all locks, including those in lock down, to
locked state (see Table 9).
The Flash memory devices provide a flexible locking scheme which allows each block to be individually
locked or unlocked with no latency.
The devices offer two-level protection for the blocks.
The first level allows software-only control of block locking (for data which needs to be changed frequently),
while the second level requires hardware interaction
before locking can be changed (code which does not
require frequent updates).
Control signals WP#, DQ0, and DQ1 define the state
of a block; for example, state [001] means WP# = 0,
DQ0 = 1 and DQ1 = 0.
Table 8 defines all of the possible locking states.
NOTE: All blocks are software-locked upon powerup sequence completion.
LOCKED STATE
After a power-up sequence completion, or after a
reset sequence, all blocks are locked (states [001] or
[101]). This means full protection from alteration. Any
PROGRAM or ERASE operations attempted on a locked
block will return an error on bit SR1 of the status register. The status of a locked block can be changed to
unlocked or lock down using the appropriate software
commands. Writing the lock command sequence, 60h
followed by 01h, can lock an unlocked block.
READING A BLOCK’S LOCK STATUS
The lock status of every block can be read in the
read device identification mode. To enter this mode,
write 90h to the the bank containing address 00h. Subsequent READs at block address +00002 will output the
lock status of that block. The lowest two outputs, DQ0
and DQ1, represent the lock status. DQ0 indicates the
block lock/unlock status and is set by the LOCK command and cleared by the UNLOCK command. It is also
automatically set when entering lock down. DQ1 indicates lock down status and is set by the LOCK DOWN
UNLOCKED STATE
Unlocked blocks (states [000], [100], [110]) can be
programmed or erased. All unlocked blocks return to
the locked state when the device is reset or powered
down. An unlocked block can be locked or locked down
using the appropriate software command sequence,
60h followed by D0h (see Table 4).
Table 8
Block Locking State Transition
WP#
DQ1
DQ0
NAME
ERASE/PROGRAM
ALLOWED
LOCK
UNLOCK
LOCK
DOWN
0
0
0
Unlocked
Yes
To [001]
No Change
To [011]
0
0
1
Locked (Default)
No
No Change
To [000]
To [011]
0
1
1
Lock Down
No
No Change
No Change
No Change
1
0
0
Unlocked
Yes
To [101]
No Change
To [111]
1
0
1
Locked
No
No Change
To [100]
To [111]
1
1
0
Lock Down
Disabled
Yes
To [111]
No Change
To [111]
1
1
1
Lock Down
Disabled
No
No Change
To [110]
No Change
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
19
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©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
command. It can only be cleared by reset or powerdown, not by software. Table 8 shows the locking state
transition scheme. The READ ARRAY command, FFh,
must be issued to the bank containing address 00h
prior to issuing other commands.
CHIP PROTECTION REGISTER
A 128-bit chip protection register can be used to
fulfill the security considerations in the system (preventing the device substitution).
The 128-bit security area is divided into two 64-bit
segments. The first 64 bits are programmed at the
manufacturing site with a unique 64-bit unchangeable number. The other segment is left blank for customers to program as desired. (See Figure 9).
LOCKING OPERATIONS DURING ERASE
SUSPEND
Changes to block lock status can be performed during an ERASE SUSPEND by using the standard locking
command sequences to unlock, lock, or lock down. This
is useful in the case when another block needs to be
updated while an ERASE operation is in progress.
To change block locking during an ERASE operation, first write the ERASE SUSPEND command (B0h),
then check the status register until it indicates that the
ERASE operation has been suspended. Next, write the
desired lock command sequence to block lock, and the
lock status will be changed. After completing any desired LOCK, READ, or PROGRAM operations, resume
the ERASE operation with the ERASE RESUME command (D0h).
If a block is locked or locked down during an ERASE
SUSPEND on the same block, the locking status bits
will be changed immediately. When the ERASE is resumed, the ERASE operation will complete.
A locking operation cannot be performed during a
PROGRAM SUSPEND.
Figure 9
Protection Register Memory Map
88h
85h
4 Words
User-Programmed
84h
4 Words
Factory-Programmed
81h
80h
PR Lock
0
Table 9
Chip Configuration Addressing1
ITEM
ADDRESS 2
DATA
Manufacturer Code (x16)
00000h
002Ch
Device Code
Top boot configuration
Bottom boot configuration
00001h
Block Lock Configuration
Block is unlocked
Block is locked
Block is locked down
XX002h
Lock
DQ0 = 0
DQ0 = 1
DQ1 = 1
Chip Protection Register Lock
80h
PR Lock
Chip Protection Register 1
81h–84h
Factory Data
Chip Protection Register 2
85h–88h
User Data
·
·
·
·
·
44B2h
44B3h
NOTE: 1. Other locations within the configuration address space are reserved by
Micron for future use.
2. “XX” specifies the block address of lock configuration.
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
20
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©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
READING THE CHIP PROTECTION REGISTER
The chip protection register is read in the device
identification mode. To enter this mode, load the 90h
command to the bank containing address 00h. Once in
this mode, READ cycles from addresses shown in Table
9 retrieve the specified information. To return to the
read array mode, write the READ ARRAY command
(FFh). The READ ARRAY command, FFh, must be issued to the bank containing address 00h prior to issuing other commands.
PAGE READ MODE
The initial portion of the page mode cycle is the
same as the asynchronous access cycle. Holding CE#
LOW and toggling addresses A0–A2 allows random access of other words in the page. The page word size is
eight words.
VPP / VCC PROGRAM AND ERASE
VOLTAGES
The MT28F321P20 Flash memory provides insystem programming and erase with V PP in the
0.9V–2.2V range. The 12V VPP mode programming is
offered for compatibility with existing programming
equipment and does not enhance program/erase
performance.
The device can withstand 100,000 WRITE/ERASE
operations when VPP = VPP1 or 100 WRITE/ERASE operations and 10 cumulative hours when VPP = VPP2.
In addition to the flexible block locking, the VPP
programming voltage can be held low for absolute hardware write protection of all blocks in the Flash device.
When VPP is below VPPLK, any PROGRAM or ERASE
operation will result in an error, prompting the corresponding status register bit (SR3) to be set.
During WRITE and ERASE operations, the WSM
monitors the VPP voltage level. WRITE/ERASE operations are allowed only when VPP is within the ranges
specified in Table 10.
When VCC is below VLKO, any WRITE/ERASE operation will be disabled.
PROGRAMMING THE CHIP PROTECTION
REGISTER
The first 64 bits (PR1) of the protection register (addresses 81h–84h) are programmed with a unique identifier at the factory. DQ0 of the PR lock register (address
80h) is programmed to a “0” state, locking the first 64
bits and preventing any further programming. The
second 64 bits (PR2) is a user area (addresses 85h–
88h), where the user can program any information into
this area as long as DQ1 of the PR lock register remains
unprogrammed. After DQ1 of the PR lock register is
programmed, no further programming is allowed on
PR2. The programming sequence is similar to array
programming except that the PROTECTION REGISTER PROGRAMMING SETUP command (C0h) is issued
instead of an ARRAY PROGRAMMING SETUP command (40h), followed by the data to be programmed at
addresses 85h–88h.
To program the PR lock bit for PR2 (to prevent further programming), use the above sequence on address 80h, with data of FFFDh (DQ1 = 0).
Table 10
VPP Range (V)
ASYNCHRONOUS READ CYCLE
When accessing addresses in a random order or
when switching between pages, the access time is given
by tAA.
When CE# and OE# are LOW, the data is placed on
the data bus and the processor can read the data.
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
In-System
In-Factory
21
MIN
0.9
11.4
MAX
2.2
12.6
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©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
STANDBY MODE
DEVICE RESET
Icc supply current is reduced by applying a logic
HIGH level on CE# and RST# to enter the standby
mode. In the standby mode, the outputs are placed in
High-Z. Applying a CMOS logic HIGH level on CE# and
RST# reduces the current to ICC3 (MAX). If the device is
deselected during an ERASE operation or during programming, the device continues to draw current until
the operation is complete.
To correctly reset the Flash memory devices, the
RST# signal must be asserted (RST# = VIL) for a minimum of tRP. After reset, the devices can be accessed for
a READ operation with a delayed access time of tRWH
from the rising edge of RST#. The circuitry used for
generating the RST# signal needs to be common with
the rest of the system reset to ensure that correct system initialization occurs. Please refer to the timing diagram for further details.
AUTOMATIC POWER SAVE MODE (APS)
POWER-UP SEQUENCE
Substantial power savings are realized during periods when the array is not being read and the device is in
the active mode. During this time the device switches
to the automatic power save mode. When the device
switches to this mode, ICC is reduced to a level comparable to ICC3. Further power savings can be realized by
applying a logic HIGH level on CE# to place the device
in standby mode. The low level of power is maintained
until another operation is initiated. In this mode, the I/
Os retain the data from the last memory address read
until a new address is read. This mode is entered automatically if no address or control signals toggle.
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
The following power-up sequence is recommended
to properly initialize internal chip operations:
• At power-up, RST# should be kept at VIL for 2µs
after VCC reaches VCC (MIN).
• VCCQ should not come up before VCC.
• V PP should be kept at V IL to maximize data
integrity.
When the power-up sequence is completed, RST#
should be brought to VIH. To ensure a proper power-up,
the rise time of RST# (10%–90%) should be <10µs.
22
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PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
**Maximum DC voltage on VPP may overshoot to +13.5V
for periods <20ns.
ABSOLUTE MAXIMUM RATINGS*
Voltage to Any Ball Except VCC and VPP
with Respect to VSS ....................... -0.5V to +2.45V
VPP Voltage (for BLOCK ERASE and PROGRAM
with Respect to VSS) ................. -0.5V to +13.5V**
VCC and VCCQ Supply Voltage
with Respect to VSS ....................... -0.3V to +2.45V
Output Short Circuit Current ............................... 100mA
Operating Temperature Range ............ -40oC to +85oC
Storage Temperature Range ............... -55oC to +125oC
Soldering Cycle .......................................... 260oC for 10s
OPERATING CONDITIONS
PARAMETER
SYMBOL
MAX
UNITS
-40
+85
oC
VCC
1.70
1.90
V
VCC supply voltage (MT28F321P20)
VCC
1.80
2.20
V
I/O supply voltage (MT28F321P18)
VCCQ
1.70
1.90
V
I/O supply voltage (MT28F321P20)
VCCQ
1.80
2.20
V
VPP voltage
VPP1
0.9
2.2
V
Operating temperature
tA
VCC supply voltage (MT28F321P18)
VPP in-factory programming voltage
Block erase cycling
MIN
VPP2
11.4
12.6
V
VPP = VPP1
VPP1
–
100,000
Cycles
VPP = VPP2
VPP2
–
100
Cycles
NOTE
1
NOTE: 1. VPP = VPP2 is a maximum of 10 cumulative hours.
Figure 10
AC Input/Output Reference Waveform
VCC
Input
VCC/2
VCCQ/2
Test Points
Output
VSS
AC test inputs are driven at VCC for a logic 1 and VSS for a logic 0. Input timing begins at VCC/2, and output timing ends
at VCCQ/2. Input rise and fall times (10% to 90%) < 5ns.
Figure 11
Output Load Circuit
VCC
14.5K
I/O
14.5K
30pF
VSS
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
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PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
DC CHARACTERISTICS1
VCC/VCCQ = 1.70V–1.90V
or 1.80V–2.20V
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
Input Low Voltage
VIL
0
0.4
V
2
Input High Voltage
VIH
VCCQ - 0.4V
VCCQ
V
2
Output Low Voltage
IOL = 100µA
VOL
–
0.10
V
Output High Voltage
IOH = -100µA
VOH
VCCQ - 0.1V
–
V
VPP Lockout Voltage
VPPLK
–
0.4
V
VPP During PROGRAM/ERASE Operations
VPP1
0.9
2.2
V
VPP2
11.4
12.6
V
VCC Program/Erase Lock Voltage
VLKO
1
–
V
Input Leakage Current
IL
–
1
µA
Output Leakage Current
IOZ
–
1
µA
VCC Random Read Current, 70ns cycle
ICC1
–
15
mA
3, 4
VCC Page Mode Read Current, 70ns/30ns cycle
ICC2
–
5
mA
3, 4
VCC Standby Current
ICC3
–
50
µA
VCC Program Current
ICC4
–
55
mA
VCC Erase Current
ICC5
–
65
mA
VCC Erase Suspend Current
ICC6
–
50
µA
5
VCC Program Suspend Current
ICC7
–
50
µA
5
Read-While-Write Current
ICC8
–
80
mA
VPP Current
(Read, Standby, Erase Suspend,
Program Suspend)
VPP = VPP1
VPP = VPP2
IPP1
–
–
1
200
µA
µA
NOTE: 1.
2.
3.
4.
5.
All currents are in RMS unless otherwise noted.
VIL may decrease to -0.4V and VIH may increase to VCCQ + 0.3V for durations not to exceed 20ns.
Test conditions: Vcc = VCC (MAX), CE# = VIL, OE# = VIH. All other inputs = VIH or VIL.
APS mode reduces ICC to approximately ICC3 levels.
ICC6 and ICC7 values are valid when the device is deselected. Any READ operation performed while in suspend mode will
have an additional current draw of suspend current (ICC6 or ICC7).
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
24
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©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
CAPACITANCE
(TA = +25ºC; f = 1 MHz)
PARAMETER/CONDITION
SYMBOL
TYP
MAX
UNITS
C
7
12
pF
COUT
9
12
pF
MAX
80
80
80
30
30
200
25
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
MAX
90
90
90
35
30
250
25
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
Input Capacitance
Output Capacitance
READ CYCLE TIMING REQUIREMENTS1
MT28F321P20 (VCC = 1.80V–2.20V)
-70
PARAMETER
READ cycle time
Address to output delay
CE# LOW to output delay
Page address access
OE# LOW to output delay
RST# HIGH to output delay
CE# or OE# HIGH to output High-Z
Output hold from address, CE# or OE# change
SYMBOL
tRC
tAA
tACE
tAPA
tAOE
tRWH
tOD
tOH
MIN
-80
MAX
70
70
70
30
25
200
15
0
MIN
0
READ CYCLE TIMING REQUIREMENTS1
MT28F321P18 (VCC = 1.70V–1.90V)
-90
PARAMETER
READ cycle time
Address to output delay
CE# LOW to output delay
Page address access
OE# LOW to output delay
RST# HIGH to output delay
CE# or OE# HIGH to output High-Z
Output hold from address, CE# or OE# change
SYMBOL
tRC
tAA
tACE
tAPA
tAOE
tRWH
tOD
tOH
MIN
0
NOTE: 1. See Figures 11 and 12 for timing requirements and load configuration.
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
WRITE CYCLE TIMING REQUIREMENTS
PARAMETER
HIGH recovery to WE# going LOW
CE# setup to WE# going LOW
Write pulse width
Data setup to WE# going HIGH
Address setup to WE# going HIGH
CE# hold from WE# HIGH
Data hold from WE# HIGH
Address hold from WE# HIGH
Write pulse width HIGH
RST# pulse width
WP# setup to WE# going HIGH
VPP setup to WE# going HIGH
Write recovery before READ
WP# hold from valid SRD
VPP hold from valid SRD
WE# HIGH to data valid
SYMBOL
tRS
tCS
tWP
tDS
tAS
tCH
tDH
tAH
tWPH
tRP
tRHS
tVPS
tWOS
tRHH
tVPPH
tWB
-70/-80/-90
MIN
MAX
150
0
50
50
50
0
0
9
30
100
0
200
50
0
0
tAA + 50
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-70/-80/-90
TYP
MAX
40
800
320
6400
8
10, 000
0.3
6
0.5
6
5
10
5
20
UNITS
ms
ms
µs
s
s
µs
µs
ERASE AND PROGRAM TIMING REQUIREMENTS
PARAMETER
4KW block program time
32KW block program time
Word program time
4KW block erase time
32KW block erase time
Program suspend latency
Erase suspend latency
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
SINGLE ASYNCHRONOUS READ OPERATION
A0–A20
VIH
VALID ADDRESS
VIL
tAA
tRC
tOD
VIH
CE#
VIL
tACE
VIH
OE#
VIL
tOH
VIH
WE#
tAOE
VIL
VOH
DQ0–DQ15
RST#
High-Z
VALID OUTPUT
VOL
tRWH
VIH
VIL
UNDEFINED
READ TIMING PARAMETERS
MT28F321P20 (VCC = 1.80V–2.20V)
READ TIMING PARAMETERS
MT28F321P18 (VCC = 1.70V–1.90V)
-70
SYMBOL
tAA
MIN
tACE
tAOE
tRC
tRWH
tOD
tOH
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
0
-80
MAX
70
MIN
-90
MAX
80
UNITS
ns
70
25
80
30
ns
ns
tACE
70
200
15
80
200
25
ns
ns
ns
tRC
ns
tOH
0
SYMBOL
tAA
MIN
tAOE
tRWH
tOD
27
0
MAX
90
UNITS
ns
90
30
ns
ns
90
250
25
ns
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
ASYNCHRONOUS PAGE MODE READ OPERATION
VIH
A3–A20
VALID ADDRESS
VIL
tRC
VIH
A0–A2
VALID
ADDRESS
VALID ADDRESS
VIL
VALID
ADDRESS
VALID
ADDRESS
tAA
tOD
VIH
CE#
VIL
tACE
VIH
OE#
VIL
VIH
WE#
VIL
tAOE
VOH
DQ0–DQ15
tAPA
VALID
OUTPUT
High-Z
VOL
VALID
OUTPUT
tOH
VALID
OUTPUT
VALID
OUTPUT
tRWH
VIH
RST#
VIL
UNDEFINED
READ TIMING PARAMETERS
MT28F321P20 (VCC = 1.80V–2.20V)
READ TIMING PARAMETERS
MT28F321P18 (VCC = 1.70V–1.90V)
-70
SYMBOL
tAA
MIN
tACE
tAPA
tAOE
tRC
tRWH
tOD
tOH
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
0
-80
MAX
70
MIN
-90
MAX
80
UNITS
ns
70
30
80
30
ns
ns
tACE
25
70
200
30
80
200
ns
ns
ns
tAOE
15
25
ns
ns
tOD
0
SYMBOL
tAA
MIN
tAPA
tRC
tRWH
tOH
28
0
MAX
90
UNITS
ns
90
35
ns
ns
30
90
250
ns
ns
ns
25
ns
ns
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©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
TWO-CYCLE PROGRAMMING/ERASE OPERATION
A0–A20
VIH
VALID ADDRESS
VALID ADDRESS
VIL
tAS
VALID ADDRESS
tAH
VIH
CE#
VIL
tCS
tWOS
tCH
VIH
OE#
VIL
tWPH
VIH
WE#
VIL
VOH
DQ0–DQ15
VOL
High-Z
CMD/
DATA
CMD
tRS
STATUS
tDS
tDH
VIH
RST#
tWB
tWP
VIL
tRHS
tRHH
tVPS
tVPPH
VIH
WP#
VIL
VIPPH
VIPPLK
VPP
VIL
UNDEFINED
WRITE TIMING PARAMETERS
SYMBOL
tRS
tCS
tWP
tDS
tAS
tCH
tDH
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
-70/-80/-90
MIN
MAX
UNITS
SYMBOL
tAH
tRHS
-70/-80/-90
MIN
MAX
9
0
150
0
50
ns
ns
ns
50
50
ns
ns
tWOS
tRHH
200
50
0
0
0
ns
ns
tVPPH
0
tVPS
tWB
29
UNITS
ns
ns
ns
ns
ns
tAA + 50
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
RESET OPERATION
CE#
VIH
VIL
RST#
VIH
VIL
tRP
OE#
VIH
VIL
DQ0–DQ15
VOH
VOL
tRWH
READ AND WRITE TIMING PARAMETERS
SYMBOL
tRWH
tRP
-70/-80
MIN
MAX
200
100
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
-90
MIN
100
MAX
250
UNITS
ns
ns
30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
Table 11
CFI
OFFSET
DATA
DESCRIPTION
00
2Ch
Manufacturer code
01
B2h
Top boot block device code
B3h
Bottom boot block device code
02–0F
reserved
10, 11
0051, 0052
12
0059
13, 14
0003, 0000
Primary OEM command set
15, 16
0039, 0000
Address for primary extended table
17, 18
0000, 0000
Alternate OEM command set
19, 1A
0000, 0000
Address for OEM extended table
1B
0017
VCC MIN for Erase/Write; Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD
Reserved
“QR”
“Y”
1C
0022
VCC MAX for Erase/Write; Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in BCD
1D
00B4
VPP MIN for Erase/Write; Bit7–Bit4 Volts in Hex; Bit3–Bit0 100mV in BCD
1E
00C6
VPP MAX for Erase/Write; Bit7–Bit4 Volts in Hex; Bit3–Bit0 100mV in BCD
1F
0003
Typical timeout for single byte/word program, 2n µs, 0000 = not supported
20
0000
Typical timeout for maximum size multiple byte/word program, 2n µs, 0000 = not
supported
21
0009
Typical timeout for individual block erase, 2n ms, 0000 = not supported
22
0000
Typical timeout for full chip erase, 2n ms, 0000 = not supported
23
000C
Maximum timeout for single byte/word program, 2n µs, 0000 = not supported
24
0000
Maximum timeout for maximum size multiple byte/word program, 2n µs, 0000 = not
supported
25
0003
Maximum timeout for individual block erase, 2n ms, 0000 = not supported
26
0000
Maximum timeout for full chip erase, 2n ms, 0000 = not supported
27
0016
Device size, 2n bytes
28
0001
Bus Interface x16 = 1
29
0000
Flash device interface description 0000 = async
2A, 2B
0000, 0000
2C
0003
2D, 2E
0037, 0000
Top boot block device erase block region information 1, 8 blocks …
0007, 0000
Bottom boot block device erase block region information 1, 8 blocks …
0000, 0001
Top boot block device…..of 8KB
0020, 0000
Bottom boot block device…..of 8KB
31, 32
0006, 0000
15 blocks of ….
33, 34
0000, 0001
……64KB
2F, 30
Maximum number of bytes in multi-byte program or page, 2n
Number of erase block regions within device (4K words and 32K words)
(continued on the next page)
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
31
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PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
Table 11
CFI (continued)
OFFSET
DATA
35, 36
0007, 0000
Top boot block device……48 block of
0037, 0000
Bottom boot block device……48 block of
37, 38
DESCRIPTION
0020, 0000
Top boot block device……64KB
0000, 0001
Bottom boot block device……64KB
39, 3A
0050, 0052
“PR”
3B
0049
“I”
3C
0030
Major version number, ASCII
3D
0031
Minor version number, ASCII
3E
3F
40
41
00E6
0002
0000
0000
Optional Feature and Command Support
Bit 0 Chip erase supported no = 0
Bit 1 Suspend erase supported = yes = 1
Bit 2 Suspend program supported = yes = 1
Bit 3 Chip lock/unlock supported = no = 0
Bit 4 Queued erase supported = no = 0
Bit 5 Instant individual block locking supported = yes = 1
Bit 6 Protection bits supported = yes = 1
Bit 7 Page mode read supported = yes = 1
Bit 8 Synchronous read supported = no = 0
Bit 9 Simultaneous operation supported = yes = 1
42
0001
Program supported after erase suspend = yes
43, 44
0003, 0000
45
0018
VCC supply optimum, 00 = not supported, Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in
BCD
46
00C0
VPP supply optimum, 00 = not supported, Bit7–Bit4 Volts in BCD; Bit3–Bit0 100mV in
BCD
Number of protection register fields in JEDEC ID space
Bit 0 block lock status active = yes; Bit 1 block lock down active = yes
47
0001
48, 49
0080, 0000
Lock bytes LOW address, lock bytes HIGH address
4A, 4B
0003, 0003
2n factory programmed bytes, 2n user programmable bytes
4C
0002
Background Operation
0000 = Not used
0001 = 4% block split
0002 = 12% block split
0003 = 25% block split
0004 = 50% block split
4D
0000
Burst Mode Type
0000 = No burst mode
00x1 = 4 words MAX
00x2 = 8 words MAX
00x3 = 16 words MAX
001x = Linear burst, and/or
002x = Interleaved burst, and/or
004x = Continuous burst
(continued on the next page)
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
32
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
Table 11
CFI (continued)
OFFSET
DATA
4E
0002
Page
0000
0001
0002
0003
0004
4F
0000
Not used
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
DESCRIPTION
Mode Type
= No page mode
= 4-word page
= 8-word page
= 16-word page
= 32-word page
33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
48-BALL FBGA
0.80 ±0.075
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or
62% Sn, 37% Pb, 2%Ag
SOLDER BALL PAD: Ø 0.27mm
C
0.10 C
SUBSTRATE: PLASTIC LAMINATE
ENCAPSULATION MATERIAL: EPOXY NOVOLAC
7.00 ±.10
5.25
BALL #1 ID
0.75
TYP
BALL A8
BALL #1 ID
48X Ø 0.35 TYP
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE
PRE-REFLOW DIAMETER
IS Ø 0.33
BALL A1
12.00 ± 0.10
CL
3.75
1.875 ±0.05
0.75
TYP
6.00 ±0.05
CL
1.20 MAX
2.625 ±0.05
3.50 ±0.05
NOTE: 1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.27mm per side.
DATA SHEET DESIGNATION
Preliminary:
This data sheet contains initial characterization limits that are subject to change upon full
characterization of production devices.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc.
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
34
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
PRELIMINARY
2 MEG x 16
PAGE FLASH MEMORY
REVISION HISTORY
Rev. 3, PRELIMINARY ....................................................................................................................................................... 7/02
• Added Programming the Chip Protection Register section
• Updated Status Register section
• Changed low power consumption voltage from 1.80V to 2.20
• Updated command descriptions
• Updated Read-While-Write/EraseConcurrency section
• Updated timing diagrams
Rev. 2, PRELIMINARY ....................................................................................................................................................... 3/02
• Added Notes 2 and 3 to DC Characteristics table
Original document, PRELIMINARY, Rev. 1 ................................................................................................................... 1/02
2 Meg x 16 Page Flash Memory
MT28F321P20_3.p65 – Rev. 3, Pub. 7/02
35
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.