MICRON MT28F1284W18

8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
FLASH MEMORY
MT28F1284W18
1.8V Low Voltage, Extended Temperature
Features
Figure 1: 56-Ball VFBGA
Dedicated commands to decrease programming times for
both in-factory and in-system operations
Fast programming algorithm (FPA) for fast PROGRAM
operation
16-word page
Flexible 8Mb multipartition architecture
Single word (16-bit) data bus
Support for true concurrent operation with zero latency
Basic configuration:
• 135 individually programmable/erasable blocks
• 16 partitions (8Mb each for code and data storage)
Operating Voltage
• VCC = 1.70V (MIN)–1.95V (MAX)
• VCCQ = 1.70V (MIN)–2.24V (MAX)
VPP = 1.8V (TYP) for in-system PROGRAM/ERASE
• 12V ±5% (HV) VPP tolerant (factory programming
compatibility)
Random access time: 60ns @ 1.70V VCC
Burst mode read access
• MAX clock rate: 66 MHz (tCLK = 15ns)
• MAX clock rate: 54 MHz (tCLK = 18.5ns)
• Burst latency 60ns @1.70V VCC and 66 MHz
• 4 word, 8 word, 16 word, and continuous burst modes
• tACLK: 14ns @ 1.70V VCC and 54 MHz
• tACLK: 11ns @ 1.70V VCC and 66 MHz
Page mode read access
• Interpage read access: 60ns @ 1.70V VCC
• Intrapage read access: 15ns @ 1.70V VCC
Low power consumption (VCC = 1.95V)
• Burst read @ 66 MHz <10mA (TYP)
• Standby < 50µA(TYP)
• Automatic power save (APS)
Enhanced program and erase suspend options
• ERASE-SUSPEND-to-READ within same partition
• PROGRAM-SUSPEND-to-READ within same
partition
• ERASE-SUSPEND-to-PROGRAM within same
partition
Dual 64-bit chip protection registers for security purposes
Cross-compatible command support
• Extended command set
• Common flash interface
Programmable WAIT# configuration
Clock suspend
100,000 ERASE cycles per block
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
‡PRODUCTS
1
2
3
4
5
6
7
8
A
A11
A8
VSS
VCC
VPP
A18
A6
A4
B
A12
A9
A20
CLK
RST#
A17
A5
A3
C
A13
A10
A21
ADV#
WE#
A19
A7
A2
D
A15
A14
WAIT#
A16
DQ12
WP#
A22
A1
E
VCCQ
DQ15
DQ6
DQ4
DQ2
DQ1
CE#
A0
F
VSS
DQ14
DQ13
DQ11
DQ10
DQ9
DQ0
OE#
G
DQ7
VSSQ
DQ5
VCC
DQ3
VCCQ
DQ8
VSSQ
Top View
NOTE:
1. See Table 3 for ball descriptions.
2. See Figure 35 for mechanical drawing.
Options
Marking
Timing
• 60ns access
• 70ns access
Burst Frequency
• 54 MHz
• 66 MHz1
Boot Block Configuration
• Top
• Bottom
Package
• 56-ball VFBGA (Standard) 7 x 8 ball
grid
• 56-ball VGBGA (Lead-free) 7 x 8 ball
grid2
Operating Temperature Range
• Extended (-40ºC to +85ºC)
-60
-70
5
6
T
B
FQ
BQ
ET
NOTES: 1. Contact factory for availability.
2. Contact factory for details.
Part Number Example:
MT28F1284W18FQ-705 TET
1
©2003 Micron Technology, Inc. All rights reserved.
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Architecture and Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Command State Machine (CSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Command State Machine Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Clear Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Read Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Read Device Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Read Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Read Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Read Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Asynchronous/Page Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Burst Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Read Configuration Register (RCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
WAIT# Signal Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Latency Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
WAIT# Signal Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Hold Data Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
WAIT# Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Burst Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Burst Wrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Programming Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Conventional Word Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Fast Programming Algorithm (FPA) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
ERASE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PROGRAM SUSPEND, PROGRAM RESUME, ERASE SUSPEND, ERASE RESUME Commands . . . . . . . . . . . . . . . .27
READ-While-PROGRAM/ERASE Concurrency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Block Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Locked Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Reading the Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Programming the Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Locking the Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
VPP/VCC Program and Erase Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Automatic Power Save (APS) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Electrical Specificatons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Appendix A: CFI Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Appendix B: CSM Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
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Figure 18:
Figure 19:
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Figure 21:
Figure 22:
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Figure 24:
Figure 25:
Figure 26:
Figure 27:
Figure 28:
Figure 29:
Figure 30:
Figure 31:
Figure 32:
Figure 33:
Figure 34:
Figure 35:
56-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Partition Boundary Wrapping (Bottom Boot Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Latency Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Hold Data Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Conventional Word Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Fast Programming Algorithm (FPA) Flowchart (in-factory only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Block Erase Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Program Suspend/Program Resume Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Erase Suspend/Erase Resume Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Block Locking State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Locking Operations Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Protection Register Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
VCC and VPP at Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Reset Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
AC Input/Output Reference Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Output Load Circuit1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Single Asynchronous READ Operation (Nonlatched Mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Latched Asynchronous READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Page Mode READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Single Burst READ Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
READ Timing Parameters for Four-Word BURST Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
WAIT# Functionality for End-of-Word Line (EOWL) Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
WAIT# Signal in Burst Non-READ ARRAY Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
WAIT# Signal in Asynchronous READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Two-Cycle WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Clock Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Asynchronous READ-to-WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
WRITE-to-Asynchronous-READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Burst READ-to-WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Write-to-BURST READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
56-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
09005aef80b425b4
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4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Table 20:
Table 21:
Table 22:
Table 23:
Table 24:
Table 25:
Table 26:
Table 27:
Cross-Reference for Abbreviated Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Valid Part Number Combinations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Command Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Command Codes and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Status Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Status Register SR7 and SR0 Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Clock Frequency vs. First Access Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Sequence and Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Simultaneous Operations Allowed in the Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Block Locking State Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Write Protection Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Device Identifier Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
VPP Range (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Reset Parameter Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Asynchronous READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Burst READ Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
WRITE Cycle Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
ERASE and PROGRAM Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
CFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Command State Machine Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
09005aef80b425b4
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5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
General Description
Please
refer
to
Micron’s
Web
site
www.micron.com/flash for the latest data sheet.
The MT28F1284W18 is a high-performance, highdensity, nonvolatile memory solution that can significantly improve system performance. This architecture
features a multipartition configuration that supports
READ-While-PROGRAM/ERASE operations with no
latency. An 8Mb partition size enables optimal design
flexibility.
A high-performance bus interface enables a fast
burst mode READ operation; a conventional asynchronous/page bus interface is provided as well. The burst
interface increases the data throughput, minimizing
the impact of the first data latency.
The MT28F1284W18 enables soft protection for
blocks, as read only, by configuring soft protection registers with dedicated command sequences. For security purposes, two 64-bit chip protection registers are
provided.
The embedded WORD PROGRAM and BLOCK
ERASE functions are fully automated by an on-chip
write state machine (WSM). An on-chip device status
register can be used to monitor the WSM status and
determine the progress of the PROGRAM/ERASE tasks.
at
Architecture and Memory Organization
The MT28F1284W18 Flash device contains 16 separate partitions (banks) of memory for simultaneous
READ and PROGRAM/ERASE operations. Burst READs
can cross partition boundaries, but the user must
ensure that the burst does not extend into a partition
that is actively programming or erasing. During a PROGRAM/ERASE operation, any of the fifteen other partitions may be read. Note that only two partitions can
operate simultaneously. Partitions are configured as
follows:
• Partition 0 (bottom boot) or partition 15 (top
boot) contains eight 8K-word parameter blocks
and seven 64K-word main blocks.
• The other 15 partitions contain eight 64K-word
main blocks and comprise one-sixteenth of the
total memory.
Figure 3 depicts the memory organization.
Figure 2: Functional Block Diagram
PR Lock
Query
DQ0–DQ15
OTP
Manufacturer’s ID
Data Input
Buffer
Device ID
Block Lock
Data
Register
RCR
RST#
CE#
WE#
Status
Reg.
CSM
OE#
Program/
Erase
Pump Voltage
Generators
WSM
DQ0–DQ15
Output
Multiplexer
I/O Logic
A0–A22
Address
Input
Buffer
Address
CNT WSM
ADV#
CLK
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MT28F1284W18_D.fm - Rev. D, 11/03 EN
Address Latch
Y/Z DEC
Y/Z Gating/Sensing
X DEC
Bank 0 Blocks
"
"
Address
Multiplexer
"
"
Y/Z DEC
Y/Z Gating/Sensing
X DEC
Bank 15 Blocks
Output
Buffer
WAIT#
BSM
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 3: Memory Organization
8
7
010000–01FFFF
00E000–00FFFF
8
0
000000–001FFF
…
112
700000–70FFFF
64
111
6F0000–6FFFFF
104
680000–68FFFF
64
103
670000–67FFFF
64
96
600000–60FFFF
…
…
64
…
…
64
…
…
…
…
780000–78FFFF
770000–77FFFF
…
…
…
…
120
119
…
Partition 15
64
64
64
64
…
15
0F0000–0FFFFF
64
…
64
8
7E0000–7EFFFF
64
8
080000–08FFFF
64
7
070000–07FFFF
…
070000–07FFFF
…
14
…
64
…
080000–08FFFF
…
15
…
64
126
… …
F00000–0FFFFF
64
…
22
7F0000–7F1FFF
…
64
…
100000–10FFFF
…
23
…
64
127
…
170000–17FFFF
8
…
30
128Mb
7FE000–7FFFFF
…
64
…
180000–18FFFF
…
31
…
64
BLK#
134
…
1F0000–1FFFFF
SIZE(KW)
8
…
38
Partition 12 Partition 13 Partition 14
64
64
……….
64
…
680000–68FFFF
…
119
…
64
Partition 0 Partition 1
…
770000–77FFFF
…
126
…
64
…
780000–78FFFF
… …
127
…
64
…
…
128Mb
7F0000–7FFFFF
…
BLK#
134
…
Parameter
Partition 0
Partition 1 Partition 2 Partition 3
….
Partition 14 Partition 15
SIZE(KW)
64
Top Boot Block Device
Parameter
Bottom Boot Block Device
64
0
000000–00FFFF
NOTE:
1. Total number of blocks: 8 parameter + 127 main = 135.
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Device Marking
Due to the size of the package, the Micron® standard part number is not printed on the top of each
device. Instead, an abbreviated device mark com-
Table 1:
prised of a five-digit alphanumeric code is used. The
abbreviated device marks are cross-referenced to the
Micron part numbers in Table 1.
Cross-Reference for Abbreviated Device Marking
PRODUCT PART NUMBER
ENGINEERING
SAMPLES
QUALIFICATION
SAMPLES
PRODUCTION
MARKING
FX616
FX615
FX618
FX617
FY616
FY615
FY618
FY617
FW616
FW615
FW618
FW617
MT28F1284W18FQ-606 TET
MT28F1284W18FQ-606 BET
MT28F1284W18FQ-705 TET
MT28F1284W18FQ-705 BET
Part Numbering Information
Micron’s low-power devices are available with several different combinations of features (see Figure 4).
Valid combinations of features and their corresponding part numbers are listed in Table 2.
Figure 4: Part Number Chart
MT 28F 1284W18 FQ-60 6 M B ET ES
Micron Technology
Production Status
Flash Family
28F = Dual-Supply Flash
Blank = Production
ES = Engineering Samples
QS = Qualification Samples
Density/Organization/Banks
Operating Temperature Range
128 = 128Mb (8,192K x 16)
4 = 16 banks (all banks have the same dimensions)
ET = Extended (-40ºC to +85ºC)
Read Mode Operation
W = Asynchronous/Page/Burst Read
B = Bottom boot
T = Top boot
Operating Voltage Range
Manufacturer ID
Boot Block Starting Address
18 = 1.70V–1.95V Vcc
1.70V–2.24V VccQ
M = Micron [2Ch]
Package Code
Burst Mode Frequency
5 = 54 MHz
6 = 66 MHz
FQ = 56-ball VFBGA (Standard) 7 x 8 grid
BQ = 56-ball VFBGA (Lead-free) 7 x 8 grid
Access Time
-60 = 60ns
-70 = 70ns
Table 2:
Valid Part Number Combinations
ACCESS TIME
(ns)
BOOT BLOCK
STARTING
ADDRESS
BURST
FREQUENCY
(MHz)
OPERATING
TEMPERATURE
RANGE
MT28F1284W18FQ-606 BET
60
Bottom
66
-40oC to +85oC
MT28F1284W18FQ-606 TET
60
Top
66
-40oC to +85oC
MT28F1284W18FQ-705 BET
70
Bottom
54
-40oC to +85oC
MT28F1284W18FQ-705 TET
70
Top
54
-40oC to +85oC
PART NUMBER
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8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 3:
Ball Descriptions
58-BALL FBGA
NUMBERS
SYMBOL
TYPE
DESCRIPTION
E8, D8, C8, B8, A8,
B7, A7, C7, A2, B2,
C2, A1, B1, C1, D2,
D1, D4, B6, A6, C6,
B3, C3, D7
B4
A0–A22
Input
Address inputs: Inputs for the addresses during READ and WRITE
operations. All addresses are internally latched during WRITE cycles and
synchronous READ cycles. During asynchronous READ cycles, A0–A3 are not
internally latched.
CLK
Input
C4
ADV#
Input
E7
CE#
Input
F8
OE#
Input
C5
WE#
Input
B5
RST#
Input
D6
WP#
Input
F7, E6, E5, G5, E4, G3,
E3, G1, G7, F6, F5, F4,
D5, F3, F2, E2
DQ0–
DQ15
Input/
Output
D3
WAIT#
Output
A4, G4
E1, G6
G2, G8
A3, F1
A5
VCC
VCCQ
VSSQ
VSS
VPP
Supply
Supply
Supply
Supply
Supply/
Input
Clock: Synchronizes the Flash device to the system operating frequency
during burst mode READ operations. When configured for burst mode
READs, address is latched on the first rising (or falling, depending upon the
read configuration register setting) CLK edge when ADV# is active or upon
a rising ADV# edge, whichever occurs first. CLK is ignored during
asynchronous page access READ and WRITE operations.1
Address Valid: Indicates that a valid address is present on the address inputs.
Addresses are latched on the rising edge of ADV# during READ operations.1
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device
goes into standby power mode if neither PROGRAM nor ERASE operations
are pending.
Output Enable: Enables the output buffers when LOW. When OE# is HIGH,
the output buffers are disabled.
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW,
the cycle is either a WRITE to the command state machine (CSM) or to the
memory array.
Reset: When RST# is a logic LOW, the device is in reset mode, which drives
the outputs to High-Z and resets the write state machine. When RST# is at
logic HIGH, the device is in standard operation. When RST# transitions from
logic LOW to logic HIGH, the device resets all blocks to locked and defaults
to the read array mode.
Write Protect: Controls the lock down function of the flexible locking
feature.
Data Inputs/Outputs: Inputs array data on the second CE# and WE# cycle
during PROGRAM operation. Inputs commands to the command user
interface when CE# and WE# are active. DQ0–DQ15 output data when CE#
and OE# are active.
Wait: Provides data valid feedback during burst read access. The signal is
gated by CE#. The WAIT# signal polarity is set by RCR10 in the RCR.
Device Power Supply: [1.70V–1.95V] Supplies power for device operation.
I/O Power Supply: [1.70V–2.24] Supplies power for input/output buffers.
I/O Ground: Do not float any ground ball.
Supply Ground: Do not float any ground ball.
Program/Erase Enable: [0.9V–1.95V or 11.4V–12.6V] Operates as input at
logic levels to control complete device protection. Provides factory
programming compatibility, and acts as a current source, when driven to
11.4V–12.6V.
NOTE:
1. The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous/page mode.
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Command State Machine (CSM)
Command State Machine Activation
Commands are issued to the command state
machine (CSM) using standard microprocessor write
timings. The CSM acts as an interface between external microprocessors and the internal write state
machine (WSM). Table 5 defines the available commands and provides data for each of the bus cycles,
and Table 6 provides the command descriptions. Program and erase algorithms are automated by an onchip WSM. During a PROGRAM or ERASE cycle, the
CSM informs the WSM that a PROGRAM or ERASE
cycle has been requested. Table 27 shows the CSM
transition states.
Once a valid PROGRAM/ERASE command is
entered, the WSM executes the appropriate algorithm,
which generates the necessary timing signals to control the device internally to accomplish the requested
operation. A command is valid only if the exact
sequence is completed. After the WSM completes its
task, the WSM status bit (SR7) (see Table 7) is set to a
logic HIGH level (VIH), allowing the CSM to respond to
the full command set again.
Device operations are selected by entering an 8-bit
command code with conventional microprocessor
timings into an on-chip CSM through I/Os DQ0–DQ7.
The number of bus cycles required to activate a command is typically one or two. The first operation is
always a WRITE. Control signals CE# and WE# must be
at a logic LOW level (VIL), and OE# and RST# must be
at logic HIGH (VIH). The second operation, when
needed, can be a WRITE or a READ, depending upon
the command. During a READ operation, control signals CE#, ADV#, and OE# must be at a logic LOW level
(VIL), and WE# and RST# must be at logic HIGH (VIH).
Table 4 illustrates the bus operations for all the modes:
write, read, reset, standby, and output disable.
When the device is reset, internal reset circuitry initializes the chip to a read array mode of operation.
Changing the mode of operation requires that a command code be entered into the CSM. Users can verify
the status of the operations initiated by the CSM by
reading the status register. This single status register
permits monitoring of the progress of the various
operations that can take place on a memory partition.
Status register bits SR0–SR7 correspond to DQ0–DQ7
(see Table 7).
Table 4:
Bus Operations
MODE
RST#
CE#
ADV#
OE#
WE#
WAIT#
DQ0–DQ15
Read (array, status registers, device
identifier, or query)
Standby
Output disable
VIH
VIL
VIL
VIL
VIH
Active1
DOUT
VIH
VIH
VIH
VIL
X
X
X
VIH
X
VIH
High-Z
High-Z
High-Z
Reset
Write
VIL
VIH
X
VIL
X
X
X
VIH
X
VIL
1
Active
High-Z
High-Z
High-Z
DIN
NOTE:
1. The WAIT# signal is driven by CE#; polarity depends on RCR10. Valid only in synchronous mode only.
09005aef80b425b4
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10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 5:
Command Sequencing
FIRST BUS CYCLE
COMMAND
READ ARRAY
READ DEVICE IDENTIFIER
READ QUERY
READ STATUS REGISTER
CLEAR STATUS REGISTER
BLOCK ERASE SETUP
PROGRAM SETUP
FAST PROGRAMMING ALGORITHM
PROGRAM/ERASE SUSPEND
PROGRAM/ERASE RESUME
LOCK BLOCK
UNLOCK BLOCK
LOCK-DOWN BLOCK
PROTECTION PROGRAM
LOCK PROTECTION PROGRAM
SET READ CONFIGURATION REGISTER
NOTE:
OPERATION
ADDRESS1
DATA
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
PnA
PnA
PnA
PnA
XX
BA
WA
WA
XX
XX
BA
BA
BA
PA
LPA
RCRV
FFh
90h
98h
70h
50h
20h
40h/10h
30h
B0h
D0h
60h
60h
60h
C0h
C0h
60h
1. BA:
IA:
IC:
ID:
BBA:
Address within the block.
Identification code address.
Identifier code data.
Identification code data.
Block base address. The first address of a
particular block.
LPA: Lock protection register address
(BBA + 80h).
PA: Protection register address.
PBA: Partition base address. The very first
address of a particular partition.
PD: Data to be written at location PA.
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
SECOND BUS CYCLE
OPERATION
ADDRESS
DATA
READ
READ
READ
BBA + IA
PBA + QA
BA
IC
QD
SRD
WRITE
WRITE
WRITE
BA
WA
WA
D0h
WD
D0h
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
BA
BA
BA
PA
LPA
RCRV
01h
D0h
2Fh
PD
FFFDh
03h
PnA: Any address within a specific partition.
QA: Query code address.
QD: Query code data DQ[7:0].
RCRV:Data to be written into the read
configuration register presented on
A15–A0.
SRD: Data read from the status register.
WA: Word address of memory location to be
written.
WD: Data to be written at the location WA.
XX: Any valid address within the device.
11
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©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 6:
OPERATION
READ
PROGRAM
ERASE
SUSPEND
Command Codes and Descriptions
CODE
DEVICE
MODE
BUS
CYCLE
FFh
70h
Read Array
Read Status
Register
First
First
90h
Read Device
Identifier
First
98h
Read Query
First
50h
Clear Status
Register
First
40h
Program
Setup
First
10h
First
30h
Program
Setup
FPA Setup
D0h
FPA Confirm
20h
Erase Setup
D0h
Erase Confirm
B0h
Program/Erase
Suspend
D0h
Program/Erase
Resume
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DESCRIPTION
Places the addressed partition in read array mode.
This command places the addressed partition into read status
register mode. Reading the partition will output the contents of the
status register for the addressed partition. The device will
automatically enter this mode for the addressed partition after a
PROGRAM or ERASE operation has been initiated.
Puts the addressed partition into the read device identifier mode so
that reading the device will output the manufacturer/device codes,
configuration register data, block lock status, or protection register
data on DQ0–DQ15.
Puts the addressed partition into the read query mode so that
reading the partition will output common flash interface
information.
The WSM can set the block lock status (SR1), VPP status (SR3),
program status (SR4), and erase status (SR5) bits in the status register
to “1,” but it cannot clear them to “0.” SR1, SR3, SR4, and SR5 can
only be cleared by a device reset or by using the CLEAR STATUS
REGISTER command.
A two-cycle command: The first cycle prepares for a PROGRAM
operation, and the second cycle latches addresses and data and
initiates the WSM to execute the program algorithm. After the
second cycle, the device outputs status register data on the falling
edge of OE# or CE#, whichever occurs last.
Equivalent to Program Setup (40h).
First
This program command activates FPA mode. The first cycle prepares
for FPA operation. If the second cycle is an FPA CONFIRM
COMMAND (D0h), subsequent WRITEs provide program data. All
other commands are ignored once FPA mode begins.
Second If the previous command was FPA SETUP (30h), the CSM latches the
address and data and prepares the device for FPA mode.
First
Prepares the CSM for the ERASE CONFIRM command. If the next
command is not ERASE CONFIRM, the CSM will set both SR4 and SR5
of the status register to a “1,” place the partition into read status
register mode, and wait for another command.
Second If the previous command was an ERASE SETUP command, then the
CSM will close the address and data latches, and it will begin erasing
the block indicated on the address pins. The device will then output
status register data on the falling edge of OE# or CE#, whichever
occurs last.
First
Issuing this command will suspend the currently executing
PROGRAM/ERASE operation. The status register will indicate when
the operation has been successfully suspended by setting either the
program suspend (SR2) or erase suspend (SR6), and the WSM status
bit (SR7) to a “1” (ready). The WSM will continue to idle in the
suspend state, regardless of the state of all input control signals
except RST#, which will immediately reset the WSM and the
remainder of the chip if RST# is driven to VIL.
First
If a PROGRAM or ERASE operation is suspended (as indicated by SR2
or SR6), this command will resume the operation.
12
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ASYNC/PAGE/BURST FLASH MEMORY
Table 6:
Command Codes and Descriptions (continued)
OPERATION
BLOCK LOCKING
CODE
60h
DEVICE
MODE
01h
Block Lock
Setup
Lock Block
D0h
Unlock Block
2Fh
Lock Down
Block
Protection
Register
Program
Setup
PROTECTION
PROGRAM
C0h
SET READ
CONFIGURATION
REGISTER
60h
03h
Set Read
Configuration
Register Setup
Set Read
Configuration
Register Data
BUS
CYCLE
DESCRIPTION
First
Prepares the CSM for changes to the block locking status. See note 1.
Second If the previous command was BLOCK LOCK SETUP, the CSM will latch
the address and lock the block indicated on the address bus.
Second If the previous command was BLOCK LOCK SETUP, the CSM will latch
the address and unlock the block indicated on the address bus. If the
block had been previously set to lock down, this operation will have
no effect unless WP# is driven to VIH.
Second If the previous command was BLOCK LOCK SETUP, the CSM will latch
the address and lock down the block indicated on the address bus.
First
Prepares the CSM for a PROTECTION REGISTER PROGRAM operation.
The second cycle latches address and data, and starts the WSM’s
protection register program or lock algorithm. After the second
cycle, the device outputs status register data on the falling edge of
OE# or CE#, whichever occurs last. To read array data after
programming, issue a READ ARRAY command.
First
Prepares the RCR to be modified. See note 1.
Second If the previous command was SET READ CONFIGURATION REGISTER
SETUP, the configuration bits presented on the address bus will be
stored into the Read Configuration Register.
NOTE:
1. If the 60h command is not followed by D0h, 01h, 2Fh, or 03h, the CSM sets SR4 and SR5 to indicate a command
sequence error.
09005aef80b425b4
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ASYNC/PAGE/BURST FLASH MEMORY
Status Register
Clear Status Register
The status register allows the user to determine
whether the state of a PROGRAM/ERASE operation is
pending or complete.
The status register provides the status of the device
to the external microprocessor. During periods when
the WSM is active in a partition, that partition will
default to the read status register mode and can be
polled to determine the WSM status.
After monitoring the status register during a PROGRAM/ERASE operation in a partition, that partition
will remain in read status mode until a new command
is issued to the CSM. Table 7 defines the status register
bits.
The internal circuitry can set, but not clear, the
block lock status bit (SR1), the VPP status bit (SR3), the
program status bit (SR4), and the erase status bit (SR5)
of the status register. The CLEAR STATUS REGISTER
command (50h) allows the external microprocessor to
clear these status bits and synchronize to the internal
operations. When the status bits are cleared, the state
of the device does not change.
Table 7:
Status Register Bit Definitions
STATUS BIT # STATUS REGISTER BIT
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
ERASE SUSPEND STATUS
1 = BLOCK ERASE Suspended
0 = BLOCK ERASE in Progress/
Completed
ERASE STATUS
1 = Error in Block Erasure
0 = Successful BLOCK ERASE
PROGRAM STATUS
1 = Error in PROGRAM
0 = Successful PROGRAM
VPP STATUS
1 = VPP Low Detect, Operation Abort
0 = VPP = OK
PROGRAM SUSPEND STATUS
1 = PROGRAM Suspended
0 = PROGRAM in Progress/Completed
BLOCK LOCK STATUS
1 = PROGRAM/ERASE Attempted on a
Locked Block; Operation Aborted
0 = No Operation to Locked Blocks
FAST PROGRAMMING
ALGORITHM STATUS
0 = Partition is busy, but only if SR7 = 0
1 = Another partition is busy, but only
if SR7 = 0
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DESCRIPTION
SR7 indicates ERASE or PROGRAM completion in the device.
SR6–SR1 are invalid while SR7 = 0. See Table 8 for valid SR7
and SR0 combinations.
When ERASE SUSPEND is issued, WSM halts execution and
sets both SR7 and SR6 bits to “1.” SR6 bit remains set to “1”
until an ERASE RESUME command is issued.
When this bit is set to “1,” WSM has applied the maximum
number of erase pulses to the block and is still unable to
verify successful block erasure.
When this bit is set to “1,” WSM has attempted but failed to
program a word.
The VPP status bit does not provide continuous indication of
the VPP level. The WSM interrogates the VPP level only after
the PROGRAM or ERASE command sequences have been
entered and informs the system if VPP is LOW. The VPP level
is also checked before the PROGRAM/ERASE is verified by
the WSM.
When PROGRAM SUSPEND is issued, WSM halts execution
and sets both SR7 and SR2 bits to “1.” SR2 bit remains set to
“1” until a PROGRAM RESUME command is issued.
If a PROGRAM or ERASE operation is attempted to a locked
block, SR1 is set by the WSM. The operation specified is
aborted and the device is returned to read status mode.
Addressed partition is erasing or programming. In FPA
mode, SR0 indicates a data stream word has finished
programming or verifying, depending on the FPA phase.
Refer to Table 8 for valid SR7 and SR0 combinations.
14
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Table 8:
Status Register SR7 and SR0 Description
SR7
SR0
0
0
0
1
1
0
1
1
DESCRIPTION
The addressed partition is performing a PROGRAM/ERASE operation.
FPA: Device is finished programming or verifying data or is ready for data.
A partition other than the one currently addressed is performing a PROGRAM/ERASE operation.
FPA: the device is either programming or verifying data.
No PROGRAM/ERASE operation is in progress in any partition. Erase and program suspend bits
(SR6 and SR2) indicate whether other partitions are suspended.
Will not occur in standard PROGRAM/ERASE operations.
FPA: This combination will not occur.
READ Operations
Read Query
The following READ operations are available: READ
ARRAY, READ DEVICE IDENTIFIER, READ QUERY,
and READ STATUS REGISTER.
Note that READ DEVICE IDENTIFIER, READ
QUERY, and READ STATUS REGISTER will read in
either asynchronous or single burst mode.
The read query mode outputs common flash interface (CFI) data when the device is read. (See Table 26
on page 59 for more information.) Two bus cycles are
required for this operation. It is possible to access the
query by writing the read query command code 98h on
DQ0–DQ7. Control signals CE#, ADV#, and OE# must
be at a logic LOW level (VIL) and WE# and RST# must
be at a logic HIGH level (VIH) to read data from the
query. The CFI data structure contains information
such as block size, density, command set, and electrical specifications. To return the addressed partition to
read array mode, write the read array command code
(FFh) on DQ0–DQ7.
Read Array
The array is read by entering the command code
FFh on DQ0–DQ7 to each partition to be read. Control
signals CE#, ADV#, and OE# must be at a logic LOW
level (VIL) and WE# and RST# must be at a logic HIGH
level (VIH) to read data from the array. Data is available
on DQ0–DQ15. Upon device reset, all partitions
default to the read array mode. To return the addressed
partition to read array mode, write the read array command code (FFh) on DQ0–DQ7.
Read Status Register
The status register provides the status of the device
to the external microprocessor. The status register is
read by entering the command code 70h on DQ0–DQ7.
The address for both cycles must be in the same partition. Status register data is updated and latched on the
falling edge of OE#, on the falling edge of CE#, or on
the clock edge which starts a burst (whichever occurs
last). See “Burst Read Mode” on page 16 for BURST
operation. Latching the data prevents errors from
occurring if the register input changes while monitoring the status register.
The status register outputs the data on DQ0–DQ7.
Table 7 contains the status register definitions.
To return the addressed partition to read array
mode, write the read array command code (FFh) on
DQ0–DQ7.
Read Device Identifier
The read device identifier mode outputs five types
of information: the manufacturer and device identifier,
the block locking status, the read configuration register, and the protection register data. Two bus cycles are
required for this operation: the device identifier data is
read by entering the command code 90h on DQ0–DQ7
and the identification code address on the address
lines. Control signals CE#, ADV#, and OE# must be at a
logic LOW level (VIL), and WE# and RST# must be at a
logic HIGH level (VIH) to read device identifier data.
Data is available on DQ0–DQ15. To return the
addressed partition to read array mode, write the read
array command code (FFh) on DQ0–DQ7. See Table 15
on page 36 for more details.
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Read Modes
The MT28F1284W18 supports two read configurations: asynchronous/page mode and burst mode. The
RCR15 bit (see Table 9) in the read configuration register sets the read configuration. At reset, asynchronous/
page mode is the default configuration for all READ
operations.
the partition boundary is reached, and then read from
partition 1. If the application keeps clocking beyond
partition 15 last location, then the internal counter
restarts from partition 0 first address (see Figure 5).
Figure 5: Partition Boundary Wrapping
(Bottom Boot Example)
Asynchronous/Page Read Mode
Asynchronous/page read mode is the default read
configuration state. To use the device in an asynchronous-only application, ADV# and CLK may be tied to
VSS, and WAIT# should be floated. Note that ADV# may
also be used in asynchronous mode to latch addresses
(latched asynchronous read mode).
A random access is initiated either on the falling
edge of CE#, on the falling edge of ADV#, or on a transition of the address lines (A0–A22), whichever occurs
last. Access times are given by tACE, tAADV, and tAA,
respectively.
A latched asynchronous read mode is also available
in which all address lines except A0–A3 are latched. In
this mode, the rising edge of ADV# will latch the
addresses. After the addresses are latched, this mode
becomes identical to the normal mode. The latched
mode is useful when noise is present on the address
lines, which might cause a READ operation from
unwanted locations.
Page mode is a performance-enhancing extension
to the legacy asynchronous READ operation. The initial portion of the page mode cycle is the same as the
asynchronous access cycle. Subsequent READs are
performed by holding CE# LOW and toggling A0–A3,
allowing random access of other words in the page.
These subsequent READs are done at the faster page
access time, tAPA.
00000h
Partition 0 end address
07FFFFh
Partition 1 start address
080000h
Partition 0
Partition boundary
Partition 1 end address
.
.
.
0FFFFFh
Partition 15 start address
780000h
Partition 15 end address
7FFFFFh
Partition 15
Clock Suspend
The clock suspend feature enables the device to suspend a burst sequence, to allow data to be retrieved
from another device sharing the same bus. The system
processor can resume the burst sequence where it left
off at a later time, with zero initial access latency penalty. Clock suspend is most beneficial in non-cached
systems.
Clock suspend can occur at any stage of a burst,
during initial access latency, or when outputting data.
When a burst access is suspended, internal array sensing continues, and any previously latched internal
data is retained. As long as the device operation conditions are met, a burst sequence can be suspended and
resumed without any limit.
Clock suspend is executed when CE# is asserted, the
current address has been latched (either ADV# rising
edge or CLK edge), CLK is halted, and OE# is deasserted. CLK can be halted when it is at VIH or VIL. To
resume, OE# is re-asserted and CLK is restarted. Subsequent CLK edges resume the burst sequence where
it left off.
Note that when using the clock suspend feature, the
device’s WAIT# signal remains active. Multiple devices
should not share the systems’s READY signal when
using the clock suspend feature. Refer to the WAIT#
signal configuration on RCR8.
Burst Read Mode
The burst read mode is used to achieve a faster data
rate than is possible with asynchronous read mode. A
burst access is started when an active clock edge
(defined by RCR6; refer to Table 9 for more information) occurs after ADV# goes LOW. The address is
latched when ADV# goes HIGH or on the active clock
edge, whichever occurs first. The burst read configuration is set in the read configuration register.
BURST READ operations can traverse partition
boundaries, but application code is responsible for
ensuring that the operations do not extend into partitions that are programming or erasing. All blocks in all
partitions are burstable. For example, if a burst starts
in partition 0, the application can keep clocking until
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MT28F1284W18_D.fm - Rev. D, 11/03 EN
Partition 0 start address
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Read Configuration Register (RCR)
The SET READ CONFIGURATION REGISTER command is a sequence used to load the read configuration register (RCR). It is a two-cycle command
sequence. Read configuration setup (60h) is written,
followed by a second WRITE (03h) that specifies the
value to be written to the read configuration register.
Table 9:
BIT #
The new RCR settings are placed on the address bus
(A0–A15), and are latched on the rising edge of CE# or
WE#, whichever occurs first. Refer to Table 9 for the
RCR bit settings. After setting the RCR, the device automatically returns to read array mode. Upon reset, the
RCR is set to FFCFh.
Read Configuration Register
DESCRIPTION
FUNCTION
15
Read Mode
0 = Synchronous Burst Access Mode
1 = Asynchronous/Page Access Mode (default)
14
Reserved
Default = 1
Latency Code
Sets the number of clock cycles before valid data out (see Figure 6):
000 = Code 0 - reserved
001 = Code 1 - reserved
010 = Code 2
011 = Code 3
100 = Code 4
101 = Code 5
110 = Code 6 - reserved
111 = Code 7 - reserved (default)
0 = WAIT# signal is active LOW
1 = WAIT# signal is active HIGH (default)
Sets the data output configuration:
0 = Hold data for one clock
1 = Hold data for two clocks (default)
Controls the behavior of the WAIT# output signal:
0 = WAIT# asserted during delay
1 = WAIT# asserted one data cycle before delay (default)
Specifies the order in which data is addressed in synchronous burst mode:
0 = Reserved
1 = Linear (default)
Defines the clock edge on which the BURST operation starts and data is
referenced:
0 = Falling edge
1 = Rising edge (default)
Default = 0
0 = Burst wraps within the burst length
1 = Burst no wrap (default)
Sets the number of words the device will output in burst mode:
001 = 4 words
010 = 8 words
011 = 16 words
111 = Continuous burst (default)
13–11
10
Wait Signal Polarity
9
Hold Data Out
8
Wait Configuration
7
Burst Sequence
6
Clock Configuration
5–4
3
Reserved
Burst Wrap
2–0
Burst Length
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WAIT# Signal Function
When performing a continuous burst, or when performing a four-, eight-, or 16-word burst with no wrap
selected (RCR3 = 1), the device may have an output
delay when the burst sequence crosses the first 16word boundary. The delay will occur only once during
any burst access. The starting address dictates the
amount of delay. If the starting address is at the end of
a 16-word boundary, the output delay will be the maximum delay. If the starting address is aligned with a 16word boundary, a delay will not be seen. Likewise, if a
burst never crosses a 16-word boundary, no delay will
be seen. For example, in a four-word burst, no-wrap
mode, possible linear burst sequences that do not
cause delays are:
0-1-2-3
1-2-3-4
2-3-4-5
3-4-5-6
4-5-6-7
5-6-7-8
6-7-8-9
7-8-9-10
The WAIT# output is high impedance until the
device is active (CE# = VIL). In asynchronous/page
mode, WAIT# is set to an asserted state (as defined by
RCR10). WAIT# is also set to an asserted state during
non-read-array BURST operations such as burst read
of status register, query, or device identifier.
During clock suspend, WAIT# remains active
because CE# gates the WAIT# signal. The WAIT# signal
does not revert to a high-impedance state when OE# is
de-asserted and therefore can cause contention with
another device attempting to control the system's
ready signal during a clock suspend. Multiple devices
should not be connected directly to the sysem's
READY ready signal if the clock suspend feature is
used.
8-9-10-11
9-10-11-12
10-11-12-13
11-12-13-14
12-13-14-15
Read Mode
The device supports two read configurations: burst
mode, and asynchronous/page mode. The RCR15 bit
(refer to Table 9) in the read configuration register sets
the read mode. Asynchronous/page mode is the
default read mode.
The WAIT# signal informs the system if an output
delay occurs. When the WAIT# signal is asserted, it
indicates invalid data. When the WAIT# signal is deasserted, it indicates valid data. See Figure 26 for more
details.
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Latency Counter
The latency counter (RCR13–RCR11) provides the
number of clocks that must elapse after the clock edge
that starts the burst before data is valid, as shown in
Figure 6. This value depends on the input clock frequency. See Table 10 for the clock frequency vs. first
access latency information.
18
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Figure 6: Latency Counter
VIH
CLK
VIL
VIH
A0-A21
VIL
VALID
ADDRESS
VIH
ADV#
VIL
VOH
Code 2
VALID
OUTPUT
DQ0-DQ15
VO L
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
Code 3
VOH
DQ0-DQ15
VO L
VALID
OUTPUT
Code 4
VOH
VALID
OUTPUT
DQ0-DQ15
VO L
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
Code 5
VOH
DQ0-DQ15
VO L
UNDEFINED
NOTE:
CLK shown as rising edge configuration (RCR6 = 1).
Table 10: Clock Frequency vs. First Access Latency
LATENCY COUNTER CODE
Frequency (MHz)
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19
2
3
4/5
£40
£54
£66
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WAIT# Signal Polarity
RCR10 sets the WAIT# signal polarity. When
RCR10 = 0, WAIT# is active LOW. When RCR10 = 1, the
WAIT# signal is active HIGH. See “WAIT# Signal Function” on page 18 for more information.
Hold Data Out
The hold data out (RCR9) specifies for how many
clocks data will be held valid. (See Figure 7.)
Figure 7: Hold Data Output Configuration
CLK
WAIT# (RCR8 = 1)
Note 1
tACLK
WAIT# (RCR8 = 0)
Note 1
Hold
Data
1 CLK
VALID
OUTPUT
DQ0–DQ15
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
WAIT# (RCR8 = 0)
tKHTL
Note 1
tACLK
WAIT# (RCR8 = 1)
Hold
Data
2 CLK
Note 1
VALID
OUTPUT
DQ0–DQ15
VALID
OUTPUT
NOTE:
1. WAIT# shown active HIGH (RCR10 = 1).
WAIT# Configuration
The wait configuration bit (RCR8) controls the
WAIT# signal behavior for all burst read modes. It
should be set according to the system and CPU characteristics. The WAIT# signal can be configured to assert
either during valid data, or one data cycle before data
becomes valid (see Figure 6). See “WAIT# Signal Function” on page 18 for more information.
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Burst Sequence
The burst sequence (RCR7) specifies the ordering of
data in burst mode. Linear burst order (RCR7 = 1) is the
only burst sequence supported by the device. See
Table 11 for more details.
Clock Configuration
The clock configuration (RCR6) defines the clock
edge on which the burst operation starts and data is
defined.
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Burst Wrap
The burst wrap option (RCR3) determines whether
the burst access wraps within the burst length or
crosses the burst length boundary. In wrap mode
(RCR3 = 0) the four-, eight-, or 16-word access will
wrap within the four, eight, or 16 words, respectively.
In no-wrap mode (RCR3 = 1), the device operates similarly to a continuous burst. See Table 11 for more
details.
Burst Length
The burst length (RCR2–RCR0) defines the number
of words the device outputs. The device supports burst
lengths of four words, eight words, 16 words, or continuous burst. When the continuous burst option is
selected, the internal address wraps to 000000h after
reaching the maximum address.
Table 11: Sequence and Burst Length
4-WORD
BURST
LENGTH
STARTING
ADDRESS
(DEC)
WRAP
NO
WRAP
RCR3
RCR3
LINEAR
LINEAR
LINEAR
LINEAR
0
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
0-1-2-3-4-5-6-…
1
0
1-2-3-0
1-2-3-4-5-6-7-0
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0
1-2-3-4-5-6-7-…
2
0
2-3-0-1
2-3-4-5-6-7-0-1
2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1
2-3-4-5-6-7-8-…
3
0
3-0-1-2
3-4-5-6-7-0-1-2
3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
3-4-5-6-7-8-9-…
4
0
4-5-6-7-0-1-2-3
4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3
4-5-6-7-8-9-10-…
5
0
5-6-7-0-1-2-3-4
5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4
5-6-7-8-9-10-11-…
6
0
6-7-0-1-2-3-4-5
6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5
6-7-8-9-10-11-12-…
7
0
7-0-1-2-3-4-5-6
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
7-8-9-10-11-12-13-…
8
0
...
...
...
8-9-10-11-12-13-14-15-0-1-2-3-4-5-6-7
...
9
0
...
...
...
9-10-11-12-13-14-15-0-1-2-3-4-5-6-7-8
...
10
0
...
...
...
10-11-12-13-14-15-0-1-2-3-4-5-6-7-8-9
...
11
0
...
...
...
11-12-13-14-15-0-1-2-3-4-5-6-7-8-9-10
...
12
0
...
...
...
12-13-14-15-0-1-2-3-4-5-6-7-8-9-10-11
...
13
0
...
...
...
13-14-15-0-1-2-3-4-5-6-7-8-9-10-11-12
...
14
0
14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13
14-15-16-17-18-19-20-..
15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
15-16-17-18-19-20-21-..
15
0
...
...
8-WORD
BURST LENGTH
16-WORD
BURST LENGTH
CONTINUOUS
BURST
...
...
...
...
...
0
1
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
0-1-2-3-4-5-6-…
1
1
1-2-3-4
1-2-3-4-5-6-7-8
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16
1-2-3-4-5-6-7-…
2
1
2-3-4-5
2-3-4-5-6-7-8-9
2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17
2-3-4-5-6-7-8-…
3
1
3-4-5-6
4
1
5
1
5-6-7-8-9-10-11-12
5-6-7-8-9-10-11-12-13-14-15-16-17-18-19-20
5-6-7-8-9-10-11…
6
1
6-7-8-9-10-11-12-13
6-7-8-9-10-11-12-13-14-15-16-17-18-19-20-21
6-7-8-9-10-11-12…
7
3-4-5-6-7-8-9-10
3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10-11
4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19
4-5-6-7-8-9-10-…
1
…
7-8-9-10-11-12-13-14
7-8-9-10-11-12-13-14-15-16-17-18-19-20-21-22
7-8-9-10-11-12-13…
8
...
1
...
...
8-9-10-11-12-13-14-15-16-17-18-19-20-21-22-23
...
9
...
1
...
...
9-10-11-12-13-14-15-16-17-18-19-20-21-22-23-24
...
10
...
1
...
...
10-11-12-13-14-15-16-17-18-19-20-21-22-23-24-25
...
11
...
1
...
...
11-12-13-14-15-16-17-18-19-20-21-22-23-24-25-26
...
12
...
1
...
...
12-13-14-15-16-17-18-19-20-21-22-23-24-25-26-27
...
13
...
1
...
...
13-14-15-16-17-18-19-20-21-22-23-24-25-26-27-28
...
14
1
...
14-15-16-17-18-19-20-21-22-23-24-25-26-27-28-29
14-15-16-17-18-19-20-…
15
1
15-16-17-18-19-20-21-22-23-24-25-26-27-28-29-30
15-16-17-18-19-20-21-…
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
21
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©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Programming Operations
In addition to the traditional single word programming commands (10h and 40h), another sequence is
offered to speed up the in-factory programming operations (30h). The in-factory programming operation is
compatible with the use of an external power supply
connected to the VPP ball. For in-system operations,
the VPP ball can be connected either to a general purpose I/O ball of the host system, or the VCC ball.
READ DEVICE IDENTIFIER, READ QUERY, and READ
STATUS REGISTER command until the PROGRAM
operation has been completed, after which time, all
commands to the CSM become valid again.
Taking RST# to VIL during programming aborts the
PROGRAM operation, leaving undetermined data in
the location being programmed. When programming
is aborted, a delay time of tPRD must elapse after RST#
goes LOW before the internal RESET operation is complete. An additional delay of tRWH must elapse after
RESET is complete (or after RST# goes HIGH, whichever occurs last) before data can be read from the
device. Refer to Figure 18 and Table 17 for more information. During programming, VPP must remain above
VPPLK, and VCC must remain in the voltage range provided in the recommended operating conditions.
Conventional Word Programming
After the setup command code is entered (10h/40h)
on DQ0–DQ7, followed by the data to be programmed,
the WSM takes over and correctly sequences the
device to complete the PROGRAM operation. The
PROGRAM operation may be monitored through the
status register. During this time, the CSM will only
respond to a PROGRAM SUSPEND, READ ARRAY,
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
22
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 8: Conventional Word
Programming Flowchart
BUS
OPERATION COMMAND
WRITE
Start
WRITE
Write 40h,
Word Address
WRITE
PROGRAM
SETUP
WRITE
DATA
Write Word Data,
Word Address
READ
Read Status
Register Bits
PROGRAM
SUSPEND Loop
NO
NO
PROGRAM
SUSPEND?
SR7 = 1?
COMMENTS
Data = 40h
Addr = Address of word to
be programmed
Data = Word to be
programmed
Addr = Address of word to
be programmed
Status register data
Toggle OE# or CE# to
update status register.
Check SR7
1 = Ready, 0 = Busy
YES
YES
Full Status Register
Check (optional)1
Word Program
Completed
FULL STATUS REGISTER CHECK FLOW
Read Status
Register Bits
NO
SR3 = 0?
BUS
OPERATION COMMAND
VPP Range Error
READ
YES
NO
SR4 = 0?
NO
Check SR32
1 = VPP range error
Check SR42
1 = Data program error
Check SR1
1 = Attempted PROGRAM to
locked block. PROGRAM
aborted.
Program Error
YES
SR1 = 0?
COMMENTS
Lock Block Error
YES
Word Program Passed
NOTE:
1. Full status register check can be done after each word or after a sequence of words.
2. SR1, SR3, and SR4 are cleared only by the CLEAR STATUS REGISTER command, but do not prevent additional PROGRAM operation attempts.
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
23
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©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Fast Programming Algorithm (FPA)
Mode
address can be held constant, or it can be incremented
within the address range. The program cycle ends
when the programmer writes FFFFh outside the
address range of the current block.
When the FPA is activated, the data must be provided in sequential order to the WSM. Immediately
after programming, verification is executed. The data
sequence and starting address are provided to the
WSM, which automatically performs a data verification. The result is stored in the status register. Writing
FFFFh outside the memory block boundary exits the
verification cycle. Figure 9 shows the FPA flowchart.
Note that issuing a 70h command to the device after
FPA setup (30h) will be interpreted as data and will be
written to the device.
The fast programming algorithm (FPA) is intended
for in-factory use. It enables fast data stream programming. For in-factory programming, FPA minimizes
chip programming time when 11.4V < VPP < 12.6V. FPA
algorithm can also provide accelerated program with
VPP = 1.8V. Executing the FPA command (30h) followed
by FPA CONFIRM (D0h), enables an entire block to be
programmed. This eliminates the need to continuously update the address to be programmed.
An initial delay is required after issuing the FPA
command. (See Table 25.) If the block is locked, the
status register returns an error. When the FPA command is executed successfully, a data stream can be
programmed beginning at the first address. The
Figure 9: Fast Programming Algorithm (FPA) Flowchart (in-factory only)
FPA Setup
FPA Program
FPA Verify
FPA Exit
Start
Read
Status Register1
Read
Status Register1
Read
Status Register1
Unlock Block
SR0 = 1
Data
Stream Ready?
WRITE 30h
Address = WA4
SR0 = 1
Verify
Stream Ready?
SR0 = 0
WRITE D0h
Address = WA4
SR7 = 0
SR0 = 0
FPA
Exited?
SR7 = 1
WRITE Data
Address = WA4
WRITE Data
Address = WA4
Full Status
Check Procedure
Read
Status Register
Read
Status Register2
Operation
Complete
FPA Setup Time
SR0 = 1
SR0 = 1
Program
Done?
Read
Status Register1
Verify
Done?
SR0 = 0
SR0 = 0
FPA Setup
Done?
SR7 = 1
Check VPP and
Lock Errors
(SR3, SR1)
No
No
Last Data?
Last Data?
SR7 = 0
Yes
Yes
WRITE FFFFh
Address ≠ BA3
WRITE FFFFh
Address ≠ BA3
Exit
NOTE:
1. When reading the status register, the address must be within the block being programmed.
2. During FPA verify, if a word fails to verify, status changes to 90h.
3. BA = Address within block.
4. WA = First word Address to be written in the block.
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
ERASE Operations
An ERASE operation must be used to initialize bits
in an array block to “1s.” The commands to initiate
BLOCK ERASE are as follows: BLOCK ERASE SETUP
(20h) followed by BLOCK ERASE CONFIRM (D0h) (see
Figure 10).
A two-command erase sequence protects against
accidental erasure of memory contents.
When the BLOCK ERASE CONFIRM command is
complete, the WSM automatically executes a sequence
of events to complete the BLOCK ERASE. During this
sequence, the block is programmed with logic 0s, the
0s are then verified, all bits in the block are erased to
logic 1 state, and finally verification is performed to
ensure that all bits are correctly erased. During an
ERASE, VPP must remain above VPPLK, and VCC must
remain in the voltage range provided in the recom-
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
mended operating conditions. Monitoring of the
ERASE operation is possible through the status register. SR7 = 1 indicates the ERASE operation is complete.
SR5 = 1 indicates an ERASE failure; SR3 = 1 indicates
an invalid VPP supply voltage; and SR1 = 1 indicates an
ERASE operation was attempted on a locked block.
Taking RST# to VIL during an ERASE aborts the
ERASE operation leaving undetermined data in the
block being erased. When an ERASE is aborted, a delay
time of tERD must elapse after RST# goes LOW, before
the internal RESET operation is complete. An additional delay of tRWH must elapse after the RESET is
complete (or after RST# goes HIGH, whichever occurs
last) before data can be read from the device. Refer to
Figure 18 on page 38 and Table 17 on page 38 for more
information.
25
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©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 10: Block Erase Flowchart
BUS
OPERATION COMMAND
Start
WRITE
Issue ERASE SETUP
Command and
Block Address
WRITE
Issue BLOCK ERASE
CONFIRM Command
and Block Address
WRITE
ERASE
SETUP
ERASE
READ
Read Status
Register Bits
ERASE
SUSPEND Loop
COMMENTS
Data = 20h
Block Addr = Address
within block to be erased
Data = D0h
Block Addr = Address within
block to be erased
Status register data
Toggle OE# or CE# to
update status register
Check SR7
1 = Ready, 0 = Busy
NO
NO
ERASE
SUSPEND?
SR7 = 1?
YES
YES
BUS
OPERATION COMMAND
Full Status Register
Check (optional)1
READ
BLOCK ERASE
Completed
COMMENTS
Check SR32
1 = VPP error
Check SR4 and SR52
Both = 1 = Command
sequence error
FULL STATUS REGISTER CHECK FLOW
Read Status
Register Bits
Check SR52
1 = BLOCK ERASE error
NO
SR3 = 0?
Check SR12
1 = Attempted ERASE of
locked block. ERASE
aborted.
If an error is detected, clear the status register before
attempting an erase retry or other error recovery.
VPP Range Error
YES
YES
SR[4:5] = 1?
Command Sequence Error
NO
NO
SR5 = 0?
Block Erase Error
YES
NO
SR1 = 0?
Lock Block Error
YES
BLOCK ERASE Passed
NOTE:
1. Full status register check can be done after each block or after a sequence of blocks.
2. SR1, SR3, SR4, and SR5 are cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are
erased before full status is checked. (These bits do not prevent additional ERASE operation.)
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
26
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©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
PROGRAM SUSPEND, PROGRAM
RESUME, ERASE SUSPEND, ERASE
RESUME Commands
than the one being programmed. To resume the
ERASE/PROGRAM operation, a RESUME command
(D0h) must be issued to cause the CSM to clear the
suspend state previously set (see Figures 11 and 12).
It is also possible that an ERASE in any block can be
suspended and a PROGRAM to another block within
any partition can be initiated. At this point, a PROGRAM SUSPEND may be issued to allow a READ of yet
another location. After the completion of a READ operation, PROGRAM can be resumed by issuing a PROGRAM RESUME command. Finally, after the device
has reached the ready state, SR7 = 1, an ERASE
RESUME will allow the WSM to finish the original
ERASE operation.
A minimum time should elapse between an ERASE
RESUME command and a subsequent ERASE SUSPEND command to ensure that the device achieves
sufficient cumulative erase time.
During the execution of an ERASE/PROGRAM operation, the SUSPEND command (B0h) can be issued to
direct the WSM to suspend the ERASE/PROGRAM
operation. Once the WSM has reached the suspend
state, it allows the CSM to respond only to the READ
ARRAY, READ STATUS REGISTER, READ QUERY,
READ DEVICE IDENTIFIER, and PROGRAM RESUME.
Additionally, PROGRAM, PROGRAM SUSPEND, ERASE
RESUME, LOCK BLOCK, UNLOCK BLOCK, and LOCK
DOWN BLOCK are valid commands during an ERASE
SUSPEND. (See “Block Locking” on page 30).
Once in erase suspend mode, array data must be
read/programmed into a block other than the one
being erased. During the PROGRAM SUSPEND operation, array data should be read from an address other
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
27
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 11: Program Suspend/Program
Resume Flowchart
BUS
OPERATION COMMAND
WRITE
Start
WRITE
Issue PROGRAM
SUSPEND Command
PROGRAM
SUSPEND
READ
STATUS
READ
Issue READ STATUS
Command
Same Partition
WRITE
Read Status
Register Bits
READ
MEMORY
READ
WRITE
NO
SR7 = 1?
PROGRAM/
RESUME
COMMENTS
Data = B0h
Data = 70h
Status register data
Toggle OE# or CE# to
update status register
Check SR7
1 = Ready
Check SR2
1 = Suspended
Data = FFh
Read data from block other
than that being
programmed
Data = D0h
NOTE:
YES
If the suspended partition was placed in read array
mode, then the following condition applies:
NO
SR2 = 1?
BUS
OPERATION COMMAND
YES
WRITE
Full Status Register
Check (optional)
Program Complete
READ
STATUS
COMMENTS
Return partition to status
mode:
Data = 70h
Addr = address within same
partition
Issue READ ARRAY
Command
Finish
Reading?
NO
YES
Issue PROGRAM
RESUME Command
Write FFh
Program Partition
Program Resumed
Read Array Data
Issue READ STATUS
Command
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 12: Erase Suspend/Erase Resume
Flowchart
BUS
OPERATION COMMAND COMMENTS
WRITE
Start
WRITE
ERASE
SUSPEND
READ
STATUS
Issue ERASE
SUSPEND Command
Issue READ STATUS
Command
Same Partition
WRITE
Read Status
Register Bits
READ
ARRAY
READ or
WRITE
NO
SR7 = 1?
WRITE
ERASE
RESUME
Data = B0h
Data = 70h
Addr = Any address in same
partition
Check SR7
1 = Ready, 0 = Busy
Check SR6
1 = Suspended
0 = Completed
Data = FFh
Addr = Any device address
(except block being erased)
Read data from, or write
data to, a block other than
that being erased
Data = D0h
Addr = Any address
YES
NOTE:
NO
SR6 = 1?
If the suspended partition was placed in read array
mode or a program loop, then the following condition
applies:
ERASE Complete
YES
READ or
PROGRAM?
PROGRAM
BUS
OPERATION COMMAND COMMENTS
WRITE
READ
Issue READ ARRAY
Command
PROGRAM Loop
(Note 1)
NO
READ
STATUS
Return partition to status
mode
Data = 70h
Addr = Address within same
partition
READ
or PROGRAM
Complete?
YES
Issue ERASE
RESUME Command
ERASE Continued2
Issue READ STATUS
Command
Same Partition
NOTE:
1. See Word Programming flowchart for complete programming procedure.
2. See BLOCK ERASE flowchart for complete erase procedure.
09005aef80b425b4
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29
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
READ-While-PROGRAM/ERASE Concurrency
read status mode and an array READ operation can be
performed on any other partition. Partition x will
remain in read status mode.
The CFI and the device identifier areas are considered an additional partition separate from the array
partitions and support concurrent operations.(See
Table 12 for simultaneous operations allowed between
the protection register and the main partitions.)
It is possible for the device to read from one partition while erasing/programming to another partition.
For example, during a READ CONCURRENCY operation, if a PROGRAM or ERASE operation is being performed in partition x, then partition x changes to the
Table 12: Simultaneous Operations Allowed in the Protection Register
PROTECTION
REGISTER
MAIN PARTITION
DESCRIPTION
READ
PROGRAM/ERASE
PROGRAM
READ
During the programming or erasing of a main partition, the protection
register may be read from any other partition.
During the programming of the protection register, READs are only allowed
in the main partitions. A delay of 200ns must be inserted after issuing the
PROTECTION PROGRAM command (C0h) before performing concurrent read
of the main partitions.
Block Locking
The Flash device provides a flexible locking scheme
that allows each block to be individually locked or
unlocked with no latency.
The device offers two-level protection for the
blocks. The first level allows software-only control of
block locking (for data that needs to be changed frequently), while the second level requires hardware
interaction before locking can be changed (code that
does not require frequent updates).
Control signals WP#, DQ1, and DQ0 define the state
of a block; for example, state [001] means WP# = 0,
DQ1 = 0, and DQ0 = 1. See “Reading a Block’s Lock Status” on page 33.
Table 13 defines all of the possible locking states,
Figure 13 shows the block locking state diagram, and
Figure 14 describes the locking operations.
Table 13: Block Locking State Transition
WP#
DQ1
DQ0
NAME
0
0
0
0
0
1
0
1
1
1
1
0
0
1
1
0
1
0
1
1
1
Unlocked
Locked
(Default)
Lock Down
Unlocked
Locked
Lock Down
Disabled
Lock Down
Disabled
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
ERASE/PROG
ALLOWED
LOCK
UNLOCK
LOCK
DOWN
Yes
No
To [001]
No Change
No Change
To [000]
To [011]
To [011]
No
Yes
No
Yes
No Change
To [101]
No Change
To [111]
No Change
No Change
To [100]
No Change
No Change
To [111]
To [111]
To [111]
No
No Change
To [110]
No Change
30
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 13: Block Locking State Diagram
LOCKED
UNLOCKED
60h/D0h
60h/01h
[000]
[001]
60h
/2F
Power-Up/Reset
Default
h
60h/2Fh
WP# = VIL = 0
60h/D0h
[011]
Locked-Down
[111]
Locked-Down is disabled by
WP# = VIH
60h/01h
[110]
60h/2Fh
WP# = VIH = 1
60h/2Fh
60h/D0h
Power-Up/Reset
Default
60h/01h
[100]
[101]
60h/D0h = UNLOCK command
60h/01h = LOCK command
60h/2Fh = LOCK DOWN command
= WP# hardware control (bidirectional)
= WP# hardware control (unidirectional)
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
31
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 14: Locking Operations
Flowchart
Locked State
After a reset sequence, all blocks are locked (states
[001] or [101]). This means full protection from alteration. Any PROGRAM or ERASE operations attempted
on a locked block will return an error on bit SR1 of the
status register. The status of a locked block can be
changed to unlocked or lock down using the appropriate software commands. Writing the LOCK SETUP
command sequence (60h) followed by UNLOCK
BLOCK (D0h) can unlock a locked block.
Start
Write 60h,
Block Address
Optional
Write 01h/D0h/2Fh,
Block Data
Unlocked State
Unlocked blocks (states [000], [100], [110]) can be
programmed or erased. All unlocked blocks return to
the locked state when the device is reset or powered
down. An unlocked block can be locked or locked
down by writing the LOCK SETUP command (60h) followed by LOCK BLOCK (01h), or LOCK DOWN BLOCK
(2Fh).
Write 90h,
BA
Read Block Lock
Status
Locked Down State
Lock Change
Complete
BUS
OPERATION COMMAND
The lock down function is dependent on the WP#
input. When WP# = 0, blocks in lock down [011] are
protected from PROGRAM, ERASE, and lock status
changes. When WP# reverts to WP# = 1, the lock down
function is disabled [111], and locked down blocks can
be individually unlocked by a software command to
the [110] state, where they can be erased and programmed. These blocks can then be relocked [111] and
unlocked [110] as desired while WP# remains HIGH.
When WP# goes LOW, blocks that were previously
locked down return to the locked down state [011]
regardless of any changes made while WP# was HIGH.
A locked or unlocked block can be locked down by
writing the LOCK SETUP command (60h) followed by
LOCK DOWN (2Fh). Resetting the device resets all
blocks, including those in lock down, to the locked
state (see Table 13).
COMMENTS
WRITE
LOCK SETUP
Data = 60h
Addr = BLOCK to LOCK/UNLOCK/
LOCK DOWN (BA)
WRITE
LOCK,
Data = 01h (LOCK BLOCK)
UNLOCK, or
D0h (UNLOCK BLOCK)
LOCK DOWN
2Fh (LOCK DOWN BLOCK)
CONFIRM
Addr = BLOCK to LOCK/UNLOCK/
LOCK DOWN (BA)
WRITE
(Optional)
READ ID
Data = 90h
Addr = BA
READ
(Optional)
BLOCK LOCK
STATUS
Data = Block Lock Status Data
Addr = BBA + 02h
Confirm locking change on DQ[1:0].
See Table 13 for valid
combinations.
09005aef80b425b4
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32
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Reading a Block’s Lock Status
To change a block’s lock status during an ERASE
operation, first write the ERASE SUSPEND command
(B0h), then check the status register until it indicates
that the ERASE operation has been suspended. Next,
write the desired LOCKING command sequence to the
desired block, and the block’s lock status will be
changed. After completing any desired LOCK, READ,
or PROGRAM operations, resume the ERASE operation
with the ERASE RESUME command (D0h).
If an erase suspended block has its lock status
changed, the lock status bits will change immediately.
When the ERASE is resumed, the ERASE operation will
complete.
A locking operation cannot be performed during a
PROGRAM SUSPEND.
Using nested locking or program command
sequences during erase suspend can introduce ambiguity into status register results. Following protection
configuration setup (60h), an invalid command will
produce a command sequence error (SR4 and SR5 will
be set to “1”) in the status register. If a command
sequence error occurs during an erase suspend, SR4
and SR5 will be set to “1” and will remain at “1” after
the erase suspend is resumed. When the ERASE is
complete, any possible error during the ERASE cannot
be detected via the status register because of the previous command sequence error. This is also true if an
error occurs during a program operation error nested
within an erase suspend.
The lock status of every block can be read in the
read device identifier mode. To enter this mode, write
90h to the device. Subsequent READs at the base block
address +00002 will output the lock status of that
block. The lowest two outputs, DQ0 and DQ1, represent the lock status. DQ0 indicates the block lock/
unlock status and is set by the LOCK command and
cleared by the UNLOCK command. It is also automatically set when entering lock down. DQ1 indicates lock
down status and is set by the LOCK DOWN command.
It can only be cleared by reset or power-down, not by
software. Table 13 on page 30 shows the locking state
transition scheme and Table 14 shows the write protection truth table.
Table 14: Write Protection Truth Table
VPP WP# RST# WRITE PROTECTION
X
VIL
X
X
VIL
VIH
X
X
VIL
VIH
VIH
VIH
Device inaccessible
Word program and block erase
prohibited
All lock down blocks locked
All lock down blocks can be unlocked
Locking Operations During Erase Suspend
Changes to a block’s lock status can be performed
during an erase suspend by using the standard locking
command sequences to unlock, lock, or lock down.
This is useful in the case when another block needs to
be updated while an ERASE operation is in progress.
09005aef80b425b4
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33
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Protection Register
Figure 15: Protection Register Memory
Map
The 128-bit security area is divided into two 64-bit
segments. The first 64 bits of the protection register
(addresses 81h–84h) are programmed at the factory
with a unique 64-bit unchangeable number. DQ0 of
the PR lock register (address 80h) is programmed to a
“0” state, locking the first 64 bits and preventing any
further programming.
The second 64 bits (addresses 85h–88h) are left
erased for the user to program as desired (see
Figure 15). The user can program any information into
this area as long as DQ1 of the PR lock register (address
80h) remains unprogrammed. After DQ1 of the PR lock
register is programmed, no further programming is
allowed in the user area.
ERASE operations are not allowed on the protection
register.
READ-While-PROGRAM operation is only allowed
between the chip protection register and main partitions. Table 12 describes the simultaneous operations
allowed in the chip protection register.
88h
85h
4 Words
User-Programmed
84h
4 Words
Factory-Programmed
81h
80h
PR Lock
DQ1 DQ0
Reading the Protection Register
The protection register is read in the device identifier mode. To enter this mode, load the 90h command.
Once in this mode, READ cycles from addresses shown
in Table 15 on page 36 retrieve the specified information. To return to the read array mode, write the READ
ARRAY command (FFh).
Programming the Protection Register
The user area of the protection register (addresses
85h–88h) may be programmed by writing the PROTECTION PROGRAM command (C0h), followed by the
data to be programmed at one of the addresses within
the user area. This procedure may be repeated for each
of the addresses in the user area, as long as DQ1 of the
PR lock register remains unprogrammed. Issuing a
PROTECTION PROGRAM command outside the register’s address space results in a status register error (SR4
= 1). See Figure 16 on page 35 for more information.
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
34
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 16: Protection Register
Programming Procedure
BUS
OPERATION COMMAND
WRITE
Start
PROTECTION
PROGRAM
SETUP
COMMENTS
Data = C0h
Addr = Protection address
WRITE
Data = Data to program
Addr = Protection address
READ
Read SRD
Toggle CE# or OE# to
update SRD
Check SR7
1 = WSM Ready
0 = WSM Busy
Protection program operations addresses must be within
the protection register address space. Addresses outside
this space will return an error.
Repeat for subsequent programming operations.
Full status register check can be done after each
PROGRAM or after a sequence of PROGRAM operations.
Write C0h,
Addr = Prot Addr
Write Protection
RegisterAddress/Data
Read Status Register
NO
SR7 = 1?
BUS
OPERATION COMMENTS
YES
Full Status Check
(if desired)
READ
SR1 SR3 SR4
0
1
1 VPP error
0
0
1 Protection register
program error
1
0
1 Register locked; operation
aborted
Only the CLEAR STATUS REGISTER command clears SR1,
SR3, and SR4.
If an error is detected, clear the status register before
attempting a program retry or other error recovery.
Program Complete
Read SRD
YES
SR3, SR4 = 1?
VPP Range Error
NO
YES
SR3 = 0, SR4 = 1?
Programming Error
NO
YES
SR1 = 1, SR4 = 1?
Locked-Register
Program Aborted
NO
Program Successful
09005aef80b425b4
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35
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©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Locking the Protection Register
After DQ1 of the PR lock register is programmed, the
user’s protection register cannot be changed. The PR
lock register will read FFFCh. PROTECTION PROGRAM commands written to a locked section result in
a status register error (SR1 = 1, SR4 = 1).
DQ0 of the PR lock register is programmed to “0” by
the factory to protect the unique device number. DQ1
of the PR lock register can be programmed by the user
to lock the user portion (upper 64 bits) of the chip protection register (refer to Figure 15). This bit is set using
the PROTECTION PROGRAM command, C0h, to program FFFDh into the PR lock register (address 80h).
Table 15: Device Identifier Codes
ADDRESS1
ITEM
BASE
OFFSET
DATA
DESCRIPTION
Manufacturer’s Identification
Code
Block
00h
002Ch
Micron ManID
Device ID code
Block
01h
44C8h
44C9h
128Mb top boot device
128Mb bottom boot device
Block lock status
Block
02h
Block lock down status
Block
02h
DQ0 = 0
Block is unlocked
DQ0 = 1
Block is locked
DQ1 = 0
Block is not locked down
DQ1 = 1
Block is locked down
Read configuration register
Block
05h
Protection register lock status
Block
80h
Register data
Lock data
Protection register
Block
81h–84h
Factory data
85h–88h
User data
NOTE:
1. Address = base + offset.
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
36
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
VPP/VCC Program and Erase Voltages
If VCCQ and/or VPP are not connected to the system
supply, then VCC should attain VCC (MIN) before
applying VCCQ and VPP. Device inputs should not be
driven before supply voltage = VCC (MIN). Power supply transitions should only occur when RST# is LOW.
When VPP is applied within the in-factory programming range (VPP2), the sequence shown in Figure 17
must be followed. Applying VPP within the in-system
programming range (VPP1) does not require this
sequence.
The Flash device provides in-system programming
and erase with VPP in the 0.9V–1.95V range (VPP). The
12V VPP mode programming is offered for compatibility with existing programming equipment.
The device can withstand 100,000 PROGRAM/
ERASE operations with VPP = VPP1, or 1,000 PROGRAM/ERASE operations with VPP = VPP2.
In addition to the flexible block locking, the VPP programming voltage can be held LOW for absolute hardware write protection of all blocks in the Flash device.
When VPP is below VPPLK, any PROGRAM or ERASE
operation will result in an error, prompting the corresponding status register bit (SR3) to be set.
During PROGRAM and ERASE operations, the WSM
monitors the VPP voltage level. PROGRAM/ERASE
operations are allowed only when VPP is within the
ranges specified in Table 16.
When VCC is below VLKO, any PROGRAM/ERASE
operation will be disabled.
Figure 17: VCC and VPP at Power Up
VCC
VPP
MIN
MAX
VPP1
VPP2
0.9
11.4
1.95
12.6
VPP2
0V
T1 > 50µs
T2 > 1µs
Standby Mode
ICC supply current is reduced by applying a logic
HIGH level on CE# to enter the standby mode. In the
standby mode, the outputs are at a high impedance
state independent of OE#. Applying a logic HIGH level
on CE# reduces the current to ICCs. If the device is
deselected during an ERASE operation or during programming, the device continues to draw current until
the operation is complete.
Table 16: VPP Range (V)
SYMBOL
0V
Device Reset
To reset the device, the RST# signal must be asserted
(RST# = VIL) for a minimum of tRP. After reset, the
device defaults to read array mode, the status register
is set to 80h, and the read configuration register
defaults to asynchronous/page read mode. A delayed
access time of tRWH from the rising edge of RST# must
elapse before data can be read from the device. The
circuitry used to generate the RST# signal needs to be
common with the system reset. Refer to the timing diagram for further details.
If RST# is asserted during a PROGRAM or ERASE
operation, the operation will be aborted and the memory contents at the aborted block or address are
invalid.
Automatic Power Save (APS) Mode
Substantial power savings are realized during periods when the array is not being read and the device is
in active mode. During this time, the device switches
to the automatic power save (APS) mode. When the
device switches to APS mode, ICC is reduced to a level
comparable to ICCS. Further power savings can be realized by applying a logic HIGH level on CE# to place the
device in standby mode. The low level of power is
maintained until another operation is initiated. In this
mode, the I/Os retain the data from the last memory
address read until a new address is read. This mode is
entered automatically if no address or control signals
toggle.
Power-Up Sequence
The device is protected against accidental block erasure or programming during power transitions. If VCC,
VCCQ, and VPP are connected together, it does not matter whether VPP or VCC powers up first.
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
37
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©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 18: Reset Operations
tRP
A) Reset during
read mode
RST#
tRWH
VIH
VIL
tPRD
B) Reset during
program or block erase
tPRD ≥ tRP
tERD ≥ tRP
RST#
VIH
tERD
VIL
tPRD
C) Reset during
program or block erase
tPRD ≤ tRP
tERD ≤ tRP
tRWH
Abort
Complete
RST#
VIH
tRWH
Abort
tERD Complete
VIL
DQ0–DQ15
VOH
VALID
OUTPUT
VO L
tVCCRS
VCC
VCC
0V
Table 17: Reset Parameter Definitions
PARAMETER
SYMBOL
t
RST# pulse width
RP
MIN
MAX
100
UNIT
ns
RST# HIGH to output delay
t
150
ns
RST# LOW during PROGRAM to RESET operation complete
t
10
µs
RST# LOW during BLOCK ERASE to RESET operation complete
t
20
µs
RWH
PRD
VCC setup to RST# going HIGH
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
ERD
t
VCCRS
38
60
µs
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Electrical Specificatons
Table 18: Absolute Maximum Ratings
Note 1
VOLTAGE
MIN
MAX
UNITS
Voltage to any ball except VCC, VCCQ, and VPP
VPP Voltage
VCC Supply Voltage
VCCQ Supply Voltage
Output Short Circuit Current
Operating Temperature Range
Storage Temperature Range
Soldering Cycle
-0.5
-0.2
-0.2
-0.2
+2.45
+14
+2.45
+2.45
100
+85°
+125°
+260
V
V
V
V
mA
°C
°C
°C
-40
-65°
NOTES
2
3
NOTE:
1. Stresses greater than those listed in Table 18 may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. Maximum DC voltage on VPP may overshoot to +14V for periods < 20ns.
3. See technical note TN-00-15, “Recommended Soldering Techniques,” for more information.
Table 19: Recommended Operating Conditions
PARAMETER
Operating Temperature
VCC Supply Voltage
I/O Supply Voltage
Input/Output Capacitance: DQs
VPP Voltage
VPP In-factory Programming Voltage
Block Erase Cycling (VPP = VPP1)
Block Erase Cycling (VPP = VPP2)
Time for VPP at VPP2
SYMBOL
T
A
VCC
VCCQ
CIO
VPP1
VPP2
MIN
TYP
MAX
-40
–
+85
1.70
1.70
–
0.9
11.4
–
–
–
–
4.0
–
–
–
–
1.95
2.24
6.5
1.95
12.6
100,000
1,000
100
t
PPH
UNITS
o
C
V
V
pF
V
V
Cycles
Cycles
Hours
Table 20: Capacitance
TA = +25°C; f = 1 MHz
PARAMETER/CONDITION
SYMBOL
TYP
MAX
UNITS
CIN
COUT
CCLK
5
8
10
8
10
12
pF
pF
pF
Input Capacitance
Output Capacitance
Clock Capacitance
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
39
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 21: DC Characteristics
All currents are in RMS unless otherwise noted
VCC = 1.70V–1.95V
VCCQ = 1.70V–2.24V
PARAMETER
Input Low Voltage
Input High Voltage
Output Low Voltage
IOL = 100µA
Output High Voltage
IOH = -100µA
VPP Lockout Voltage
VCC Lock
Input Load Current
Output Leakage Current
VCC Standby Current
Asynchronous Read Current @ 5 MHz
4-word Page Read Current @ 13 MHz
8-word Page Read Current @ 13 MHz
16-word Page Read Current @ 13 MHz
Vcc Continuous Burst Read Current
4-word Page Read Current @ 54 MHz/66 MHz
8-word Page Read Current @ 54 MHz/66 MHz
16-word Page Read Current @ 54 MHz/66 MHz
Continous Burst Read Current @ 54 MHz/66 MHz
VCC Program Current
VPP = VPP1, Program in Progress
VPP = VPP2, Program in Progress
VCC Block Erase Current
VPP = VPP1, Block Erase in Progress
VPP = VPP2, Block Erase in Progress
VCC Program Suspend Current
VCC Erase Suspend Current
VCC Automatic Power Save Current
VPP Standby Current
VPP Program Suspend Current
VPP Erase Suspend Current
VPP Read Current
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
SYM
MIN
TYP
VIL
VIH
VOL
-0.4
VCCQ - 0.4
-0.1
VOH
VCCQ - 0.1
V
VPPLK
VLKO
ILI
ILO
ICCS
ICCR
0.4
1.0
V
V
µA
µA
µA
mA
ICCR
UNITS
NOTES
0.4
VCCQ + 0.03
0.1
V
V
V
1
1
10
5
2
2
2
±1
±1
50
7
4
4
4
3
3
3
8
5
5
5
12
18
8
25
15
18
8
10
10
10
30
15
50
50
50
µA
µA
µA
0.2
5
µA
0.2
2
5
15
µA
0.2
ICCR
MAX
2, 3
mA
mA
5
mA
ICCW
ICCE
mA
ICCWS
ICCES
ICCAPS
IPPS
IPPWS
IPPES
IPPR
40
4
4
4
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 21: DC Characteristics
All currents are in RMS unless otherwise noted
VCC = 1.70V–1.95V
VCCQ = 1.70V–2.24V
PARAMETER
SYM
VPP Program Current
VPP = VPP1, Program in Progress
VPP = VPP2, Program in Progress
VPP Erase Current
VPP = VPP1, Erase in Progress
VPP = VPP2, Erase in Progress
IPPW
MIN
TYP
MAX
0.05
8
0.10
22
0.05
8
0.10
22
UNITS
NOTES
mA
mA
IPPE
NOTE:
1. VIL may decrease to -0.4V and VIH may increase to VCCQ + 0.3V for durations not to exceed 20ns.
2. APS mode reduces ICC to approximately ICCS levels.
3. Test conditions: VCC = VCC (MAX), CE# = VIL, OE# = VIH. All other inputs = VIH or VIL.
4. ICCES and ICCWS values are valid when the device is deselected. Any READ operation performed while in suspend
mode will have an additional current draw of suspend current (ICCES or ICCWS).
5. ICCR Burst current measurements are made in wrap mode.
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
41
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 22: Asynchronous READ Cycle Timing Requirements
See Figure 19 and Figure 20 for timing requirements and load configuration.
-60
PARAMETER
SYMBOL
READ cycle time
t
Address to output delay
t
CE# LOW to output delay
MIN
-70
MAX
60
RC
MIN
MAX
70
UNITS
ns
AA
60
70
ns
t
ACE
60
70
ns
OE# LOW to output delay
t
AOE
20
30
ns
RST# HIGH to output delay
t
RWH
150
150
ns
CE# LOW to output in Low-Z
t
CEZ
0
OEZ
0
0
ns
0
ns
OE# LOW to output in Low-Z
t
CE# or OE# HIGH to output High-Z
t
Output hold from address, CE# or OE# transition
t
OH
0
0
ns
Address setup to ADV# HIGH
t
AVS
7
7
ns
CE# LOW to ADV# HIGH
t
7
7
ns
5
OD
CVS
ADV# LOW to output delay
t
20
60
AADV
70
ns
ns
t
VP
7
7
ns
ADV# pulse width HIGH
t
VPH
7
7
ns
Address hold from ADV# HIGH
t
AVH
7
7
ns
Page address access
t
ADV# pulse width LOW
15
APA
22
ns
Figure 19: AC Input/Output Reference Waveforms
VCCQ
Input
VCCQ/2
VCCQ/2
Test Points
Output
VSS
VCCQ
90% VCCQ
Input
Rise and Fall Levels
10% VCCQ
VSS
NOTE:
AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input timing begins at VCCQ/2, and output timing
ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5ns.
Figure 20: Output Load Circuit1
VCCQ
16.7K
I/O
16.7K
30pF
VSS
NOTE:
1. Minimum recommended capacitive loading is 5pF.
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
42
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 23:
Burst READ Cycle Timing Requirements
-606
PARAMETER
SYM
CLK period
t
CLK
CLK frequency
f
CLK
t
CLK HIGH (LOW) time
CLK fall (rise) time
MIN
-705
MAX
MIN
15
MAX
18.5
ns
66
3
KP
54
MHz
3
ns
6
ns
2
tKHKL
7
UNITS
7
ns
Address valid setup to CLK
tAKS
ADV# LOW setup to CLK
tVKS
7
7
ns
CE# LOW setup to CLK
tCKS
7
7
ns
11
14
ns
CLK to output valid (latency codes 3, 4, and 5)
tACLK
CLK to output valid (latency code 2)
tACLK
Output hold from CLK
tKOH
3
3
ns
Address hold from CLK
tAKH
7
7
ns
CLK to WAIT# valid
tKHTL
11
14
ns
CE# LOW to WAIT# valid
tCEWV
11
14
ns
CE# HIGH to WAIT# High-Z
tCEWZ
11
14
ns
CE# HIGH between subsequent burst READs
t
See Note 1
See Note 1
14
CBPH
18
ns
NOTE:
1. Maximum frequency for latency code 2 = 40 MHz (tACLK = 20ns).
Table 24:
WRITE Cycle Timing Requirements
-60/-70
PARAMETER
SYMBOL
MIN
tRS
150
ns
CE# setup to WE# going LOW
tCS
0
ns
Write pulse width
tWP
40
ns
Data setup to WE# (CE#) going HIGH
t
DS
40
ns
Address setup to WE# (CE#) going HIGH
t
AS
40
ns
CE# hold from WE# HIGH
t
CH
0
ns
Data hold from WE# (CE#) HIGH
t
DH
0
ns
t
AH
0
ns
RST# HIGH recovery to CE# going LOW
Address hold from WE# HIGH
t
Write pulse width HIGH
WPH
MAX
UNITS
20
ns
ns
ns
VPS
200
VPP hold from valid SRD
tVPPH
0
WP# hold from valid SRD
tRHH
0
ns
WP# setup to WE# going HIGH
tRHS
200
ns
WE# HIGH to OE# LOW
tWOA
0
ns
Write recovery before READ
tWOS
50
ns
tWB
tAA+20
ns
WAV
0
ns
t
VPP setup to WE# going HIGH
WE# HIGH to output valid
t
WE# HIGH to address valid
WE# HIGH to CLK valid
t
WCV
12
ns
WE# HIGH to ADV# HIGH
tWAH
12
ns
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
43
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8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 25: ERASE and PROGRAM Timing Requirements
VPP1
OPERATION
PARAMETER
MAX
TYP
MAX
UNIT
NOTES
2.5
0.25
2.5
s
1, 2
0.7
4
0.4
4
s
1, 2
ERS/PB
Erasing and Suspending
0.3
8KW parameter block
t
ERS/MB
64KW main block
t
PROGRAM SUSPEND
5
10
5
10
µs
1
t
ERASE SUSPEND
20
25
20
25
µs
1
t
PROG/W
Conventional Word Programming
8
130
Single word
8
130
µs
1
t
PROG/PB
8KW parameter block
0.03
0.07
0.03
0.07
s
1, 2
PROG/MB
64KW main block
0.24
0.6
0.24
0.6
s
1, 2
16
3.5
16
µs
Suspend
Latency
SUSP/P
SUSP/E
t
Program
Operation
Latency
TYP
t
Erase Time
Program
Time
DESCRIPTION
VPP2
Fast Programming Algorithm
3.5
FPA/W
Single word
t
FPA/PB
8KW parameter block
15
15
ms
1, 2
t
FPA/MB
64KW main block
120
120
ms
1, 2
t
5
FPA/SETUP
FPA Setup
t
Program-to-verify transition
2.7
5.6
FPA/VERIFY
Verify
1.7
130
t
FPA/TRAN
t
5
µs
2.7
5.6
µs
1.7
130
µs
NOTE:
1. Excludes external system-level overhead.
2. Exact results may vary based on system overhead.
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
44
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 21: Single Asynchronous READ Operation (Nonlatched Mode)
tRC
A0–A22
VIH
VALID
ADDRESS
VIL
tAA
CE#
VIH
VIL
tACE
OE#
tOD
tAOE
VIH
VIL
tOEZ
WE#
tCEZ
VIL
DQ0–DQ15
tOD
VIH
VOH
tOH
High-Z
High-Z
VALID
OUTPUT
VO L
UNDEFINED
READ Timing Parameters
-60
SYMBOL
tRC
MIN
-70
MAX
60
MIN
-60
MAX
70
UNITS
SYMBOL
MIN
MAX
UNITS
tCEZ
0
0
ns
0
0
ns
AA
60
70
ns
t
tACE
60
70
ns
tOD
t
20
30
ns
t
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
MAX
ns
t
AOE
MIN
-70
OEZ
OH
45
5
0
20
0
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 22: Latched Asynchronous READ Operation
tRC
A3–A22
VIH
VALID
ADDRESS
VIL
A0–A3
VALID
ADDRESS
VIH
VALID
ADDRESS
VIL
VALID
ADDRESS
tAA
tAVS
tVPH
ADV#
tAVH
VIH
VIL
tVP
tAADV
tACE
CE#
VIH
VIL
tCVS
OE#
tAOE
tOD
VIH
VIL
tOD
tOEZ
WE#
VIH
tCEZ
VIL
DQ0–DQ15
VOH
High-Z
High-Z
VALID
OUTPUT
VO L
tOH
UNDEFINED
READ Timing Parameters
-60
SYMBOL
t
RC
MIN
-70
MAX
60
MIN
-60
MAX
70
UNITS
SYMBOL
MIN
-70
MAX
MIN
MAX
UNITS
ns
t
OH
0
0
ns
tAA
60
70
ns
tAVS
7
7
ns
t
60
70
ns
t
7
7
ns
t
20
30
ns
t
t
150
150
ns
t
7
7
ns
ns
t
VPH
7
7
ns
ns
tAVH
7
7
ns
ACE
AOE
RWH
t
CEZ
0
tOEZ
0
t
OD
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
0
0
5
20
CVS
60
AADV
VP
70
ns
ns
46
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 23: Page Mode READ Operation
A3–A22
VIH
VALID
ADDRESS
VIL
A0–A3
VIH
VALID
ADDRESS
VIL
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
tAA
tAVS
tVPH
ADV#
tAVH
VIH
VIL
tVP
tAADV
tACE
CE#
VIH
VIL
tCVS
OE#
tAOE
tOD
VIH
VIL
tOEZ
WE#
tCEZ
VIL
WAIT#
tOD
VIH
VOH
High-Z
High-Z
Note 1
VO L
tAPA
DQ0–DQ15
VOH
High-Z
tOH
VALID
OUTPUT
VO L
VALID
OUTPUT
VALID
OUTPUT
High-Z
VALID
OUTPUT
UNDEFINED
NOTE:
1. WAIT# is shown active LOW.
READ Timing Parameters
-60
SYMBOL
MIN
-70
MAX
MIN
-60
MAX
UNITS
SYMBOL
MIN
-70
MAX
MIN
MAX
UNITS
tAA
60
70
ns
tAVS
7
7
ns
t
ACE
60
70
ns
t
7
7
ns
tAOE
30
30
ns
tAADV
150
150
ns
t
VP
7
7
ns
ns
tVPH
7
7
ns
ns
t
7
ns
t
t
RWH
tCEZ
0
t
0
OEZ
OD
OH
0
5
t
t
0
0
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
20
0
CVS
AVH
APA
60
70
7
15
ns
ns
22
ns
ns
47
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 24: Single Burst READ Operation
tCLK
CLK
VIH
Note 1
VIL
tAKH
tAKS
A0–A22
VIH
tKP
tKP
VALID
ADDRESS
VIL
tAVS
tVPH
ADV#
tVKS
VIL
CE#
tCEWZ
tVP
VIH
VIL
OE#
tAVH
VIH
tCVS
tAOE
VIH
VIL
tOD
tCKS
WE#
VIH
VIL
WAIT#
tOEZ
tOD
tCEWV
High-Z
VOH
High-Z
Note 2
VOL
tACLK
DQ0–DQ15
VOH
tKOH
High-Z
High-Z
VALID
OUTPUT
VO L
tOH
UNDEFINED
NOTE:
1. Figure 6 on page 19 describes how to insert clock cycles during initial access.
2. WAIT# is shown active LOW, and WAIT# configured during delay (RCR8 = 0, RCR10 = 0).
READ Timing Parameters
-606
SYMBOL
MIN
OEZ
0
OD
OH
t
AVS
MIN
0
7
-606
UNITS
30
ns
tVKS
ns
t
ns
t
1
11
14
ns
tACLK2
20
20
ns
t
3
3
ns
7
7
ns
20
0
7
SYMBOL
MAX
7
KOH
MIN
MAX
7
7
CKS
ACLK
MIN
-705
MAX
0
5
t
t
MAX
20
tAOE
t
-705
UNITS
ns
7
ns
ns
t
7
7
ns
t
t
7
7
ns
t
TBD
14
ns
ns
t
TBD
14
ns
CVS
VP
tVPH
t
AVH
tCLK
t
AKS
7
7
7
7
ns
15
18.5
ns
7
7
ns
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
AKH
CEWV
CEWZ
NOTE:
1. Latency codes 3, 4, and 5.
2. Latency code 2.
48
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 25: READ Timing Parameters for Four-Word BURST Operation
tCLK
CLK
VIH
Note 1
VIL
tAKS
A0–A22
VIH
tKP
tAKH
tKP
VALID
ADDRESS
VIL
tAVS
tVKS
tVPH
ADV#
VIL
CE#
tAVH
VIH
tVP
tCBPH
VIH
VIL
tCVS
OE#
VIL
WE#
WAIT#
tAOE
tOD
VIH
tCKS
tOD
tOEZ
VIH
VIL
tCEZ
tKHTL
tOH
High-Z
VOH
High-Z
Note 2
VOL
tACLK
DQ0–DQ15
VOH
tKOH
High-Z
VALID
OUTPUT
VO L
VALID
OUTPUT
VALID
OUTPUT
High-Z
VALID
OUTPUT
UNDEFINED
NOTE:
1. Figure 6 on page 19 describes how to insert clock cycles during initial access.
2. WAIT# is shown active LOW, and WAIT# configured during delay (RCR8 = 0, RCR10 = 0).
READ Timing Parameters
-606
SYMBOL
MIN
-705
MAX
MIN
20
-606
MAX
UNITS
30
SYMBOL
MIN
-705
MAX
MIN
MAX
UNITS
ns
t
VKS
7
7
ns
tCEZ
0
0
ns
tCKS
7
7
ns
t
0
0
ns
t
ACLK
1
11
14
ns
t
ACLK2
20
20
t
AOE
OEZ
5
tOD
20
t
0
0
ns
tKOH
3
t
7
7
ns
t
7
ns
t
t
OH
AVS
t
CVS
7
7
t
VP
7
7
ns
tVPH
7
7
ns
t
7
7
ns
15
18.5
ns
7
7
ns
AVH
tCLK
t
AKS
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
AKH
ns
7
11
KHTL
CBPH
3
14
ns
14
18
ns
ns
ns
NOTE:
1. Latency codes 3, 4, and 5.
2. Latency code 2.
49
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 26: WAIT# Functionality for End-of-Word Line (EOWL) Condition
CLK
VIH
Note 1
VIL
tAKS
A0–A22
VIH
tAKH
VALID
ADDRESS
VIL
tAA
tAVS
tVPH
ADV#
tAVH
VIH
VIL
CE#
tVKS
tVP
tAADV
VIH
tACE
VIL
OE#
tCVS
VIH
tAOE
VIL
tCKS
tOEZ
tCEZ
VIH
WE#
tCEWV
VIL
WAIT#
VOH
tKHTL
High-Z
High-Z
Note 2
VOL
tACLK
tKOH
DQ0–DQ15
High-Z
VOH
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
High-Z
VO L
UNDEFINED
NOTE:
1. Figure 6 on page 19 describes how to insert clock cycles during initial access.
2. WAIT# is shown active LOW, and WAIT# configured during delay (RCR8 = 0, RCR10 = 0).
READ Timing Parameters
-606
SYMBOL
MIN
-705
MAX
MIN
-606
MAX
UNITS
SYMBOL
MIN
-705
MAX
MIN
MAX
UNITS
tAA
60
70
ns
tVKS
7
7
ns
t
ACE
60
70
ns
t
7
7
ns
tAOE
20
30
ns
t
ACLK1
11
14
20
20
CKS
ns
t
0
0
ns
tACLK2
t
0
0
ns
t
3
3
ns
t
7
7
ns
t
7
7
ns
ns
t
11
14
ns
ns
t
TBD
14
ns
CEZ
OEZ
AVS
t
CVS
7
7
60
tAADV
70
t
VP
7
7
ns
tVPH
7
7
ns
t
AVH
7
7
ns
tAKS
7
7
ns
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
KOH
AKH
KHTL
CEWV
NOTE:
1. Latency codes 3, 4, and 5.
2. Latency code 2.
50
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 27: WAIT# Signal in Burst Non-READ ARRAY Operation
CLK
VIH
Note 1
VIL
tAKS
A0–A22
VIH
tAKH
VALID
ADDRESS
VIL
tAVS
tVPH
ADV#
tVKS
tAVH
VIH
VIL
tVP
CE#
VIH
VIL
tCVS
OE#
tOD
tAOE
VIH
VIL
tCKS
WE#
tOEZ
VIH
VIL
WAIT#
tCEZ
tOD
High-Z
VOH
VOL
tOH
tKOH
tACLK
DQ0–DQ15
High-Z
Note 2
VOH
High-Z
High-Z
VALID
OUTPUT
VO L
UNDEFINED
NOTE:
1. Figure 6 on page 19 describes how to insert clock cycles during initial access.
2. WAIT# is shown active LOW, and WAIT# configured during delay (RCR8 = 0, RCR10 = 0).
READ Timing Parameters
-606
SYMBOL
MIN
-705
MAX
MIN
20
-606
MAX
UNITS
30
SYMBOL
MIN
-705
MAX
MIN
MAX
UNITS
ns
tAKS
7
7
ns
t
CEZ
0
0
ns
t
VKS
7
7
ns
tOEZ
0
0
ns
tCKS
7
7
ns
11
14
20
20
tAOE
5
tOH
0
0
ns
t
t
7
7
ns
tKOH
3
3
ns
t
7
7
ns
OD
AVS
20
ns
ns
tACLK1
t
t
7
7
ns
t
7
7
ns
t
VPH
7
7
ns
tAVH
7
7
ns
CVS
VP
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
ACLK2
AKH
NOTE:
1. Latency codes 3, 4, and 5.
2. Latency code 2.
51
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 28: WAIT# Signal in Asynchronous READ Operation
tRC
A0–A22
VIH
VALID
ADDRESS
VIL
tAA
CE#
VIH
VIL
tACE
tAOE
OE#
tOD
VIH
VIL
tOD
tOEZ
WE#
VIH
tCEZ
VIL
WAIT#
VOH
High-Z
High-Z
Note 1
VOL
DQ0–DQ15
VOH
High-Z
High-Z
VALID
OUTPUT
VO L
tOH
UNDEFINED
NOTE:
1. WAIT# shown active LOW.
READ Timing Parameters
-60
SYMBOL
t
RC
MIN
-70
MAX
60
MIN
-60
MAX
70
UNITS
SYMBOL
t
0
0
CEZ
t
60
70
ns
t
t
60
70
ns
t
t
20
30
ns
t
AA
ACE
AOE
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
MIN
ns
OEZ
52
MAX
MIN
0
MAX
0
ns
20
0
UNITS
ns
0
5
OD
OH
-70
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 29: Two-Cycle WRITE Operation
Note 1
A0–A22
VIH
VIL
VALID
ADDRESS
VALID
ADDRESS
VALID
ADDRESS
tAS
tWAV
tAVS
tAVH
tAH
ADV#
VIH
VIL
tVP
tWAH
CE# (WE#)
VIH
VIL
tCS
OE#
VIH
VIL
WE# (CE#)
tCH
tWP
tWOS
tWPH
VIH
VIL
tRS
DQ0–DQ15
VIH
tWB
tDH
High-Z
DATA IN
VIL
High-Z
High-Z
DATA IN
VALID
SRD
High-Z
tDS
VIH
RST#
VIL
tRHS
tRHH
VIH
WP#
VIL
tVPS
tVPPH
VVPPH
VPP VPPLK
VIL
UNDEFINED
NOTE:
1. Status register data (SRD) may be read after a two-cycle PROGRAM/ERASE sequence to determine completion of the PROGRAM/ERASE algorithm.
READ/WRITE Timing Parameters
-60/-70
-60/-70
SYMBOL
MIN
t
150
ns
t
20
ns
t
0
ns
t
7
ns
t
40
ns
t
200
ns
t
DS
40
ns
t
0
ns
tAS
0
ns
200
ns
RS
CS
WP
MAX
UNITS
SYMBOL
WPH
VP
VPS
VPPH
40
ns
tRHH
t
CH
0
ns
t
tDH
0
ns
tWOS
t
AH
0
ns
t
tAVH
7
ns
tWAV
t
7
ns
t
AVS
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
MIN
RHS
WB
WAH
53
t
MAX
UNITS
50
ns
AA + 20
ns
0
ns
12
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 30: Clock Suspend
VIH
CLK
VIL
tCLK
tKP
tKP
tAKS
VIH
A0–A22
tAKH
VALID
ADDRESS
VIL
VALID
ADDRESS
tAVS
tVPH
ADV#
tVKS
tAVH
VIH
VIL
tCBPH
tVP
CE#
VIH
VIL
tAOE
tCVS
tCEZ
OE#
VIL
WE#
tOD
VIH
tCKS
tOD
tOEZ
tAOE
VIH
VIL
WAIT#
VOH
tOH
tKHTL
High-Z
High-Z
VOL
tKOH
tACLK
DQ0–DQ15
VOH
High-Z
VALID
OUTPUT
VO L
VALID
OUTPUT
High-Z
High-Z
VALID
OUTPUT
VALID
OUTPUT
High-Z
UNDEFINED
READ Timing Parameters
-606
SYMBOL
MIN
-705
MAX
MIN
20
t
AOE
-606
SYMBOL
MIN
-705
MAX
UNITS
30
ns
t
AKS
7
MAX
MIN
7
MAX
UNITS
ns
tCEZ
0
0
ns
tVKS
7
7
ns
t
0
0
ns
t
7
7
ns
ns
tACLK1
11
14
20
20
OEZ
5
tOD
20
CKS
ns
t
OH
0
0
ns
tACLK2
tAVS
7
7
ns
t
KOH
3
3
ns
ns
tAKH
7
7
ns
ns
t
ns
t
t
CVS
t
VP
t
VPH
t
AVH
tCLK
t
KP
7
7
7
7
7
7
7
7
ns
15
18.5
ns
3
tKHKL
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
6
2
CBPH
14
14
18
ns
ns
NOTE:
1. Latency codes 3, 4, and 5.
2. Latency code 2.
ns
3
11
KHTL
ns
54
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 31: Asynchronous READ-to-WRITE Operation
tRC
tAS
tAA
A0–A22
VIH
VALID
ADDRESS
VIL
VALID
ADDRESS
tACE
CE#
tAH
tOD
VIH
VIL
tAOE
OE#
tOD
VIH
VIL
WE#
tCS
VIL
tOEZ
tCEZ
DQ0–DQ15
tCH
tWP
VIH
VOH
tOH
High-Z
tDS
High-Z
VALID
OUTPUT
VO L
tDH
High-Z
DATA IN
UNDEFINED
READ Timing Parameters
-60
SYMBOL
MIN
WRITE Timing Parameters
-70
MAX
MAX
SYMBOL
MIN
MAX
UNITS
ns
t
0
ns
60
70
ns
t
40
ns
t
60
70
ns
t
40
ns
t
20
30
ns
t
AS
40
ns
ns
tCH
0
ns
ns
t
DH
0
ns
ns
tAH
0
ns
RC
AA
ACE
AOE
tCEZ
0
t
0
OEZ
OH
0
0
5
tOD
t
70
UNITS
t
t
60
MIN
-60/-70
0
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
20
0
CS
WP
DS
ns
55
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 32: WRITE-to-Asynchronous-READ Operation
tAS
A0–A22
VIH
tRC
VALID
ADDRESS
VIL
CE#
tAH
VALID
ADDRESS
tCS
VIH
tCH
tOH
VIL
tWAV
tWP
VIH
WE#
VIL
tWOA
VIH
OE#
VIL
tAOE
tAA
tDS
DQ0–DQ15
VOH
High-Z
VO L
tDH
tOD
tACE
tOD
High-Z
DATA IN
High-Z
VALID
OUTPUT
tRS
VIH
RST#
VIL
UNDEFINED
READ Timing Parameters
-60
SYMBOL
t
RC
MIN
WRITE Timing Parameters
-70
MAX
60
MIN
-60/-70
MAX
70
UNITS
SYMBOL
MIN
ns
t
150
ns
RS
MAX
UNITS
tAA
60
70
ns
tCS
0
ns
t
ACE
60
70
ns
t
40
ns
tAOE
20
30
ns
tDS
40
ns
5
20
ns
t
40
ns
ns
t
0
ns
t
0
ns
t
0
ns
tWOA
0
ns
t
0
ns
t
OD
t
OH
0
0
WP
AS
CH
DH
AH
WAV
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
56
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 33: Burst READ-to-WRITE Operation
tAKS
tAKH
tWAV
Note 1
CLK
tAVS
tAS
VALID
ADDRESS
A0–A22
VALID
ADDRESS
VALID
ADDRESS
tAH
tVPH
tVKS
tAVH
ADV#
tCKS
tCVS
tCBPH
tCH
CE#
tOD
tAOE
OE#
tCS
tWP
tWPH
WE#
tKHTL
WAIT#
tCEZ
tACLK
tKOH
tOEZ
High-Z
DQ0–DQ15
High-Z
tDS
High-Z
VALID
OUTPUT
tDH
High-Z
DATA IN
DATA IN
UNDEFINED
NOTE:
1. Figure 6 on page 19 describes how to insert clock cycles during initial access.
READ Timing Parameters
-606
SYMBOL
MIN
WRITE Timing Parameters
-705
MAX
MIN
20
-60/-70
MAX
UNITS
30
ns
t
0
ns
ns
t
40
ns
tDS
40
ns
t
t
AOE
t
CEZ
0
0
t
OEZ
0
0
t
OD
t
AVS
7
7
t
CVS
7
7
VPH
7
7
tAVH
7
7
ns
tAKS
7
7
ns
t
5
VKS
7
7
ns
t
CKS
7
7
ns
11
14
20
tACLK2
3
ns
tAKH
7
7
ns
KHTL
t
CBPH
11
14
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
14
18
MAX
UNITS
AS
40
ns
tCH
0
ns
t
DH
0
ns
tAH
0
ns
t
0
ns
t
20
ns
WAV
WPH
NOTE:
1. Latency codes 3, 4, and 5.
2. Latency code 2.
20
3
t
WP
ns
tKOH
MIN
CS
20
t
tACLK1
SYMBOL
ns
ns
57
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 34: Write-to-BURST READ Operation
tVKS
Note 1
tAKS
CLK
tAS
tAH
tAKH
VALID
ADDRESS
A0–A22
VALID
ADDRESS
tAVH
tWAH
tVP
ADV#
tCH
tCS
tCBPH
tCKS
CE#
tWAV
tWCV
tWP
WE#
tAOE
OE#
tKHTL
WAIT#
tACLK
tDS
DQ0–DQ15
High-Z
tDH
tACLK
tKOH
VALID
OUTPUT
DATA IN
VALID
OUTPUT
tRS
RST#
UNDEFINED
NOTE:
1. Figure 6 on page 19 describes how to insert clock cycles during initial access.
READ Timing Parameters
-606
SYMBOL
MIN
-705
MAX
MIN
20
tAOE
WRITE Timing Parameters
-60/-70
MAX
UNITS
SYMBOL
MIN
30
MAX
UNITS
ns
tRS
150
ns
t
7
7
ns
t
CS
0
ns
tAVH
7
7
ns
tWP
40
ns
t
AKS
7
7
ns
t
DS
40
ns
tVKS
7
7
ns
tAS
40
ns
ns
t
0
ns
ns
t
0
ns
t
0
ns
VP
7
t
CKS
t
ACLK
7
11
1
14
20
tACLK2
AH
3
3
ns
t
7
7
ns
AKH
11
tKHTL
t
CBPH
14
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
DH
20
t
KOH
CH
14
18
WAV
0
ns
tWCV
12
ns
t
12
ns
t
ns
WAH
ns
NOTE:
1. Latency codes 3, 4, and 5.
2. Latency code 2.
58
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Appendix A: CFI Table
Table 26: CFI
OFFSET
DATA
00
002C
0089
01
DESCRIPTION
Manufacturer’s ID (ManID)
Micron
Intel
Device ID Code (DevID)
Top boot block device code (Micron)
Bottom boot block device code (Micron)
Reserved
“QR”
“Y”
Primary OEM command set
Address for primary extended table
Alternate OEM command set
Address for OEM extended table
VCC MIN for Erase/Write; Bit 7–bit 4 volts in BCD; Bit 3–bit 0 100mV in BCD
VCC MAX for Erase/Write; Bit 7–bit 4 volts in BCD; Bit 3–bit 0 100mV in BCD
VPP MIN for Erase/Write; Bit 7–bit 4 volts in hex; Bit 3–bit 0 100mV in BCD
VPP MAX for Erase/Write; Bit 7–bit 4 volts in hex; Bit 3–bit 0 100mV in BCD
02 – 0F
10, 11
12
13, 14
15, 16
17, 18
19, 1A
1B
1C
1D
1E
1F
44C8
44C9
reserved
0051, 0052
0059
0003, 0000
0039, 0000
0000, 0000
0000, 0000
0017
0019
00B4
00C6
0003
20
0000
Typical timeout for maximum size multiple byte/word program, 2nµs, 0000 = not supported
21
000A
Typical timeout for individual block erase, 2nms, 0000 = not supported
22
0000
Typical timeout for full chip erase, 2ns, 0000 = not supported
23
0004
Maximum timeout for single byte/word program, 2nµs times typical, 0000 = not supported
24
0000
Maximum timeout for maximum size multiple byte/word program, 2nµs, 0000 = not
supported
25
0002
Maximum timeout for individual block erase, 2ns, 0000 = not supported
26
0000
Maximum timeout for full chip erase, 2ns, 0000 = not supported
27
0018
28
29
2A, 2B
0001
0000
0000, 0000
Device size, 2n bytes
Bus interface x8 = 0, x16 = 1, x32 = 2, x64 = 3
Flash device interface description 0000 = async
2C
2D, 2E
0002
007E, 0000
0007, 0000
0000, 0002
0040, 0000
0007, 0000
007E, 0000
0040, 0000
0000, 0002
0000, 0000
0000, 0000
0050, 0052
2F, 30
31, 32
33, 34
35, 36
37, 38
39, 3A
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MT28F1284W18_D.fm - Rev. D, 11/03 EN
Typical timeout for single byte/word program, 2nµs, 0000 = not supported
Maximum number of bytes in multibyte program or page, 2n
Number of erase block regions within device (8K words and 64K words)
Top boot block device erase block region information 1
Bottom boot block device erase block region information 1
Top boot block device erase block region information 1
Bottom boot block device erase block region information 1
Top boot block device erase block region information 2
Bottom boot block device erase block region information 2
Top boot block device erase block region information 2
Bottom boot block device erase block region information 2
Reserved for future erase block region information
Reserved for future erase block region information
“PR”
59
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 26: CFI (continued)
OFFSET
DATA
3B
3C
3D
3E
3F
40
41
0049
0031
0033
00E6
0003
0000
0000
42
43, 44
45
46
47
48, 49
4A, 4B
0001
0003, 0000
0018
00C0
0001
0080, 0000
0003, 0003
4C
0005
4D
4E
4F
50
51
52
0004
0001
0002
0003
0007
Top: 0002
Bot: 0002
Top: 000F
Bot: 0001
Top: 0000
Bot: 0000
Top: 0011
Bot: 0011
Top: 0000
Bot: 0000
Top: 0000
Bot: 0000
Top: 0001
Bot: 0002
Top: 0007
Bot: 0007
Top: 0000
Bot: 0000
Top: 0000
Bot: 0040
53
54
55
56
57
58
59
5A
5B
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
DESCRIPTION
“I”
Major version number, ASCII
Minor version number, ASCII
Optional Feature And Command Support
Bit 0 Chip erase supported no = 0
Bit 1 Suspend erase supported = yes = 1
Bit 2 Suspend program supported = yes = 1
Bit 3 Chip lock/unlock supported = no = 0
Bit 4 Queued erase supported = no = 0
Bit 5 Instant individual block locking supported = yes = 1
Bit 6 Protection bits supported = yes = 1
Bit 7 Page mode read supported = yes = 1
Bit 8 Synchronous read supported = yes = 1
Bit 9 Simultaneous operation supported = yes = 1
Program supported after erase suspend = yes
Bit 0 block lock status active = yes; Bit 1 block lock down active = yes
VCC supply optimum, 00 = not supported, Bit 7–bit 4 volts in BCD; Bit 3–bit 0 100mV in BCD
VPP supply optimum, 00 = not supported, Bit 7–bit 4 volts in BCD; Bit 3–bit 0 100mV in BCD
Number of protection register fields in JEDEC ID space
Lock bytes LOW address, lock bytes HIGH address
2n factory programmed bytes, 2n user programmable bytes
Page mode read capability, 2n bytes
Number of synchronous mode read configuration fields that follow
Synchronous mode read capability configuration 1
Synchronous mode read capability configuration 2
Synchronous mode read capability configuration 3
Synchronous mode read capability configuration 4
Number of device hardware partition regions within the device
Number of identical partitions within the partition region
Number of identical partitions within the partition region
Number of PROGRAM/ERASE operations allowed in a partition
Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in
this region is in program mode
Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in
this region is in erase mode
Types of erase block regions in this partition region
Partition region 1 erase block type 1 information
Partition region 1 erase block type 1 information
Partition region 1 erase block type 1 information
60
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 26: CFI (continued)
OFFSET
DATA
5C
Top: 0002
Bot: 0000
Top: 0064
Bot: 0064
Top: 0000
Bot: 0000
Top: 0001
Bot: 0001
Top: 0003
Bot: 0003
5D
5E
5F
60
DESCRIPTION
Partition region 1 erase block type 1 information
Partition 1 (erase block type 1)
Partition 1 (erase block type 1)
Partition 1 (erase block type 1) bits per cell; internal ECC
Partition 1 (erase block type 1) page mode and synchronous mode capabilities
Partition region 1 erase block type 2 information
Bot: 61
Bot: 0006
Bot: 62
Bot: 0000
Bot: 63
Bot: 0000
Bot: 64
Bot: 0002
Partition region 1 erase block type 2 information
Partition region 1 erase block type 2 information
Partition region 1 erase block type 2 information
Partition region 1 (erase block type 2)
Bot: 65
Bot: 0064
Bot: 66
Bot: 0000
Bot: 67
Bot: 0001
Bot: 68
Top: 61
Bot: 69
Top: 62
Bot: 6A
Top: 63
Bot: 6B
Top: 64
Bot: 6C
Top: 65
Bot: 6D
Top: 66
Bot: 6E
Top: 67
Bot: 6F
Top: 68
Bot: 70
Top: 69
Bot: 71
Bot: 0003
Top: 0001
Bot: 000F
Top: 0000
Bot: 0000
Top: 0011
Bot: 0011
Top: 0000
Bot: 0000
Top: 0000
Bot: 0000
Top: 0002
Bot: 0001
Top: 0006
Bot: 0007
Top: 0000
Bot: 0000
Top: 0000
Bot: 0000
Partition region 1 (erase block type 2)
Partition region 1 (erase block type 2) bits per cell
Partition region 1 (erase block type 2) page mode and synchronous mode capabilities
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
Number of identical partitions within the partition region
Number of identical partitions within the partition region
Number of PROGRAM/ERASE operations allowed in a partition
Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in
this region is in program mode.
Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in
this region is in erase mode.
Types of erase block regions in this partition region
Partition region 2 erase block type 1 information
Partition region 2 erase block type 1 information
Partition region 2 erase block type 1 information
61
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 26: CFI (continued)
OFFSET
DATA
Top: 6A
Bot: 72
Top: 6B
Bot: 73
Top: 6C
Bot: 74
Top: 6D
Bot: 75
Top: 6E
Bot: 76
Top: 6F
Top: 0002
Bot: 0002
Top: 0064
Bot: 0064
Top: 0000
Bot: 0000
Top: 0001
Bot: 0001
Top: 0003
Bot: 0003
Top: 0007
Partition region 2 erase block type 1 information
Top: 70
Top: 0000
Partition region 2 erase block type 2 information
Top: 71
Top: 0040
Partition region 2 erase block type 2 information
Top: 72
Top: 0000
Partition region 2 erase block type 2 information
Top: 73
Top: 0064
Partition 2 (erase block type 2)
Top: 74
Top: 0000
Partition 2 (erase block type 2)
Top: 75
Top: 0001
Partition 2 (erase block type 2) bits per cell
Top: 76
Top: 0003
Partition 2 (erase block type 2) page mode and synchronous mode capabilities
77
78
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
DESCRIPTION
Partition 2 (erase block type 1)
Partition 2 (erase block type 1)
Partition 2 (erase block type 1) bits per cell
Partition 2 (erase block type 1) page mode and synchronous mode capabilities
Partition region 2 erase block type 2 information
TBD
Reserved
62
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
Appendix B: CSM Table
Table 27: Command State Machine Transition
Note that this table shows that the command state transitions are based on incoming commands. Only one partition can actively program or erase at a
time.
DEVICE NEXT STATE AFTER COMMAND INPUT
CURRENT CHIP STATE8
READ
ARRAY3
(FFh)
PROGRAM
SETUP4,5
(10h/40h)
ERASE
SETUP4,5
(20h)
FPA
SETUP4
(30h)
READY
Ready
Program
Setup
Erase
Setup
FPA
Setup
Ready (Lock Error)
LOCK/RCR SETUP
BLOCK
ERASE
CONFIRM,
PROGRAM/
ERASE
RESUME,
UNLOCK
BLOCK
CONFIRM9
(D0h)
PROGRAM/
ERASE
SUSPEND
(B0h)
CLEAR
STATUS
REGISTER 6
(50h)
READ
STATUS
(70h)
READ
ID/
QUERY
(90h,
98h)
Ready
Ready
LOCK,
UNLOCK,
LOCK
DOWN,
RCR
SETUP5
(60h)
OTP
SETUP5
(C0h)
Lock/RCR
Setup
OTP
Setup
LOCK
DOWN
BLOCK
CONFIRM9
(2Fh)
LOCK BLOCK
CONFIRM9
(01h)
WRITE RCR
CONFIRM9
(03h)
FPA EXIT
(ADDRESS
<> BA)
(FFFFh)
ILLEGAL
COMMANDS
OR FPA DATA
(OTHER CODES)2
WSM
OPERATION
COMPLETES
Ready
Ready (Lock Error)
Ready
Ready (Lock Error)
N/A
SETUP
OTP Busy
OTP
Ready
BUSY
Program Busy
SETUP
PROGRAM
Program Busy
BUSY
SUSPEND
Program Suspend
Program
Busy
SETUP
Ready (Error)
Erase Busy
SUSPEND
Erase
Suspend
Erase Suspend
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
BUSY
SUSPEND
LOCK/RCR SETUP IN
ERASE SUSPEND
SETUP
FAST
PROGRAMMING
ALGORITHM
FPA BUSY
FPA VERIFY
Ready (Error)
N/A
Erase Busy
Erase Busy
Erase Suspend
Ready
Lock/RCR
Setup in
Erase
Suspend
Erase Suspend
N/A
Program in Erase Suspend Busy
SETUP
PROGRAM IN
ERASE
SUSPEND
Program Suspend
Ready
Program
Suspend in
Erase
Suspend
Program in Erase Suspend Busy
Program Suspend in Erase Suspend
Program in
Erase
Suspend
Busy
Erase Suspend (Lock Error)
Erase
Suspend
Ready (Error)
FPA Busy
Erase
Suspend
Program in Erase Suspend Busy
Program Suspend in Erase Suspend
Erase Suspend (Lock Error)
Erase Suspend
N/A
Erase Suspend
(Lock Error)
N/A
Ready (Error)
FPA Busy7
Verify
Busy7
FPA Verify
FPA Busy7
Ready
FPA Verify7
Ready
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
63
ERASE
Program in
Erase
Suspend
Setup
Program Busy
Erase
Suspend
Erase Busy
BUSY
N/A
Program
Suspend
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
Table 27: Command State Machine Transition (continued)
Note that this table shows that the command state transitions are based on incoming commands. Only one partition can actively program or erase at a
time.
DEVICE NEXT STATE AFTER COMMAND INPUT
CURRENT CHIP STATE8
READ
ARRAY3
(FFh)
PROGRAM
SETUP4,5
(10h/40h)
ERASE
SETUP4,5
(20h)
FPA
SETUP4
(30h)
BLOCK
ERASE
CONFIRM,
PROGRAM/
ERASE
RESUME,
UNLOCK
BLOCK
CONFIRM9
(D0h)
PROGRAM/
ERASE
SUSPEND
(B0h)
READ
STATUS
(70h)
CLEAR
STATUS
REGISTER 6
(50h)
READ
ID/
QUERY
(90h,
98h)
LOCK,
UNLOCK,
LOCK
DOWN,
RCR
SETUP5
(60h)
OTP
SETUP5
(C0h)
LOCK BLOCK
CONFIRM9
(01h)
LOCK
DOWN
BLOCK
CONFIRM9
(2Fh)
WRITE RCR
CONFIRM9
(03h)
FPA EXIT
(ADDRESS
<> BA)
(FFFFh)
ILLEGAL
COMMANDS
OR FPA DATA
(OTHER CODES)2
WSM
OPERATION
COMPLETES
OUTPUT NEXT STATE AFTER COMMAND INPUT1
PROGRAM SETUP, ERASE
SETUP, OTP SETUP, PROGRAM
IN ERASE SUSPEND SETUP,
FPA SETUP, FPA BUSY,
VERIFY BUSY
Status
LOCK/RCR SETUP, LOCK/RCR
SETUP IN ERASE SUSPEND
Status
Array
READY, PROGRAM BUSY,
PROGRAM SUSPEND, ERASE
BUSY, ERASE SUSPEND,
PROGRAM IN ERASE SUSPEND
BUSY, PROGRAM SUSPEND IN
ERASE SUSPEND
Status
Output does
not change
Status
OTP BUSY
Array3
Status
Output does not change
Status
Output
does not
change
Status
ID/
Query
Status
Output does not change
Array
Output does
not change
64
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
2. Illegal commands are those not defined in the command set.
3. All blocks default to read array mode at power up.
4. Both cycles of two-cycle commands should be issued to the same block address. If they are issued to different blocks, the second WRITE determines the
active block.
5. If the CSM is active, both cycles of a two-cycle command are ignored.
6. The CLEAR STATUS command clears the status register error bits except when the CSM is running or during SUSPEND.
7. FPA writes are allowed only when SR0 = 0. FPA is busy if BA = address at FPA CONFIRM command. Any other commands are treated as data.
8. The current state is that of the WSM, not the block.
9. Confirm commands perform the operation and the move to the ready state.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
NOTE:
1. The output state shows the type of data that appears at the outputs if the block address is the same as the command address.
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Figure 35: 56-Ball VFBGA
0.10 C
0.700 ±0.075
SEATING PLANE
C
SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2%Ag OR
96.5% Sn, 3% Ag , 0.5% Cu
SUBSTRATE: PLASTIC LAMINATE
5.25
56X Ø 0.375
DIMENSIONS APPLY TO
SOLDER BALLS POST
REFLOW. THE PRE-REFLOW
BALL DIAMETER IS 0.35 ON
A 0.30 SMD BALL PAD.
MOLD COMPOUND: EPOXY NOVOLAC
BALL A1 ID
0.75
TYP
BALL A1 ID
BALL A1
4.50 ±0.05
BALL A8
4.50
9.00 ±0.10
2.25 ±0.05
0.75 TYP
1.00 MAX
2.625 ±0.050
5.50 ±0.05
11.00 ±0.10
NOTE:
1. All dimensions in millimeters.
Data Sheet Designation
Production: This data sheet contains minimum and maximum limits specified over the complete power supply
and temperature range for production devices. Although considered final, these specifications are
subject to change, as further product development and data characterization sometimes occur.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
65
Micron Technology, Inc., reserves the right to change products or specifications without notice..
©2003 Micron Technology, Inc
8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Revision History
Rev. D, Production .........................................................................................................................................................11/03
Updated Vcc and VCCQ MINs
Updated DC Table
Updated CFI Table
Removed TBDs from Timing Table
Rev. C, Production .........................................................................................................................................................10/03
Added Lead-free package
Updated DC Table
Updated Erase and Program Timing Tables
Updated CFI Table
Rev. B, Advance ................................................................................................................................................................8/03
• Removed support for the “Interleaved” Burst Option
• Expanded definition for tACLK
• Updated VFBGA package drawing and notes
• Added value for tCEWV and tCEWZ
Original document, Rev A., Advance .............................................................................................................................3/03
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
66
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.