MT90210 Multi-Rate Parallel Access Circuit Preliminary Information Features • • • • • • Parallel-to-serial and serial-to-parallel conversion of up to 1536 full duplex channels or 3072 time-slots Serial port data rates selectable between 2.048, 4.096 or 8.192 Mb/s Provides a mechanism for a double buffer function to be implemented in external memory 24 serial I/O lines programmable in different modes: 12 in/12 out at 8.192 Mb/s (1536 full duplex channels) or 24 bidirectional line modes for 2.048 and 4.096 Mb/s Provides a bidirectional 8-bit parallel port operating at 16.384 or 32.768 MByte/s for direct interface to external memory (dual port) Provides an external 13-bit output address bus for direct connection with an 8K-position dual port memory JTAG boundary scan Applications MT90210AL August 1998 100 Pin PQFP -40 to +85°C Description The MT90210 is a 100-pin device used to interface a parallel bidirectional 8 bit bus to 24 time division multiplexed (TDM) serial streams. The device is configured to perform simultaneous parallel-to-serial and serial-to-parallel conversion with the capability of handling up to 3072 channels, 1536 on the transmit and 1536 on the receive direction. Depending on the operation mode selected at the mode pins, the individual 64 Kb/s channels on the serial links may be configured as inputs or outputs. The data on the parallel bus is in a format suitable for interfacing with a dual-port RAM. Depending on the data rate selected by the MD0-MD2 input pins, serial data is clocked in and out on the serial streams at either 2.048, 4.096 or 8.192 Mb/s. RDin Strobe RBC R/W1 R/W2 External Memory Access Control S0 • • • • • • • • S23 Shift Registers Timing Generation Address Generator Write Counter Counter Analog PLL Read Boundary Scan Test MUX P0 • • P7 WBC SCLK HC4 C16C16+ F0i PCLK PLLVSS LP1,LP2 PLLAGND CKout RST PLLVDD Mode Control • • • • • • • • • • A0 • Fast access to ST-BUS, SCSA, MVIP, and H-MVIP serial backplanes Voice processing cards for Computer Telephony Integration (CTI) Video and teleconferencing bridge cards Fast DSP access to serial TDM buses TDI TCK TMS TRST TDO • ISSUE 2 Ordering Information A12 • DS5026 OEser MD2 MD1 MD0 Figure 1 - Functional Block Diagram 2-145 MT90210 A5 VSS VDD A4 A3 A2 VSS A1 A0 VDD Strobe VSS P7 P6 P5 VSS P4 VDD P3 P2 VSS P1 P0 R/W2 R/W1 VDD2 CKout PCLK RST PLLVDD Preliminary Information 80 78 76 74 72 70 68 66 64 62 60 58 56 54 52 50 82 48 84 46 86 44 88 42 90 40 100 PIN PQFP 92 38 94 36 96 34 98 32 100 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 PLLAGND LP1 LP2 PLLVSS IDDTN TD VSS2 C16C16+ VDD2 MD0 MD1 MD2 F0i TRST TCK TMS TDI HC4 SCLK S4 S5 S6 VDD VSS S7 S8 S9 S10 VSS S11 S12 S13 S14 S15 VDD VSS S16 S17 S18 S19 S20 VSS S21 S22 S23 TDO VSS2 RDin OEser A6 A7 VSS A8 A9 VDD A10 VSS A11 A12 RBC VDD VSS WBC S0 S1 S2 VSS VDD S3 Note: the PQFP package meets the JEDEC standard MO-108, CC1. Critical dimensions: Lead pitch = 0.65mm, Body Size = 14mm x 20mm, Package size = 17.9mm x 23.9mm. Figure 2 - Pin Connections Pin Description Pin Name Description 95-97, 100, 1-3, 6 S0-S2, S3, S4-S6, S7 Serial Lines 0-7 (TTL compatible with internal pullups in the range 25 - 125kΩ). Bidirectional, time division multiplexed serial streams. According to mode selected by MD0-2 inputs, distinct data rates can be selected at the serial port. In mode 3, these lines are configured as inputs only. In modes 1, 2, 4 and 5, these lines become bidirectional. 7-9, 11-15 S8-S10, S11-S15 Serial Lines 8-15. See description for S0-S7 above. In mode 3, S8-S11 are inputs and S12-S15 are outputs. In modes 1, 2, 4 and 5 these are bidirectional lines. 18-22, 24-26 S16-S20 S21-S23 Serial Lines 16-23. See descripton for S0 - S7 above. For mode 3, these lines are outputs and operate at 8.192 Mb/s rates. When operating in modes 1, 2, 4 and 5, these lines are bidirectional. 27 TDO Boundary Scan Test Data Output. 29 RDin Read P0-P7 input clock. This input is used by the MT90210 to sample bytes coming in at the parallel port P0-P7 lines. Typically, the user should connect CKout to this input. 30 OEser Serial Port Output Enable (Input). On the parallel-to serial conversion direction, this input is used by the MT90210 to know which time-slots on the serial output streams will be placed in high-impedance. This input is sampled synchronously along with the parallel input data before the parallel-to-serial conversion takes place. When low, output serial channels are actively driven. When set high, the output bus drivers are disabled. 2-146 MT90210 Preliminary Information Pin Description (continued) Pin Name Description 31 SCLK Serial Port Clock (input). The SCLK clock is used to control the serial port operation in modes 1,2,3 and 4. Depending on the operation mode selected at the MD0-MD2 inputs, this input can accept 4.096 (MD2-0=000), 8.192 (MD2-0=001) or 16.384 (MD2-0 =010 and 011) MHz clock. In mode 5, this input is ignored. 32 HC4 H-MVIP C4. This is a 4.096 MHz clock utilized in modes 4 and 5 to maintain compatibility with existing MVIP-90 systems. It is utilized to sample the frame pulse input (F0i). Not used in Modes 1 - 3. 33 TDI Boundary Scan Test Data Input. 34 TMS Boundary Scan Test Mode Select. 35 TCK Boundary Scan Test Clock. 36 TRST Boundary Scan Test Reset. 37 F0i 38-40 Frame Synchronization Signal (TTL compatible input). This input signal establishes the frame boundary for the serial input/output streams. MD2-MD0 Operation Mode Bits 0-2 (Input). Selects the data rate for the time division, multiplexed serial streams. 2.048 (mode 1, MD2-0=000), 4.096 (mode 2, MD2-0=001) or 8.192 (mode 3, MD2-0=010) Mb/s data rates are available. When MD2-0 are set to 011 (mode 4), the MT90210 operates in mixed data rates mode where S16-23 operate at 8.192 Mb/s and the remaining serial streams run at 2.048 Mb/s. In mode 5 (MD2-0=100), the MT90210 operates as per mode 4 but the device will accept a differential clock reference at 16.384 MHz at pins C16+ and C16-. 42 C16+ Serial Port Clock Input. In mode 5 (MD2-0= 100), this is a 16.384 MHz differential signal. Note used in Modes 1 - 3. 43 C16- Serial Port Clock Input. The complement to C16+. 45 TD 46 IDDTN Connect to Ground. 47 PLLVSS PLL Ground Input. 48 LP2 Loop Filter Input. An external RC circuit is required at this input, refer to Figure 10. 49 LP1 Loop Filter Input. An external RC circuit is required at this input, refer to Figure 10. 50 Reserved - Do not connect. PLLAGND PLL Analog Ground output. Provides ground to PLL loop filter, refer to Figure 10. 51 PLLVDD PLL Power Input. +5V 52 RST 53 PCLK Parallel Port Clock Input. CKout must be connected to this input. 54 CKout Internal VCO Output Signal. Output of internal PLL frequency multiplier. In mode 1 the frequency is 16.384 MHz, for the other modes the frequency is 32.768 MHz. Must be connected to PCLK only. 56 R/W1 Read/Write Output 1. This output signal toggles low for the last half of a memory write cycle indicating valid data. 57 R/W2 Read/Write Output 2. This output is low for memory read operations and high for memory write operations. RESET. A low on this pin resets the device. 2-147 MT90210 Preliminary Information Pin Description (continued) Pin Name Description 58-59, 61-62, 64, 66-68 P0-P1, P2-P3, P4, P5-P7 Parallel Input/Output Data Bus. This 8 bit data bus is a bidirectional parallel port used to perform 8-bit transactions between the MT90210 and the external dual port RAM. Data is clocked in and out of the P0-P7 parallel port according to Figures 22 and 23. 70 Strobe Strobe Output. This output is typically connected to the Chip-enable input of the external dual port RAM. It is kept low during all read cycles, stays high during inactive periods and goes low for the last half of a memory write cycle. 72-73, 75- 77, 80-82, 84-85, 87, 89-90 A0-A1, A2-A4, A5-A7, A8-A9, A10, A11-A12 External Memory Address Outputs A0-A12. These 13 address output lines are provided by the MT90210 to allow a direct connection to an external dual port RAM. 91 RBC Read Data Block Complete (output). A transition on this output is used to notify the external CPU that the MT90210 has finished reading the contents of one entire 125µs frame from the external dual port memory (e.g.; from addresses 0000h to 0FFFh in modes 3, 4 or 5). Whenever RBC toggles, the MT90210 starts reading the next half of the memory (addresses 1000h to 1FFFh) while the local CPU updates the first half with more data to be sent. RBC toggles every 125µs. When this signal is low, the MT90210 is reading the lower memory block. 94 WBC Write Data Block Complete (Output). A transition on this output is used to notify the external CPU that the MT90210 has finished writing the contents of one entire 125µs frame into the external dual port memory (e.g; from addresses 0000h to 0FFFh in modes 3,4 or 5). Once WBC toggles, the local CPU can access the Dual port memory to get the data while the MT90210 writes the contents of the next 125µs frame into the other half (addresses 1000h to 1FFFh) of the dual port memory. WBC toggles every 125µs. When this signal is low, the MT90210 is writing to the lower memory block. 4,16, 63, 71, 78, 86, 92, 99 VDD Supply Input. +5V. 41, 55 VDD2 Supply Input. +5V. 5,10, 17, 23, 60, 65, 69, 74, 79,83, 88, 93, 98 VSS Ground. 28 VSS2 Ground. 2-148 MT90210 Preliminary Information Functional Description The MT90210 is a 100-pin device that converts incoming serial telecom streams of 2.048, 4.096 or 8.192 Mb/s on to an 8-bit parallel bus, and converts input data on this parallel bus to the outgoing serial telecom links. The device is configured to perform simultaneous parallel-to-serial and serial-to-parallel conversion. MT90210 interfaces up to 24 bidirectional serial data streams to a byte oriented parallel port for access by a dual-port RAM. It contains an address generator for parallel port read and write operations directly to an external dual port memory. A single MT90210 device can handle up to 3072 channels, 1536 on the transmit and 1536 on the receive direction. Depending on the operation mode selected at the mode pins (MD0-MD2), the 64 kb/s serial telecom channels may be configured as inputs or outputs. The data on the parallel bus is in a format suitable for interfacing with popular dual port memories. Depending on the data rate selected by the MD0MD2 input pins, serial data is clocked in and out on the serial streams at either 2.048, 4.096 or 8.192 Mb/s, as shown in Figure 6. A mechanism for implementing external double buffering is provided by the Write Block Complete (WBC) and Read Block Complete (RBC) output pins. Double buffering the data allows the processor to independently access an entire frame of data in the external memory while the MT90210 reads or writes the complementary frame in the memory. For example, in mode 3 (Figure 4), during the first frame the MT90210 will read and write in to the first half of the memory space (Block 0) and during the second frame the MT90210 will read and write in to the second half of the memory space (Block 1). Within each block the transmit data and receive data are separated and located at fixed address locations. The operation of WBC and RBC is shown in Figures 7a and 7b. On the external memory port side, the device performs 8-bit wide operations with a cycle time of 30 or 61 ns. The parallel port operates at 16.384 MByte/s (for mode 1) or 32.768 MByte/s (for modes 2,3,4 and 5). To create the high speed clock required to manage the byte operations at the parallel port, a built in PLL multiplies the serial port input clock (SCLK) by a factor of two or four depending on the mode. In all operation modes, the user should connect the PLL CKout to PCLK input. A separate input pin, Output Enable serial (OEser pin 30), may be used to selectively tristate individual 64Kb/s serial links. By using a 9-bit external dual port RAM and connecting the ninth bit to OEser as shown in Figure 9, the processor may disable an individual channel by setting the ninth bit for that channel in the transmit (TX) portion of the current block. The remaining 8 bits for this channel may be any value since they are ignored by the MT90210 when the ninth bit is 1. To avoid contention on the serial bus, it is recommend that the user configure all serial streams as inputs at start-up. This may be done by setting all OEser bits to 1 in the TX portions of both memory blocks. In mode 3, the serial streams are permanently configured as 12 inputs and 12 outputs, and the state of OEser is ignored. An Overview of CTI bus protocols Multi-Vendor Integration Protocol (MVIP) provides a coherent approach to building solutions for worldwide markets by merging computing and communications technologies under one open architecture. MVIP ensures inter-operability among telephone-based resources (such as trunk interfaces, voice, video, fax, text-to-speech, speech recognition) for use within a computer chassis in an individual or networked configuration. H-MVIP addresses the need for higher telephony traffic capacity in individual computer chassis. H-MVIP defines three major items that together make a useful digital telephony transport and switching environment: the H-MVIP digital telephony bus with up to 3072 "time-slots" of 64 Kb/s each; a bus interface with digital switching that allows a group of H-MVIP interfaced circuit boards to provide complete, flexible, distributed telephony switching; and a logical device driver model and standard software interface to a logical model. Operating Modes The MT90210 device can operate in one of five modes appropriate for different application needs. Mode selection must be done while the device is in reset (RST low and a valid clock applied to the PCLK input). These modes are explained in the following paragraphs. Mode 1: The serial input/output format conforms to the ST-BUS requirements when the data rate is 2.048 Mb/s (see Figure 6). Serial port clock (SCLK) is 4.096 MHz. The on-chip PLL produces a phase locked 16.384 MHz clock (CKout) from the SCLK input. In this data rate operation, the 24 serial lines (S0-23) become bidirectional links at 2.048 Mb/s. The ST-BUS is a time-division multiplexed serial bus with 32, 8-bit channels per frame. Frame boundaries are delineated by the frame pulse. Figure 3 depicts 2-149 MT90210 Preliminary Information how the data from the serial port is mapped into the external dual port memory. 1536 bytes for TX 0000 768 bytes for TX 768 bytes for RX 06FF 0800 768 bytes for TX 768 bytes for RX 1536 bytes for RX 02FF 0400 BLOCK 0 BLOCK 1 BLOCK 0 1536 bytes for TX BLOCK 1 1536 bytes for RX 0AFF 0C00 0EFF 0FFF MODE 1 24 bidirectional streams at 2.048Mb/s Address outputs used: A0-A11; A12 always zero. 0000 05FF 0800 0DFF 1000 15FF 1800 1DFF 1FFF MODES 2 & 3 24 bidirectional streams at 4.096Mb/s, or 12 in / 12 out at 8.192Mb/s Address outputs used: A0-A12 Legend: unused memory space Legend: unused memory space Figure 3 - Dual Port RAM Memory Map for Mode 1 Mode 2: When the device is configured for 4.096 Mb/s data rate operation, each of the 24 timedivision multiplexed serial streams is made up of 64 channels. In this data rate operation, the 24 serial lines (S0-23) become bidirectional links at 4.096 Mb/s. Serial port clock (SCLK) is 8.192 MHz. The on-chip PLL produces a phase locked 32.768 MHz clock (CKout) from the SCLK input. Figure 4 depicts how the data from the serial port is mapped into the external dual port memory. Mode 3: When the device is configured for 8.192 Mb/s data rate operation, each of the 24 timedivision multiplexed serial streams is made up of 128 channels. In this mode, bidirectional operation on the serial port streams is not provided and the MT90210 is set in a 12 in / 12 out configuration and the OEser input is ignored. Streams S0-S11 are configured as inputs, and S12-S23 are configured as outputs. Serial port clock is 16.384 MHz. The on-chip PLL doubles this clock to produce a CKout clock of 32.768 MHz. Figure 4 depicts how the data from the serial port is mapped into the external dual port memory. Figure 12 and Table 3 show the write and read operations on the parallel port at the frame boundary. 2-150 Figure 4 - Dual Port RAM Memory Map for Modes 2 and 3 Mode 4: The MT90210 is configured such that the 24 serial streams are bidirectional and split into two different functional groups: (i) streams S0-S15 operate at 2 Mb/s rate (512 timeslots), (ii) S16-S23 operate at 8.192 Mb/s rate (1024 timeslots). Memory mapping for mode 4 is described in Figure 5. For compatibility with legacy MVIP timing, mode 4 provides an additional clock input at 4.096 MHz (HC4 input pin) which allows the device to detect frame sync pulse (F0i) with a typical width of 244 ns. In mode 4, the 16.384 (SCLK) and 4.096 (HC4) MHz clocks should be in sync according to H-MVIP specifications. The on-chip PLL doubles SCLK to produce a CKout signal of 32.768 MHz. Figure 13 and Table 4 show the write and read operations on the parallel port at the frame boundary. Mode 5: Identical operation as per mode 4 with the difference that the 16.384 MHz clock is a differential signal received at the two input pins, C16+ and C16of the MT90210 device. The differential clock is needed to eliminate distortion in the clock signal passing through a ribbon cable as per H-MVIP specification. The SCLK input is not used in this mode. Memory mapping for mode 5 is depicted in Figure 5. MT90210 Preliminary Information 512 bytes for 0000 S0-S15 TX 01FF 0400 1024 bytes for S16-S23 TX BLOCK 0 512 bytes for 0800 S0-S15 RX 09FF 0C00 1024 bytes for S16-S23 RX 512 bytes for 1000 S0-S15 TX 11FF 1400 1024 bytes for S16-S23 TX BLOCK 1 512 bytes for 1800 S0-S15 RX 19FF 1C00 1024 bytes for S16-S23 RX 1FFF S0-S15 bidirectional 2.048Mb/s streams S16-S23 bidirectional 8.192Mb/s streams Address outputs used: A0-A12 Legend: unused memory space Figure 5- External Double Buffer Operation and Memory Arrangement in Modes 4 and 5. Bidirectional Operation: Serial output channel timeslots can be tri-stated by setting the OEser input pin high during a specific parallel channel timeslot. Note that when operating in bidirectional mode, the MT90210’s I/O buffers on the serial port are permanently at high impedance and the control of contention on the serial bus has to be done by the user through the OEser input pin. In modes 1, 2, 4 and 5 all of the transmit channels on the serial port side are copied back to the memory interface. This is true only in bidirectional modes (i.e., modes 1, 2, 4 and 5). Note that only the transmit (output) channels are copied back to the memory and that the input channels remain unaffected. For a specific time-slot sampled at the external memory parallel interface, the respective OEser input pin must be in the desired state; i.e., the sampling of the OEser input is synchronized with the parallel byte read at the P0-P7 lines. Functional operation of the MT90210 device at the parallel interface for modes 1, 2, and 3 Figures 8, 12, and 13 depict the parallel port READ and WRITE operation of the MT90210 device. The state of the signals R/W1, R/W2 and Strobe defines a valid Read or a valid Write operation. During a valid READ operation the signals Strobe and R/W2 stay LOW while the signal R/W1 is always HIGH. For the valid WRITE operation the signal R/W2 always stays HIGH while the signals R/W1 and Strobe toggle. Table 3 represents the sequence of events as depicted in Figure 12 during the last channel at the end of an ST-BUS frame. The MT90210 device repeats the same sequence of operation during the entire frame. For example, during channel 127 at the end of an ST-BUS frame the MT90210 will write channel 126 (streams 0 to 11) and read from channel 1 (streams 12 to 23) of the next frame as shown in Table 3. Note that there is a two channel difference between a write and a read sequence. In mode 1 and mode 2, the MT90210 device performs a group of writes and a group of reads separated by 8 PCLK periods, while for modes 3, 4 and 5 they are separated by 4 PCLK periods. Functional operation of the MT90210 device at the parallel interface for mode 4 and mode 5 Table 4 represents the sequence of events when the MT90210 device is operating at a mixed rate of operation (mode 4 and mode 5) as depicted in Figure 13. The MT90210 device repeats the same sequence of operation as shown in Table 4 throughout the entire frame. In mode 4 and mode 5 the MT90210 device is configured with 24 bidirectional serial streams and split into two different rates: S0 to S15 operate at 2.048 Mb/s data rates (512 time-slots) and streams S16 to S23 run at 8 Mb/s data rates (1024 time-slots). In this mode, 12 writes are carried out during a parallel port write cycle and 12 reads during a read cycle. Of each group of 12, 8 are dedicated to the high-speed 8.192 Mb/s links, therefore four slots are available for the 2.048 Mb/s links. To process all the 16 streams devoted for 2.048 Mb/s, four separate write or read cycles are required (these slots are denoted with the suffix "a", "b", "c", "d" in Figure 13). Each write or read cycle will use four time-slots. For example, read or write cycle "a" uses streams S0 to S3, read or write cycle "b" uses streams S4 to S7, read or write cycle "c" uses streams S8 to S11 and read or write cycle "d" uses streams S12 to S15 (see Table 4). There is a two channel difference between a read and write sequence for 2 Mb/s data and an eight channel difference for 8 Mb/s data. 2-151 MT90210 Preliminary Information Frame Boundary Established by F0i SCLK (4 MHz) SCLK (8 MHz) SCLK, C16 (16 MHz) F0i Serial I/O 2 Mb/s Ch. 31, Bit 1 Serial I/O 4 Mb/s Serial I/O 8 Mb/s Ch. 31, Bit 0 Ch. 63, Bit 2 Ch. 63, Bit 1 Ch. 63, Bit 0 Ch. 0, Bit 7 Ch. 0, Bit 7 Ch. 127, Ch. 127, Ch. 127, Ch. 127, Ch. 127, Ch. 127, Ch. 0, Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Ch. 0, Bit 6 Ch. 0, Bit 6 Ch. 0, Bit 6 Ch. 0, Bit 5 Ch. 0, Bit 4 Ch. 0, Bit 5 Ch. 0, Bit 3 Figure 6 - Serial Port Functional Timing last write address of frame n W address x A0-A12 inactive R I P0-P7 T Data Out Data Out inactive E WBC MT90210 finishes writing data from frame n. MT90210 will handle parallel port transactions related to frame n +1. last read address of frame n R E A address y A0-A12 P0-P7 Data In Data In inactive inactive D WBC MT90210 finishes reading data from frame n. MT90210 will handle parallel port transactions related to frame n +1. Figure 7a - WBC and RBC Output Transition 2-152 Ch. 0, Bit 2 MT90210 Preliminary Information RBC 125 us WBC 125 us Exclusive access of Block 0 tNA tNA Access of both Block 0 & Block 1 Access of both Block 0 & Block 1 Exclusive access of Block 1 Exclusive access of Block 0 tNA ~ 1 timeslot for modes 1, 2 & 3 tNA ~ 3 timeslots for modes 4 & 5 Figure 7b - WBC and RBC operation in relation to accessing data from Block 0 and Block 1 SCLK PCLK A0-A12 ARD ARD AWR AWR R/W1 Toggles only during write data cycle R/W2 Changes state (high to low) on every change of a block of reads or block of writes Low during read cycle, high during inactive periods and toggles during write cycles Strobe P0-P7 RD RD WR WR Note: The MT90210 device performs groups of writes and groups of reads separated by 4 inactive PCLK periods for modes 3, 4 and 5. In mode 1 and mode 2, the write and read groups are separated by 8 PCLK periods. Figure 8 - Parallel Port Functional Read/Write Operation JTAG Support The MT90210 JTAG interface is designed according to the Boundary-Scan standard IEEE1149.1. The standard specifies a design-for-testability technique called Boundary-Scan Test (BST). A boundary-scan IC has a shift-register stage or ‘Boundary-Scan Cell’ (BSC) in between the core logic and the I/O buffers adjacent to each I/O pin. The BSCs can control and observe what happens at each I/O pin of the IC. The operation of the boundary-scan circuitry is controlled by a Test Access Port (TAP) Controller. Test Access Port (TAP) The Test Access Port (TAP) provides access to many test support functions built into the MT90210. It consists of three input connections and one output connection. The following connections form the TAP: • Test Clock Input (TCK) • Test Mode Select Input (TMS) • Test Data Input (TDI) • Test port Reset (TRST) • Test Data Output (TDO) 2-153 MT90210 I[0:1] [00] Preliminary Information Instruction EXTEST Description Boundary-Scan This instruction is specifically provided to allow board-level interconnect register selected, testing of opens, bridging errors etc. Test Enabled When the EXTEST instruction is selected, the on-chip logic is isolated from the MT90210’s I/O pin such that the value of the I/O pins is determined by its boundary-scan register. Data for the execution of this instruction can be preloaded into the boundary-scan register with the SAMPLE/PRELOAD instruction. [01], SAMPLE/ [10] PRELOAD Boundary-Scan Two functions can be performed by the use of this instruction. It allows a register selected, SAMPLE (‘snapshot’) of the normal operation of the MT90210 to be Test Disabled taken for examination. And, prior to the selection of another test operation, a PRELOAD can place data values into the latched parallel outputs of the Boundary-Scan cells. During the execution of the instruction, the on-chip logic operation is not hampered in any way. [11] Bypass register selected, Test Disabled BYPASS/ NOTEST This instruction is used to BYPASS the MT90210 while performing boundary-scan testing on other devices with scan registers in the same serial register chain. The MT90210 is allowed to function normally. This instruction is automatically loaded upon reset of the MT90210, as specified in IEEE1149.1 Table1 - Instruction Register Instruction Register In accordance with the IEEE 1149.1 standard, the MT90210 uses public instructions listed in Table 1. The MT90210 JTAG Interface contains a two bit instruction register. Instructions are serially loaded into the Instruction Register from the TDI when the TAP Controller is in its Shift-IR state. Subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current and to define the serial test data register path that is used to shift data between TDI and TDO during data register scanning. Test Data Registers As specified in the IEEE 1149.1 Standard, the MT90210 JTAG interface contains two test data registers: • The Boundary Scan Register • The Bypass Register The MT90210 boundary-scan register contains 144 bits. Bit 144 in Table 2 is the first bit clocked out. All tristate enable bits are asserted high: a logic 1 enables the corresponding group of outputs/bidirectionals. Note that clocking all zeros into the scan path register will set all outputs to tristate. 2-154 Bits Definition BSC Type † 1:60 S4 - S23 B 61 RDIN I 62 OEser I 63 SCLK I 64 HC4 I 65 F0i I 66:68 MD2 - MD0 I 69 RST I 70 PCLK I 71:72 CKO O 73:76 R/W1 - R/W2 O 77:100 P0 - P7 B 101:102 Strobe O 103:128 A0 - A12 O 129:130 RBC O 131:132 WBC O 133:144 S0 - S3 B Table 2 - Boundary Scan Register † B - bidirectional: input cell, output cell followed by tristate cell. I - input: input cell. O - output: output cell, followed by tristate cell. MT90210 Preliminary Information ST-BUS SCSA MVIP H-MVIP 24 +5V S0-S23 DUAL PORT RAM* +5V SEML Mode 1: 4.096 MHz Mode 2: 8.192 MHz Mode 3 & 4: 16.384 MHz SCLK Strobe CEL CER R/W2 OEL OER OEser 9th bit External 8 kHz F0i Mode 5: 16.384 MHz 9 P7-P0 C16+ I/O8L-I/O0L 13 Mode 5: 16.384 MHz A12L-A0L A12-A0 C16Mode 4 & 5: 4.096 MHz SEMR I/O8R-I/O0R HC4 A12R-A0R 9 R/WL R/W1 13 +5V MT90210 MS R/WR RDin BOUNDARY SCAN CONNECTOR 5 TRST TDI,TDO TMS,TCK PCLK CKout PLLAGND RST LP1 WBC LP2 RBC Interface to PC Bus and/or hardware control for monitoring purpose (Customer Specific Control Logic) MD0 MD1 MD2 * Note: Dual Port RAM: Cypress part number: CY7B145-15 and IDT part number IDT7015 Figure 9 - Functional Example of the MT90210 Application Circuit Applications The MT90210 device may be used in applications such as video and teleconferencing bridge cards and voice processing cards for CTI (Computer Telephony Integration). MT90210 transfers all TDM channels of the ST-BUS interface into an external buffer. This eliminates long answer time and permits fast DSP access to ST-BUS, SCSA, MVIP or H-MVIP serial TDM buses. The MT90210 component can be set in H-MVIP mode with 24 fully bidirectional serial streams that are configured in different data rate combinations. Two data I/O subsets of H-MVIP are provided by the MT90210: (i) the 24/2 mode in which all 24 lines operate at 2.048 Mb/s and (ii) the mixed rate of operation in which 16 streams operate at 2.048 Mb/s and the remaining 8 streams operate at 8.192 Mb/s data rates. When operating at 8.192 Mb/s rates, the MT90210 automatically terminates the C16+ and C16- differential clocks specified by the H-MVIP specifications. Figure 9 shows a functional block diagram of the MT90210 in a typical application. 2-155 MT90210 Preliminary Information MT90210 PLLAGND C1 LP1 C2 R2 R1 LP2 R1= 3kΩ R2= 100Ω + 5% C1= 10nF + 5% C2= 20pF Figure 10 - Analog PLL Low Pass Filter Circuit PLL Considerations • • • • • • Phase tolerance and jitter are independent of the PLL frequency. Jitter is affected by the noise on the PLLVDD and PLLVSS pins. It will increase if the noise level increases and is recommended to be kept less than 10 MHz on PLLVDD. Use of a C2 capacitor of 15-25pF (+10%) is recommended to reduce jitter. The components should be connected within one inch (1") of the package. Use a wide PCB trace for PLLVDD and PLLVSS separate from the device VDD/VSS connections. In some setups, an RC network (Figure 11) between PLLVDD and PLLVSS supplies helps to reduce jitter. 2-156 MT90210 +5V The MT90210 device contains an analog PhaseLocked Loop (PLL) which is used to create a higher speed clock for parallel port operation from the input SCLK. This analog PLL requires a loop filter circuit to be connected to the LP1 and LP2 pins, as shown in Figure 10. Additionally, the following design considerations are recommended for the PLL circuitry: 100Ω PLLVDD 1.0nF PLLVSS Figure 11 - PLLVDD/PLLVSS RC Circuit MT90210 Preliminary Information PCLK Cycle Read Write Channel Stream Memory Address 1 - wr 126 0 0DE8h 2 - wr 126 1 0DE9h 3 - wr 126 2 0DEAh 4 - wr 126 3 0DEBh 5 - wr 126 4 0DECh 6 - wr 126 5 0DEDh 7 - wr 126 6 0DEEh 8 - wr 126 7 0DEFh 9 - wr 126 8 0DF0h 10 - wr 126 9 0DF1h 11 - wr 126 10 0DF2h 12 - wr 126 11 0DF3h 13 to 16 INACTIVE 17 rd - 0 0 1000h 18 rd - 0 1 1001h 19 rd - 0 2 1002h 20 rd - 0 3 1003h 21 rd - 0 4 1004h 22 rd - 0 5 1005h 23 rd - 0 6 1006h 24 rd - 0 7 1007h 25 rd - 0 8 1008h 26 rd - 0 9 1009h 27 rd - 0 10 100Ah 28 rd - 0 11 100Bh 29 to 32 INACTIVE Table 3 - Functional Example of the Read and Write Operation (Mode 3) 2-157 MT90210 Preliminary Information PCLK Cycle Read Write 8Mb/s Channel 8 Mb/s Stream 2 Mb/s Channel 2 Mb/s Stream Memory Address 1 - wr 124 16 - - 0FE0h . . 8 - wr 124 23 - - 0FE7h 9 - wr - - 31 0 09F0h 10 - wr - - 31 1 09F1h 11 - wr - - 31 2 09F2h 12 - wr - - 31 3 09F3h 13 . . INACTIVE 16 17 to 24 rd - 4 16 to 23 - - 0420h to 0427h 25 to 28 rd - - - 1 0 to 3 0010h to 0013h 29 to 32 INACTIVE 33 to 40 - wr 125 16 to 23 - - 0FE8h to 0FEFh 41 to 44 - wr - - 31 4 to 7 09F4h to 09F7h 45 to 48 INACTIVE 49 to 56 rd - 5 16 to 23 - - 0428h to 042Fh 57 to 60 rd - - - 1 4 to 7 0014h to 0017h 61 to 64 INACTIVE 65 to 72 - wr 126 16 -23 - - 0FF0h to 0FF7h 73 to 76 - wr - - 31 8 to 11 09F8h to 09FBh 77 to 80 INACTIVE 81 to 88 rd - 6 16 to 23 - - 0430h to 0437h 89 to 92 rd - - - 1 8 to 11 0018h to 001Bh 93 to 96 INACTIVE 97 to 104 - wr 127 16 to 23 - - 0FF8h to 0FFFh 105 to 108 - wr - - 31 12 to 15 09FCh to 09FFh - - 0438h to 043Fh 109 to 112 113 to 120 121 to 124 2-158 INACTIVE rd - 7 16 to 23 rd 1 12 to 15 001Ch to 001Fh Table 4 - Functional Example of the Parallel Interface for Mode 4 and 5 MT90210 Preliminary Information F0i S23:S0 Frame n, last channel P7:P0 Write data from S23-S0 frame n, 2nd last channel Read data for S23-S0 frame n+1, channel 0 Frame n+1, channel 0 Write data from S23-S0 frame n, last channel Read data for S23-S0 frame n+1, channel 1 Finished reading last channel of frame n RBC WBC Finished writing last channel of frame n R/W1 R/W2 STROBE Figure 12 - Modes 1, 2, 3 Read/Write Timing 2-159 MT90210 Preliminary Information 2M ts Frame n, channel 31 8M ts ch 124 ch 125 ch 126 Frame n+1, channel 0 ch 127 ch 0 ch 1 ch 2 ch 3 3 channel delay for 8 Mb/s rate Finished reading last channel of 8Mb/s and 4th quarter of last channel of 2 Mb/s of one complete frame(125 us) RBC WBC R8 7 R2 1d W8 127 W2 31d R8 6 R2 1c W8 126 W2 31c R8 5 R2 1b W8 125 W2 31b R8 4 R2 1a W8 124 W2 31a R8 3 R2 0d W8 123 W2 30d R8 2 R2 0c W8 122 W2 30c R8 1 R2 0b W8 121 W2 30b R8 0 R2 0a R8 127 R2 31d W8 120 W2 30a P7:P0 "a" denotes data for S0-S3 "b" denotes data for S4-S7 "c" denotes data for S8-S11 "d" denotes data for S12-S15 Finished writing last channel of 8 Mb/s and 4th quarter of last channel of 2 Mb/s R/W1 R/W2 STROBE Figure 13 - Mode 4 and Mode 5 Read/Write Timing Mode TX/RX Memory Address Location Formula for Block 0 Memory Address Location Formula for Block 1 1 TX 24C + S 24C + S + 800h 1 RX 24C + S + 0400h 24C + S + C00h 2 TX 24C + S 24C + S + 1000h 2 RX 24C + S + 0800h 24C + S + 1800h 3 TX 12C + S 12C + S + 1000h 3 RX 12C + S + 0800h 12C + S + 1800h 4 or 5 (@ 2M) TX 16C + S 16C + S + 1000h 4 or 5 (@ 2M) RX 16C + S + 0800h 16C + S + 1800h 4 or 5 (@ 8 M) TX 8C + (S-16) + 0400h 8C + (S-16) + 1400h 4 or 5 (@ 8M) RX 8C + (S-16) + 0C00h 8C + (S-16) + 1C00h Table 5 - Memory Address Location Formulae for all modes of operation C = channel number, S = stream number 2-160 MT90210 Preliminary Information Absolute Maximum Ratings* - Voltages are with respect to VSS unless otherwise stated. Parameter Symbol Min VDD Max Units 6 V VDD+0.3 V 1 DC Power Supply Voltage VDD to VSS 2 Voltage on any pin (other than supply pins) Vi 3 Current at any pin (except VDD and VSS) IO 40 mA 4 Package Power Dissipation PD 2 mW VSS+0.3 *Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated Characteristics Sym Min Typ Max Units 1 Operating Temperature TOP -40 25 +85 °C 2 Power Supply Voltage VDD 4.75 5.0 5.25 V Test Conditions DC Electrical Characteristics† Characteristics Sym Min Typ* Max Units 15 100 mA Test Conditions 1 Supply Current IDD 2 Input High Voltage, all inputs VIH 2.0 VDD V 3 Input Low Voltage, all inputs VIL 0 0.8 V 4 Specific Output High Sourcing Current IOH 12 mA VOH=2.4V 5 Specific Output Low Sinking Current IOL 12 mA VOL=0.4V 6 Leakage Current S0-S23 All other pins ILK Pin Capacitance CP 7 µA 200 5 10 pF † DC Electrical Characteristics are over recommended operating conditions unless otherwise stated. * Typical figures are at 25°C and are for design aid only. 2-161 MT90210 Preliminary Information AC Electrical Characteristics†-The following table specifies voltage reference levels used in both input timing and output timing specifications. The setup/hold and propagation delays are based on a single reference level which is 1.5V for TTL(VTT) and 0.5*VDD for CMOS (VCT). Voltage Reference Voltage Value when Connected to TTL Voltage Value when Connected to CMOS Units VH 2.4 0.9*VDD V VHM 2.0 0.7*VDD V VLM 0.8 0.3*VDD V VL 0.4 0.1*VDD V VTT 1.5 not applicable V VCT not applicable 0.5*VDD V t VH VH VTT VTT VL t Figure 14 - Input Pulse Width VH VHM VLM VL t t Figure 15 - Input Rise and Fall Times VH VTT VL Clock t t VH Input Data VTT VL Figure 16 - Setup Time and Hold Time 2-162 VL MT90210 Preliminary Information VH clock VTT VL t drive to drive output VTT t drive to hiz-low output t drive to hiz-high output Figure 17 - Output Delays tfrw F0i tfrs tfrh tclk tT tclkl SCLK 4.096 MHz (Mode 1) 8.192 MHz (Mode 2) 16.384 MHz (Mode 3) tclkh tstis S0-23 bit 0, last ch† (inputs) S0-23 (outputs) tstih bit 7, ch.0 tstod bit 0, last ch† bit 7, ch.0 †Mode 1, last channel = 31 Mode 2, last channel = 63 Mode 3, last channel = 127 Figure 18 - Serial Port Timing for Modes 1, 2, 3 2-163 MT90210 Preliminary Information thfrw F0i (8kHz) tfrs tfrh tstis S0-15 (2.048 Mb/s) (inputs) bit 0, ch. 31 bit 7, ch. 0 tstod S0-15 (2.048 Mb/s) (outputs) bit 0, ch. 31 HC4 (4.096 MHz) thclkl bit 7, ch. 0 thclk tT thclkh tch tclkl (16.384 MHz) tstih tclkh S16-S23 (8.192 Mb/s) (inputs) S16-S23 (8.192 Mb/s) (outputs) tstih tclk tstis bit 7, ch.127 bit 0, ch0 bit 1, ch.0 tstod bit 1, ch. 127 bit 0, ch. 127 bit 7, ch. 0 bit 1, ch. 0 Figure 19 - Serial Port Timing for Modes 4 and 5 bit cell boundary SCLK, C16+ tza S0-23 taz S0-23 Figure 20 - Serial Port Tri-state Timing 2-164 MT90210 Preliminary Information AC Electrical Characteristics† 1 2 3 Characteristics Sym SCLK, C16 Period 2.048 Mb/s (4.096 MHz) 4.096 Mb/s (8.192 MHz) 8.192 Mb/s (16.384 MHz) tclk SCLK, C16 Pulse Width High 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s tclkh SCLK, C16 Pulse Width Low 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s tclkl Min Typ* Max Units 244 122 60 ns ns ns 122 60 30 ns ns ns 122 60 30 ns ns ns 4 SCLK rise/fall time tT 5 5 HC4 hold related to C16 tch 3 ns 6 HC4 period thclk 244 ns 7 HC4 pulse low thclkl 122 ns 8 HC4 pulse high thclkh 122 ns 9 Frame Pulse Setup (ST-BUS) ns tfrs 0 ns 10 Frame Pulse Hold (ST-BUS) tfrh 10 ns 11 Frame pulse width in modes 1,2,3 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s tfrw 12 Frame pulse width in modes 4,5 thfrw 13 S0-23 delay from active to High-Z 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s taz 14 S0-23 delay from High-Z to active 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s tza 15 S0-23 Delay (high and low) from CLK falling (ST-BUS mode) 2.048 Mb/s, 4.096 Mb/s, 8.192 Mb/s tstod 16 S0-23 Set-up Time before CLK rising (ST-BUS mode) tstis 17 S0-23 Hold Time from CLK rising (ST-BUS mode) tstih Test Conditions 244 122 60 ns ns ns 244 ns 30 ns RL=1K, CL=200pF 30 ns RL=1K, CL=200pF 30 ns RL=1K, CL=200pF 0 ns 10 18 CKout output delay from SCLK tdpll 5 † DC Electrical Characteristics are over recommended operating conditions unless otherwise stated. * Typical figures are at 25°C and are for design aid only. ns ns 2-165 MT90210 CKout (mode 3/4/5) Preliminary Information tdpll SCLK C16+ C16 - Figure 21 - PLL Timing SCLK or C16+, C16CKout (16.384 MHz, mode 1) (32.768 MHz, mode 2/3/4/5) A0-A12 tad X Y Z RDin input thd tst P0-P7 (Read/ Write) X(rd) Z(rd) Y(rd) tstb Strobe toes OEser input toeh Valid Valid Note: R/W1 output signal is HIGH and R/W2 output signal is LOW during read cycles. Figure 22 - Parallel Port Data Read Cycle 2-166 MT90210 Preliminary Information SCLK or C16+, C16 CKout (16.384 MHz, mode 1) (32.768 MHz, mode 2/3/4/5) tad A0-A12 X Y tr/wd Z S tah R/W1 tdod tpwe P0-P7 (Read/ Write) WR(x) WR(y) WR(z) tstb Strobe tpwe Note: R/W2 output signal is HIGH during write cycles. Figure 23- Parallel Port Data Write Cycle AC Electrical Characteristics† Characteristics Sym Min Typ* Max Units 1 Address Output Delay from Clock tad 15 ns 2 Output Delay on R/W1 and Strobe tr/wd, tstb 9.5 ns 3 Pulse Width Low - R/W1 and Strobe modes 2, 3, 4 & 5 mode 1 tpwe 4 Internal Data Output Delay from Clock Falling tdod 5 Address Hold from Write Inactive tah 2.25 ns 6 Input Data & OE setup times tst, toes 0 ns 7 Input Data & OE hold times thd, toeh 5 ns output load 50pF ns pulse width low on PCLK for 30 ns ns output load 50 pF 13.5 30 10 Test Conditions † DC Electrical Characteristics are over recommended operating conditions unless otherwise stated. * Typical figures are at 25°C and are for design aid only. 2-167 MT90210 2-168 Preliminary Information Package Outlines L1 A A2 A1 L e b D D1 E1 Notes: 1) Not to scale 2) Top dimensions in inches 3) The governing controlling dimensions are in millimeters for design purposes ( ) E Index WARNING: This package diagram does not apply to the MT90810AK 100 Pin Package. Please refer to the data sheet for exact dimensions. Pin 1 Metric Quad Flat Pack - L Suffix 44-Pin 64-Pin 100-Pin 128-Pin Dim Min Max Min Max Min Max Min Max A - 0.096 (2.45) - 0.134 (3.40) - 0.134 (3.40) - 0.154 (3.85) A1 0.01 (0.25) - 0.01 (0.25) - 0.01 (0.25) - 0.00 0.01 (0.25) A2 0.077 (1.95) 0.083 (2.10) 0.1 (2.55) 0.12 (3.05) 0.1 (2.55) 0.12 (3.05) 0.125 (3.17) 0.144 (3.60) b 0.01 (0.30) 0.018 (0.45) 0.013 (0.35) 0.02 (0.50) 0.009 (0.22) 0.015 (0.38) 0.019 (0.30) 0.018 (0.45) D 0.547 BSC (13.90 BSC) 0.941 BSC (23.90 BSC) 0.941 BSC (23.90 BSC) 1.23 BSC (31.2 BSC) D1 0.394 BSC (10.00 BSC) 0.787 BSC (20.00 BSC) 0.787 BSC (20.00 BSC) 1.102 BSC (28.00 BSC) E 0.547 BSC (13.90 BSC) 0.705 BSC (17.90 BSC) 0.705 BSC (17.90 BSC) 1.23 BSC (31.2 BSC) E1 0.394 BSC (10.00 BSC) 0.551 BSC (14.00 BSC) 0.551 BSC (14.00 BSC) 1.102 BSC (28.00 BSC) e 0.031 BSC (0.80 BSC) 0.039 BSC (1.0 BSC) 0.256 BSC (0.65 BSC) 0.031 BSC (0.80 BSC) L L1 0.029 (0.73) 0.04 (1.03) 0.077 REF (1.95 REF) 0.029 (0.73) 0.04 (1.03) 0.077 REF (1.95 REF) 0.029 (0.73) 0.04 (1.03) 0.077 REF (1.95 REF) NOTE: Governing controlling dimensions in parenthesis ( ) are in millimeters. 0.029 (0.73) 0.04 (1.03) 0.063 REF (1.60 REF) Package Outlines 160-Pin 208-Pin 240-Pin Dim A Min Max - 0.154 (3.92) A1 Min Max Min Max .161 (4.10) - 0.161 (4.10) 0.01 (0.25) 0.01 (0.25) 0.02 (0.50) 0.01 (0.25) 0.02 (0.50) A2 0.125 (3.17) 0.144 (3.67) .126 (3.20) .142 (3.60) 0.126 (3.2) 0.142 (3.60) b 0.009 (0.22) 0.015 (0.38) .007 (0.17) .011 (0.27) 0.007 (0.17) 0.010 (0.27) D 1.23 BSC (31.2 BSC) 1.204 (30.6) 1.360 BSC (34.6 BSC) D1 1.102 BSC (28.00 BSC) 1.102 (28.00) 1.26 BSC (32.00 BSC) E 1.23 BSC (31.2 BSC) 1.204 BSC (30.6 BSC) 1.360 BSC (34.6 BSC) E1 1.102 BSC (28.00 BSC) 1.102 BSC (28.00 BSC) 1.26 BSC (32.00 BSC) e 0.025 BSC (0.65 BSC) 0.020 BSC (0.50 BSC) 0.0197 BSC (0.50 BSC) L L1 0.029 (0.73) 0.04 (1.03) 0.063 REF (1.60 REF) 0.018 (0.45) 0.029 (0.75) 0.051 REF (1.30 REF) NOTE: Governing controlling dimensions in parenthesis ( ) are in millimeters. 0.018 (0.45) 0.029 (0.75) 0.051 REF (1.30 REF) http://www.mitelsemi.com World Headquarters - Canada Tel: +1 (613) 592 2122 Fax: +1 (613) 592 6909 North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Asia/Pacific Tel: +65 333 6193 Fax: +65 333 6192 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. 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