MITEL MT90810

CMOS MT90810
Flexible MVIP Interface Circuit
Preliminary Information

Features
ISSUE 2


•
MVIP and ST-BUS compliant
•
MVIP Enhanced Switching with 384x384
channel capacity (256 MVIP channels; 128
local channels)
October 1994
Ordering Information
MT90810AK
100 Pin PQFP
0 °C to +70 °C
•
On-chip PLL for MVIP master/slave operation
•
Local output clocks of 2.048,4.096,8.192MHz
with programmable polarity
Description
•
Local serial interface is programmable to
2.048, 4.096, or 8.192Mb/s with associated
clock outputs
•
Additional control output stream
•
Per-channel message mode
•
Two independently programmable groups of up
to 12 framing signals each
•
Motorola non-multiplexed or Intel multiplexed/
non-multiplexed microprocessor interface
Mitel’s MT90810 is a Flexible MVIP Interface Circuit
(FMIC). The MVIP (Multi-Vendor Integration
Protocol) compliant device provides a complete
MVIP compliant interface between the MVIP Bus and
a wide variety of processors, telephony interfaces
and other circuits. A built-in digital time-slot switch
provides MVIP enhanced switching between the full
MVIP Bus and any combination of up to 128 full
duplex local channels of 64kbps each. An 8 bit
microprocessor port allows real-time control of
switching and programming of device configuration.
On-board clock circuitry, including both analog and
digital phase-locked loops, supports all MVIP clock
modes. The local interface supports PCM rates of
2.048, 4.096 and 8.192Mb/s, as well as parallel DMA
through the microprocessor port.
•
Applications
•
Medium size digital switch matrices
•
MVIP interface functions
•
Serial bus control and monitoring
•
Centralized voice processing systems
•
Voice/Data multiplexer
EX_8KA
EX_8KB
X2
X1/CLKIN PLL_LO
PLL_LI
FRAME
SEC8K
C4b
C2o
F0b
Timing and Clock Control
(Oscillator and Analog & Digital PLLs)
CLK2
CLK4
CLK8
RESET
Enhanced Switch
DSo[0:7]
DSi[0:7]
LDO[0:3]
LDI[0:3]
TCK
TMS
TDI
TDO
CSTo
Data Memory
S-P/
P-S
Programmable
Framing Signals
Connection Memory
JTAG
Microprocessor Interface
AD[0:7] A[0:1] ALE
WR/
R/W
RD/
DS
CS
FGA[0:11]
FGB[0:11]
ERR
RDY/ DREQ[0:1] DACK[0:1]
DTACK
Figure 1 - Functional Block Diagram
2-145
MT90810
54
52
86
LDI1
88
EX8_KB
VSS
92
FRAME
94
44
AD6
AD5
42
AD4
40
VDD
FGB6
38
AD3
36
AD2
AD1
96
AD0
34
A1
32
FGA6
A0
98
Figure 2 - Pin Connections
30
RDY/[DTACK]
FGB5
ALE
28
CS
26
RD/[DS]
VCO_VDD
WR/[R/W]
24
PLL_LI
RESET
FGA5
22
PLL_LO
20
VCO_VSS
18
X2
16
X1/CLKIN
14
VDD
VSS
TMS
12
TDO
TCK
TDI
10
FGB3
FGB2
8
FGB1
6
FGA4
FGB0
CSTo
4
FGA3
FGA1
FGA2
100 2
FGB4
FGB11
2-146
FGA7
VSS
100 PIN PQFP
CLK8
FGA0
46
90
EX8_KA
CLK4
CLK2
DACK1
DACK0
AD7
LDI2
FGA11
48
84
VDD
LDI0
DREQ1
DREQ0
LDO3
LDI3
50
82
LDO2
FGB10
FGB7
SEC8K
VSS
56
C2o
58
F0b
FGA8
C4b
60
DSo0
62
DSi0
DSo1
64
FGB8
DSi1
DSo2
66
DSi2
68
VDD
DSo3
VSS
70
DSi3
72
FGA9
DSi4
DSo4
74
DSo5
76
DSi5
DSo6
78
FGB9
DSi6
80
DSo7
DSi7
FGA10
LDO1
LDO0
VSS
Preliminary Information
ERR
MT90810
Preliminary Information
Pin Description
Pin #
Name
Description
58, 60, 63, 67, 70,
72, 74, 77
DSo[0:7]
MVIP DSo Streams (Bidirectional CMOS). 2.048Mb/s serial data
streams conforming to ST-BUS serial data stream specifications.
59, 61, 64, 68, 71,
73, 75, 78
DSi[0:7]
MVIP DSi Streams (Bidirectional CMOS). 2.048Mb/s serial data
streams conforming to ST-BUS serial data stream specifications.
80, 82, 83, 85
LDO[0:3]
Local Output Serial Streams (Output). Serial data streams
programmable to 2.048, 4.096 or 8.192Mb/s data rates.
87, 88, 89, 90
LDI[0:3]
Local Input Serial Streams (TTL Input). Serial data streams
programmable to 2.048, 4.096 or 8.192 Mb/s data rates.
4
CSTo
Control ST-BUS Output (Output). This is a 1.024Mb/s output. The
state of each bit in this stream is determined by the CSTo bit in
connection memory high.
55
F0b
MVIP F0 signal (CMOS Input/Output). ST-BUS 8kHz framing signal
56
C4b
MVIP C4 signal (CMOS Input/Output). ST-BUS 4.096MHz clock
54
C2o
MVIP C2 signal (Output). ST-BUS 2.048MHz clock. This pin is
automatically set to high impedance when it is not driven.
53
SEC8K
MVIP SEC8K signal (CMOS Input/Output). A secondary 8kHz signal
used either as an input source to the on-chip digital PLL or as an
output to the MVIP bus.
91
EX_8KA
External 8kHz input A (TTL Input).
92
EX_8KB
External 8kHz input B (TTL Input).
94
FRAME
Local Frame Output Signal (Output). This 8kHz framing signal has a
duty cycle and period equal to the MVIP F0 signal.
95
CLK8
8MHz Local Output Clock (Output). This is a 8MHz clock.
97
CLK4
4MHz Local Output Clock (Output). This 4MHz clock has a duty
cycle and period equal to the MVIP C4 signal.
98
CLK2
2MHz Local Output Clock (Output). This 2MHz clock has a duty
cycle and period equal to the MVIP C2 signal.
100, 1, 2, 3, 5, 20,
33, 46, 57, 69, 81,
96
FGA[0:11]
Frame Group A framing signals (Output). Programmable framing
signals. The frame group outputs are determined by mode bits in the
frame register to be either programmed outputs, output drive enables
for DSo, or output framing pulses for use with local serial data
streams.
6, 7, 8, 9, 14, 28,
39, 51, 62, 76, 84,
99
FGB[0:11]
Frame Group B framing signals (Output). Programmable framing
signals. The frame group outputs are determined by mode bits in the
frame register to be either programmed outputs, output drive enables
for DSi, or output framing pulses for use with local serial data streams.
19
RESET
Chip Reset (Schmitt Input). This active low reset clears all internal
registers, connection memory and data memory
35, 36, 37, 38, 42,
43, 44, 45
AD[0:7]
Microprocessor Address/Data Bus (Bidirectional TTL).
Microprocessor access to internal registers, connection and data
memories.
In non-multiplexed mode: data bus.
In multiplexed mode: multiplexed address and data bus.
2-147
MT90810
Preliminary Information
Pin Description
Pin #
32, 34
Name
A[0:1]
Description
Microprocessor Address (TTL Input).
In non-multiplexed mode: address to FMIC internal registers
In multiplexed mode: unused (leave unconnected).
29
ALE
Microprocessor Address Latch Enable (TTL Input). Selects the
microprocessor mode.
In Intel multiplexed mode, the falling edge of this signal is used to
sample the address.
27
CS
Microprocessor Bus Chip Select (TTL Input). This active low input
enables microprocessor access to connection and data memory and
internal registers.
26
RD/ [DS]
Read/Data Strobe (TTL Input).
In Intel mode (RD), this active low input configures the data bus lines
as output.
In Motorola mode (DS), this active low input operates with CS to
enable read and write operation.
25
WR/ [R/W]
Write\ Read/Write Strobe (TTL Input).
In Intel mode (WR), this active low input configures the data bus lines
as inputs.
In Motorola mode (R/W), this input controls the direction of the data
bus D[0:7] during a microprocessor access.
30
RDY [DTACK]
Ready/Data Acknowledge (Open Drain Output).
In Intel mode (RDY), this output acts as IOCHRDY. A 10K pull up is
required.
In Motorola mode (DTACK), this active low output indicates a
successful data bus transfer. A 10K pull up is required.
31
ERR
Error Status (Output). This pin is asserted high if either a clock error
(loss of C4b clock), DMA overrun condition or PLL unlock occurs.
49, 50
DREQ[0:1]
DMA Request (Output). When DMA operations on the device are
enabled, this pin requests transfers for DMA reads/writes from/to the
device.
47, 48
DACK[0:1]
DMA Acknowledge (TTL Input). When DMA operations on the device
are enabled, this pin receives acknowledgement for DMA reads/writes
from/to the device.
10
TCK
JTAG Input Clock (TTL Input). Maximum recommended clock rate is
16 MHz. If not used, this pin should be left unconnected.
11
TDI
JTAG Serial Input Data (TTL Input). If not used, this pin should be left
unconnected.
2-148
MT90810
Preliminary Information
Pin Description
Pin #
Name
Description
12
TDO
JTAG Serial Output Data (Output). If not used, this pin should be left
unconnected.
13
TMS
JTAG Mode Control Input (TTL Input). If not used, this pin should be
left unconnected.
17
X1/CLKIN
18
X2
22
PLL_LO
PLL Loop Filter Output. (Output 6mA drive).
23
PLL_LI
PLL Loop Filter Input. (1 µA Low level/High level Input current).
21
VCO_VSS
Ground for On-chip VCO.
24
VCO_VDD
+5 Volt Power Supply for On-chip VCO.
Clock Input Pin/ Crystal Oscillator Pin1.
Crystal Oscillator Pin 2 (Input). If X1 is clock input, this pin should be
left unconnected.
15, 40, 65, 86
VDD[0:3]
+5 Volt Power Supply.
16, 41, 52, 66,
79, 93
VSS[0:5]
Ground.
Device Overview
Mitel’s MT90810 is a MVIP compliant device. It
provides a complete, cost effective, MVIP compliant
interface between the MVIP Bus and a wide variety
of processors, telephony interfaces and other
circuits. The FMIC supports 384 full duplex, time
division multiplexed (TDM), channels. These
channels are divided into 256 full duplex MVIP
channels and 128 full duplex local channels. The
sample rate for each channel is 8kHz and the width
of each channel is 8 bits for a total data rate of
64kbits/s per channel.
The FMIC’s internal clock circuitry includes both an
analog and a digital PLL and supports all MVIP clock
modes. The device can be configured as a timing
master whereby an external 16.384MHz crystal or
4.096, 8.192 or 16.384MHz external clock source is
used to generate MVIP clock signals. The device can
also operate as a slave to the MVIP bus,
synchronizing its master clock to the MVIP 4MHz
bus clock.
The device’s local serial interface supports PCM
rates of 2.048, 4.096 and 8.192Mb/s, per channel
message mode, an additional control stream, as well
as parallel DMA through the microprocessor port.
Furthermore, the FMIC’s programmable group of
output framing signals and local output clocks may
be used to provide the appropriate frame and clock
pulses to drive other local serial buses such as GCI.
A microprocessor interface permits reading and
writing of the data memory, connection memory and
all internal control registers. The Connection and
Data memory can be read and updated while the
MVIP bus is active, that is, connections can be made
without interrupting bus activities.
Functional Description
Switching
The FMIC provides for switching of data from any
input channel to any output channel. This is
accomplished by buffering a single sample of each
channel in an on-chip 384 byte static RAM. Samples
are written into this data RAM in a fixed order and
read out in an order determined by the programming
of the connection memory. An input shift register and
holding latch for each input stream make up the
serial to parallel conversion blocks on the input of
the FMIC and an output holding register an shift
register make up the parallel to serial conversion
blocks on the output of the FMIC.
Data Memory
Data memory is a 384 byte static RAM block which
provides one sample of buffering for each of the 384
channels. An input shift register and holding latch for
each input stream make up the serial to parallel
conversion blocks on the input. Each input channel is
mapped to a unique location in the RAM, as shown
Table 18 - “Data Memory Mapping”.
Data memory can be read and written by the
microprocessor (See “Software Control” for further
details). Note that writing to data memory may be
futile since the contents will be overwritten by
incoming data on the serial input streams.
2-149
MT90810
Preliminary Information
DC=0 for stream 0 channel 1
DSi0
O/P
0
1
2
3
.....
29
DSo0
I/P
I/P
30
31
FMIC
0
1
2
3
.....
O/P
29
30
31
DC=1 for stream 0 channel 29
Figure 3 - Per-channel Direction Control
Connection Memory
Connection and Message Modes
Connection memory is comprised of a static RAM
block 384 locations by 12 bits. Each location in
connection memory corresponds to one of the 384
output channels. The mapping of memory location to
output channel is the same as the mapping of input
channel to data memory location and is shown in
Table 19 - “Connection Memory Mapping”.
In connection mode, the connection memory low
byte and the least significant bit of connection
memory high form a 9 bit address to point to in data
memory. The location pointed to specifies which
source/input channel to connect to the respective
output channel and stream. The same source
channel can be routed to various output channels,
thus providing broadcast facility within the switch.
The lower 8 bits of connection memory form
connection memory low byte as shown in Figure 10 “Connection Memory Low Byte”. The bits are defined
in Table 20, “Connection Memory Low Bits”.
The upper 4 bits of connection memory form
connection memory high (refer to Figure 11 “Connection memory high byte” ). Connection
memory low byte, together with the least significant
bit of connection memory high form an address to
point to in data memory. The location pointed to in
data memory provides the data for a given output
channel. The remaining three bits in connection
memory high are control bits. These bits perform
slightly different functions for MVIP and local
channels. The control bits in connection memory
high for MVIP streams enable/disable output drivers,
specify message or connection mode for individual
output channels, and determine the direction of the
DSi/DSo channel pair (see Table 21 - “Connection
Memory High Bits for MVIP channels” for further
details). The control bits in connection memory high
for local streams enable/disable DMA transfer,
specify message or connection mode for individual
output channels, and control CSTo timing (see Table
22 - “Connection Memory High Bits for Local
channels” for further details).
Connection memory can be read and written by the
microprocessor (see “Software Control” for further
details). When writing to connection memory, it is
necessary to first write the low bits and then the high
bits. The low bits are held in a temporary register
until the high bits are written. The complete write of
all 12 bits (to connection memory) is only performed
when the high bits are being written.
2-150
In message mode, the connection memory low byte
is sent directly out the corresponding output channel
and stream. The least significant bit of connection
memory high is not used.
Direction Control Bit
The direction control (DC) bit in connection memory
high determines the direction of the associated DSiDSo channel pair. If the DSi or DSo channel is
programmed as an input, the corresponding DSo or
DSi channel will automatically be configured as an
output. Thus, there are always 256 MVIP input and
256 MVIP output channels or 256 full duplex MVIP
channels on the MVIP bus. Figure 3 - “Per channel
direction control” illustrates the use of DC bit for
direction control on stream 0 channel 1 and channel
29. When DC bit is set, DSo channel is output from
the FMIC and DSi is input to the FMIC. When DC bit
is cleared, the channel directions are reversed.
Timing and Clock Control
The FMIC clock control circuitry contains an on-chip
analog PLL (with external loop filter) which is
designed to phase lock to a 4.096MHz clock. The onchip VCO runs at eight times this rate yielding a
32MHz clock which is divided by two. The resulting
16.384MHz is used as the internal master clock of
the FMIC.
The input to the analog PLL can be selected from
among several different sources including, the MVIP
C4 clock which is used as the internal master clock
of the FMIC.
The on-chip digital PLL generates a 4.096MHz clock
which is phase locked to an externally generated
MT90810
Preliminary Information
SEC8K
1, 5
PLL_MODE
2, 6
EX_8KA
EX_8KB
EX_8KA
Digital
PLL
3, 7
16MHz
C4b
0
X2
External
16MHz Crystal
X1
XCLK_SEL
0
2
1
div 2
External 8kHz
F0b
SEC8K
2
Jittery 4.096MHz
60ns peak jitter
PLL_MODE
div 4
1
(sampler)
4
0
SEL_S8K
EX_8KB
FRAME
EN_SEC8K
Analog PLL
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA PLL_LO
A
AA
4.096MHz
AA
up/ AA
Phase
AA
A
AA
A
Comparator down AA
AA
AA
AA
external
A
AA
AA
AA
loop
AA
A
AA
filter
A
AA
AA
AA
16MHz div VCO
AA
A
AA
div
4
by 2 @32MHz
A
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAA
AA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAPLL_LI
8kHz
FRAME
F0b
FMIC
CLK8
state
C4b
machine
CLK4
C2o
CLK2
Figure 4 - Clock Control Functional Block Diagram
8kHz clock. The digital PLL state machine is clocked
at 16.384MHz. The digital PLL maintains lock by
occasionally dropping or repeating a 16.384MHz
clock period on the generated 4.096MHz clock.
Consequently, the 4.096MHz clock has jitter equal to
about 60ns. If the output of the digital PLL is chosen
as the input to the analog PLL, a slow loop filter with
a time constant greater than several 8kHz frames will
smooth out the jitter.
The clock oscillator pins X1 and X2 can be used with
an external 16.384MHz crystal or pin X1 can be used
directly as a clock input with X2 left unconnected.
When X1 is used as a clock input, the frequency of
the clock can be selected to be either 16.384MHz or
8.192MHz or 4.096MHz by changing the XCLK_SEL
bits in the CLK_CNTL register.
The overall FMIC state machine from which all timing
is derived, is clocked by the 16.384MHz output of the
analog PLL, the device’s master clock. The state
machine controls all timing in the FMIC and has a
period equal to one MVIP frame (8kHz). This state
machine can either free run or synchronize to an
8kHz source such as the MVIP F0 signal or an
external 8kHz reference.
Refer to Figure 4 - “Clock Control Functional Block
Diagram” for further details.
The operation of the PLLs and the state machine is
controlled by the clock control register as described
in Figure 6 - “Clock Control (CLK_CNTRL) Register”
and Tables 8 to 10. The clock circuitry (PLLs and
state machine) operates in eight different modes.
They are:
FMIC as Timing Master (Mode 0)
The FMIC is configured as the timing master
(CLK_CNTRL register cleared, PLL mode 0
selected) after reset. The external 16.384MHz input
is divided by four and used as the input to the analog
PLL so the internal master clock is phase locked to
the 16.384MHz oscillator. The FMIC state machine is
free-running and does not synchronize to any
external 8kHz source.
In this mode, the XLCK_SEL bits of the clock control
register can be programmed to accommodate an
8.192MHz or 4.096MHz external clock instead of the
default 16.384MHz.
The FMIC becomes MVIP master when MVIP_MST
bit is set in the Control/Status register. This mode
can be used when the FMIC chip is to become timing
master in a system which has no digital network
connections (T1 or E1).
FMIC as MVIP Slave (Mode 4)
When this mode is selected, MVIP C4 clock is
selected as the input to the analog PLL. The FMIC
internal master clock is then synchronized to the
MVIP bus timing. The FMIC state machine is also
synchronized to the MVIP F0 framing signal.
The MVIP_MST bit in the Control/Status register
should never be set when the device is in mode 4 as
the FMIC is entirely slave to the MVIP bus timing.
2-151
MT90810
Preliminary Information
0
Jitter
Attenuation
(dB)
0
- 2
2
- 2
- 4
4
- 4
- 6
6
- 6
8
- 8
- 8
- 1 0
10
- 1 0
- 1 2
12
- 1 2
14
- 1 4
- 1 4
16
- 1 6
- 1 6
0
1
1
10
2
100
3
1K
4
10K
5
100K
6
Frequency, log scale (Hz)
S e r ie s
1
Figure 5 - Jitter Transfer Function of the Analog PLL
FMIC as MVIP Master (Mode 1,2,3)
In modes 1 through 3, the output of the device’s
digital PLL is selected as the input to the analog PLL.
The source to the digital PLL is selected as either
SEC8K, EX_8KA or EX_8KB depending on the
particular mode (1, 2 or 3) chosen.
In these modes, the FMIC state machine is not
synchronized to the external 8kHz input selected,
that is, the state machine output 8kHz FRAME and
F0b signals may not be phase aligned with the
external 8kHz input but will always be frequency
locked.
In modes 1, 2 and 3, the external clock X1 must be
16.384MHz. This is required for proper operation of
the digital PLL.
The FMIC becomes MVIP master when MVIP_MST
bit is set in the Control/Status register.
FMIC as MVIP Master (Mode 5,6,7)
In modes 5 through 7, the output of the device’s
digital PLL is selected as the input to the analog PLL.
The source to the digital PLL is selected as either
SEC8K, EX_8KA or EX_8KB depending on the
particular mode (5, 6 or 7) chosen.
In these modes, the FMIC state machine is
synchronized to the external 8kHz input selected,
that is, the state machine output 8kHz FRAME and
F0b signals are phase aligned with the external 8kHz
input as well as frequency locked. Here lies the
difference between these modes (5, 6 and 7) and the
above mentioned modes (1, 2 and 3). In these
modes, the external 8kHz input signal is used to
synchronize the FMIC state machine.
2-152
In modes 5,6 and 7, the external clock X1 must be
16.384MHz. This is required for proper operation of
the digital PLL.
The FMIC becomes MVIP master when MVIP_MST
bit is set in the Control/Status register.
PLL Jitter Performance
To measure the intrinsic jitter of the analog PLL, the
FMIC is set to slave mode, slave to a clean MVIP C4
clock (no jitter). A resulting jitter of 0.004UI p-p is
measured on the C2o clock.
The jitter transfer function of the analog PLL, which
is the ratio of the output jitter to the input jitter, is
shown in “Figure 5 - Jitter Transfer Function of the
Analog PLL” . The measurements are made with a
controlled sinusoidal jitter modulating the MVIP C4
clock.
To measure the intrinsic jitter of the two PLLs
combined, the FMIC is set to master mode, slave to
a clean external 8kHz clock SEC8K (no jitter). A
resulting jitter of 0.206UI p-p is measured on the C2o
clock.
Jitter transfer function of the digital PLL and analog
PLL combination is determined primarily by the
digital PLL. The digital PLL is essentially a digital
sampler which samples on the nearest rising or
falling edge of its 16MHz clock and therefore has a
60ns jitter on the output.
Please note that the digital PLL and analog PLL
combination may not meet some international
standards for jitter performance. In cases where
strict idle jitter specifications must be met, an
external custom PLL may be required and the
internal analog PLL should be disabled (refer to PLL
Diagnostic section for further details).
MT90810
Preliminary Information
Local Output Clock Control
Programmable Framing Signals
The FMIC provides four output clocks which are
always driven off of the device. The FRAME output
clock has a duty cycle and period equal to the MVIP
F0 signal. The CLK2 and CLK4 output clocks are
identical to the MVIP C2 and C4 clocks, respectively.
The CLK8 output provides a 8.192MHz clock. The
frame pulse and output clocks may be used to
provide framing and clocking signals to serial
interfaces other than ST-BUS, such as, GCI bus.
Timing diagrams and parameters are provided in
Figures 19 and 20 along with the associated table.
The FMIC provides two groups of independently
programmable output framing signals:
The local output clock control register is defined in
Table 11 - “Local Clock Control (LOC_CLK)
Register”. The register allows the user to program
the polarity of the four local output clocks. In
addition, the register contains four read-only bits
which indicate the logic levels on EX_8KA, EX_8KB,
DACK0 and DACK1 input pins of the device.
Local Serial Interface
The local serial interface is implemented on 4 input
pins LDI[0:3] and four output pins LDO[0:3]. It can be
programmed in one of four different configurations by
setting the appropriate bits in the SER_MODE
register (refer to Figure 7 - “Serial Mode
(SER_MODE) Register” ).
In serial configuration one, the data rate is set to
2Mb/s. Each input stream is associated with a serial
input pin and each serial output stream is associated
with a serial output pin. There are 32 channels per
pin.
In serial configuration two, the data rate is set to
4Mb/s. Local streams 0 and 1 are multiplexed onto
input and output pins LDI[0] and LDO[0] and streams
2 and 3 are multiplexed onto input and output pins
LDI[2] and LDO[2]. There are 64 channels per pin
and the streams are multiplexed onto the pins as
shown in Table 12 - “SER_CNFG bits (control
configuration of local serial streams)” .
In serial configuration three, the data rate is set to
8Mb/s. All four local streams are multiplexed onto
pins LDI[0] and LDO[0]. There are 128 channels per
pin and the streams are multiplexed onto the pins as
shown in Table 12 - “SER_CNFG bits (control
configuration of local serial streams)” .
In serial configuration four, the data rate is set to
2Mb/s for streams 0 and 1 and 4Mb/s for streams 2
and 3. Streams 0 and 1 are associated with serial
pins LDI/O[0] and LDI/O[1], respectively. Streams 2
and 3 are multiplexed onto pin LDI[2] and LDO[2].
The streams are multiplexed onto the pins as shown
in Table 12 - “SER_CNFG bits (control configuration
of local serial streams)” .
FGA[0:11] group A output framing signals are
programmed
by
frame
start
register
A
(FRMA_STRT) and frame mode register A
(FRMA_MODE). FGB[0:11] group B output framing
signals are programmed by frame start register B
(FRMB_STRT) and frame mode register B
(FRMB_MODE).
The framing signals may be used to drive serial
buses interfaces other than ST-BUS.
The functional characteristics of a group of framing
output signals is controlled by MODE bits in the
frame mode register. Table 13 - “Frame Group Mode
bits” defines the various modes.
In mode 0, the frame group output depends on the
status of bits in the frame start and frame mode
registers. The values of the bits in frame start
register x (x is either A for group A or B for group B)
are driven out on pins FGx[0:7] and the values of bits
0 to 3 in frame mode register x are driven out on pins
FGx[8:11]. This mode is selected after device reset
when all bits in both registers are cleared.
In mode 1, the first four outputs of the frame group
FGx[0:3] are available for programmed output as in
mode 0. The other 8 outputs of each frame group are
available as output drive enables for the MVIP DSI/
DSO channels within the streams. FGA4 to FGA11
outputs correspond to output drive enables for the
MVIP DSo channels within streams 0 to 7,
respectively. For example, if only two DSo channels,
0 and 2 on stream 0, are enabled then the
corresponding channels 0 and 2 on FGA4 will be
pulled low and the remaining channels will be left
high. Similarly, FGB4 to FGB11 outputs correspond
to output drive enables for the MVIP DSi channels
within streams 0 to 7, respectively.
In mode 2, frame groups A&B are programmed as
output framing pulses for use with the local serial
data streams (refer to Figure 16 - “Frame Pulse
Timing for Mode 2” for further details). The position
of the first framing signal in a group is determined by
an 11 bit quantity. The quantity is the FMIC state
number (the number of 16MHz clock cycles during
one frame) minus one. The lower eight bits of this
quantity are located in the frame start register, and
the upper three bits are located in the frame mode
register.The width of the framing signal is determined
by the state of the FRM_TYPE bit in the frame mode
register and can be either a single bit cell time or 8
bit cell times. All framing signals in the same group
(A or B) follow each other sequentially, that is, the
first FGx[0] is asserted then exactly 8 bit cell times
later FGx[1] is asserted and so on until the last
2-153
MT90810
Preliminary Information
framing signal in the group is asserted. The distance
between consecutive frame pulses within a frame
group can be one 2, 4 or 8Mb/s channel time and
can be specified by two bits in the frame mode
register.
Mode 3 is identical to mode 2 except the polarity of
the framing pulses is logically inverted.
Refer to Tables 13 to 16 for details on the frame start
and frame mode registers.
All the framing signals FGA[0:11] and FGB[0:11] are
available in the 100 pin PQFP package.
Delay through the MT90810
Switching delay through the FMIC is dependent on
input and output stream, source and destination
channel, as well as, I/O data rate. A summary of
throughput delay values for the device is provided in
Table 1, “Throughput Delay Values” . The minimum
delay achievable in the MT90810 depends on the
data rate selected for the streams. When switching
from a slower input data rate to a faster output data
rate, the minimum delay is set by the faster output
data rate and the maximum delay is set by the
slower input data rate. When switching from a faster
input data rate to a slower output data rate, the
minimum delay is set by the slower output data rate
and the maximum delay is set by the faster input
data rate.
Input - Output
Rate
Throughput Delay
min
max
2.048 - 2.048Mb/s 2 x 2Mb/s t.s. 1 fr. + 2 x 2Mb/s t.s.
4.096 - 4.096Mb/s 3 x 4Mb/s t.s. 1 fr. + 5 x 4Mb/s t.s.
8.192 - 8.192Mb/s 5 x 8Mb/s t.s. 1 fr. + 11 x 8Mb/s t.s.
2.048 - 4.096Mb/s 3 x 4Mb/s t.s. 1 fr. + 2 x 2Mb/s t.s.
2.048 - 8.192Mb/s 5 x 8Mb/s t.s. 1 fr. + 2 x 2Mb/s t.s.
4.096 - 2.048Mb/s 2 x 2Mb/s t.s. 1 fr. + 5 x 4Mb/s t.s.
8.192 - 2.048Mb/s 2 x 2Mb/s t.s. 1 fr. + 11 x 8Mb/s t.s.
Table 1 - Throughput Delay Values
t.s.=timeslot is used synonymously with channel
fr.=125µs frame
2Mb/s t.s.=3.9µs
4Mb/s t.s.=1.95µs
8Mb/s t.s.=0.975µs
Microprocessor Interface
The FMIC is configured and controlled via a
microprocessor interface. The microprocessor
interface consists of the combined address/data bus
AD[0:7], address bits A[0:1], the chip select bit CS,
the RD and WR signals, the address latch enable
(ALE) signal and the RDY signal. If ALE is tied to
VSS, the interface acts as an Intel nonmultiplexed
interface with the AD[0:7] bus carrying only data and
pins A[0:1] serving as the address lines. If ALE is
tied to VCC the interface acts as a Motorola
nonmultiplexed interface using A[0:1] as address
lines with RD becoming DS and WR becoming R/W.
If ALE is active (switching during accesses), the
interface acts as in Intel multiplexed interface with
the AD[0:7] bus carrying both address and data and
the A[0:1] pins unused. The RDY signal acts as
IOCHRDY in Intel mode and as DTACK in Motorola
mode.
In all modes the FMIC decodes four read/write
registers in the microprocessor’s address space
according to Table 2, “FMIC I/O Addresses”.
Address
A[1:0]
Register
0 [00]
MCS - Master Control/Status Register
1 [01]
LAR - Low Address Register
2 [10]
AMR - Address Mode Register
3 [11]
IDR - Indirect Data Register
Table 2 - FMIC I/O Addresses
The microprocessor interface provides read and
write access to all the registers. When the
microprocessor performs a read or write to the
registers, the microprocessor cycle is a fast cycle (In
Intel mode, the RDY bit is not pulled low, and in
Motorola mode, DTACK is asserted immediately).
When the microprocessor performs a read or write to
data memory or connection memory, the
microprocessor cycle is a slow cycle (In Intel mode,
the RDY is pulled low until the cycle is complete, in
Motorola mode DTACK is not asserted until the cycle
is complete).
Software Control
Initialization of the MT90810
The FMIC control registers as well as the connection
memory and data memory are accessible through
indirect addressing.
The RESET pin should be hold low during
initialization and power-up to ensure that all internal
registers and connection and data memories are
cleared.
To perform a write operation to an indirect location,
the Low Address Register (LAR) and Address Mode
Register (AMR) registers must first be initialized. The
lower 8 bits of the indirect address are written to the
LAR, and then the upper bit of the indirect address
along with the appropriate bit settings to select the
2-154
MT90810
Preliminary Information
memory and auto increment/decrement mode is
written to the AMR. Finally, the write operation is
performed when data is written to the Indirect Data
Register(IDR). Similarly, to perform a read operation
from an indirect location, the LAR and AMR must be
initialized and then the data can be read from the
IDR.
Data memory can be read and written by the
microprocessor. This is accomplished by first
initializing the LAR and AMR register to select data
memory and then either reading from or writing to
the Indirect Data Register.
Connection memory can be read and written by the
microprocessor. This is accomplished by first
initializing the LAR and AMR register to select high
or low connection memory and then either reading
from or writing to the IDR.
The indirect address can be programmed to autoincrement after reads or writes to the indirect data
register by setting bits 6 and 7 in the AMR
accordingly. The auto-increment occurs only when
the indirect address register points to either data
memory or the high byte of connection memory.
If auto-increment on read/write is enabled, and
connection memory is selected, then consecutive
reads/writes to the IDR will toggle between selection
of low to high then back to low byte of connection
memory and continue on toggling until the reads/
writes to IDR stop. Note that when reading/writing
connection memory with auto increment disabled,
the reads/writes to IDR will toggle from low to high
byte connection memory once only.
Using the auto-increment feature, the connection
memory can be quickly initialized by resetting the
LAR and initializing the AMR for auto-increment on
write with connection memory low byte selected.
Writing a stream of bytes to IDR will then fill
connection memory. The first byte written to the IDR
will go to the low byte of the first connection memory
location. The memory space selection will be
automatically toggled to select connection memory
high. The second byte written to the IDR will then be
written to connection memory high of the first
connection memory location. The memory space will
automatically toggle back to the low byte connection
memory and the address pointer will be incremented
to prepare for writing to the next location in
connection memory. Similarly, the contents of
connection memory can also be read back quickly by
setting the auto-increment on read bit of AMR and
reading from the IDR continuously.
Writing to a data memory of connection memory
when the address register contains an indirect RAM
address of greater than 383 will cause unpredictable
results.
DMA Interface
The DMA interface to the FMIC is accessible only
when the microprocessor interface is in INTEL mode.
All 128 local channels can be DMA’ed out to/in from
external memory. MVIP channels can be DMA’ed by
switching to local channels.
The DMA_EN bit in the FMIC Control/Status register
enables DMA mode. This bit should be set only after
the desired local channels have been enabled for
DMA. The DMA_EN bit does not take effect until
after the beginning of the next MVIP frame. This
assures that when the DMA transactions begin, that
they begin on a frame boundary.
An individual local channel is enabled for DMA by
setting the CE bit in connection memory high for that
channel. When a channel is enabled for DMA, both
input and output are enabled for DMA. The local
output data is also driven out on the programmed
serial output stream. It is not possible to enable input
without output or vice versa. If channels in time slot
0 are enabled for DMA, there will be no DMA
requests for those channels in the first frame after
DMA is enabled. Instead, setup and preparation for
the DMA will occur in that first frame, in the timeslot
preceding. DMA transfer will actually occur in the
second frame after DMA is enabled. It is, therefore,
recommended that channels in time slot 0 not be
enabled for DMA.
The DMA signals DREQ[1] and DACK[1] control
transfers for DMA reads from the FMIC while
DREQ[0] and DACK[0] control transfers for DMA
writes to the FMIC. For every 2Mb/s timeslot where a
channel is enabled for DMA, the FMIC will assert
DREQ and wait for a DACK from an external
controller. Upon receiving the acknowledgement,
DACK, it would proceed with one DMA burst transfer.
DMA read requests always occur at the beginning of
the 2Mb/s time slot during which, all channels
enabled for DMA in the timeslot will be DMA’ed out in
a burst, onto the local serial data stream. One burst
implies one DREQ cycle, whereby DREQ is held low
for the duration of the transfer. The maximum
number of 8 bit channels that can be DMA’ed out
during one burst is 4, since, regardless of the serial
interface mode, there can be only four 8 bit channels
per 2Mb/s time slot, whether it be one channel per
stream (on 4 streams) at 2Mb/s, 2 channels per
stream (on 2 streams) at 4Mb/s or 4 channels all on
one stream at 8Mb/s.
DMA write requests occur at the end of the 2Mb/s
time slot during which, all channels enabled for DMA
in the timeslot will be DMA’ed from the local serial
data stream. DMA write requests can also occur in
bursts of up to four 8 bit channels. The data for write
requests is actually staggered by one DMA request
for each stream. This means that the data written
2-155
MT90810
Preliminary Information
into the device due to a DMA write request of a given
channel, is not actually written to that channel but to
the next channel enabled for DMA on the same
stream.
If a DMA read or write request is not completely
served by the time the next request needs to be
asserted, a DMA overrun error occurs. This causes
the corresponding overrun bit in the MCS register, as
well as, the ERR bit to be set. DMA access can be
throttled by disabling DMA for several timeslots in
between channels that have DMA enabled.
Bit
Name
PLL Diagnostic
Diagnostic for the PLL is available via a diagnostic
register. The register contains bits which should
never be set under normal operating conditions. Two
bits in the register SEL_XIN or VCO_BYP may be
set if the user wishes to bypass the internal analog
PLL or VCO, respectively. The bits are defined in
Table 17 - “Diagnostic (DIAG_REG) Register”.
Description (This register is cleared upon reset)
7
PLL_UNLCK
The bit will be asserted if the on-chip PLL goes out of lock. The ERR pin of the FMIC
will also be asserted high. The PLL_UNLCK bit will remain asserted until a zero is
written to it.
6
DMAW_OV
5
DMAR_OV
When asserted, the bits indicate that a DMA overrun condition occurred on the DMA
Read/Write channel, respectively. The ERR pin of the FMIC will also be asserted. The
DMAR/W_OV bits will remain asserted until zeros are written to them.
4
CLK_ERR
The bit monitors activity on the C4b pin of the MVIP bus and is asserted if there has
been no activity on the C4b pin for 4µs. The ERR pin of the FMIC will also be asserted
high. The CLK_ERR bit will remain asserted until a zero is written to it
3
MVIP_MST
When set, enables the FMIC to drive the MVIP clock signals and consequently to
become master of the MVIP bus. When cleared, FMIC becomes slave of MVIP bus.
2
DMA_EN
The bit should be set to enable DMA operations only after the DMA control registers
have been initialized
1
FMIC_EN
When cleared, all MVIP signals are high impedance and LD0&2 are set to logic 1,
LD1&3 are set to logic 0. The bit should be set to enable the FMIC to drive data onto the
streams only after the chip has been initialized
0
RESET
When set, clears all registers in the FMIC control space but does NOT clear connection
and data memory. The bit must be cleared for normal operation
Table 3 - Master Control/Status Register [00]
Bit
7:0
Bit Function
Bits 0 to 7 of the Indirect Address
Table 4 -Low Address Register [01]
Bits
Bit Function
7:6
Auto increment/decrement mode
[00] Normal Mode - indirect address not auto incremented
[01] Auto increment indirect address after indirect read of IDR
[10] Auto increment indirect address after indirect write of IDR
[11] Auto increment indirect address after indirect read or write of IDR
5:4
Selects the memory space:
[00] FMIC Control Registers
[01] Data Memory
[10] Connection Memory Low Byte
[11] Connection Memory High Byte
3:1
Reserved
0
Bit 8 of the Indirect Address
Table 5 - Address Mode Register [10]
2-156
MT90810
Preliminary Information
Bits
Bit Function
7:0
All bits are written into the indirect address location specified by the LAR and AMR registers.
If auto increment on write/read is enabled, and connection memory is selected, then consecutive
writes/reads to/from the IDR will toggle between selection of high byte and low byte connection
memory.
Table 6 - Indirect Data Register [11]
Indirect Address
Name
Function
0
CLK_CNTRL
Clock Control Register
1
LOC_CLK
Local Output Clock Control
2
SER_MODE
Local Serial Configuration Register
3
RESERVED
4
FRMA_STRT
Frame Group A start register
5
FRMA_MODE
Frame Group A mode register
6
FRMB_STRT
Frame Group B start register
7
FRMB_MODE
Frame Group B mode register
8:11
RESERVED
12
DIAG_REG
13:511
RESERVED
Chip diagnostic bits
Table 7 - FMIC Control Register (read/write)
EN_SEC8K
SEL_S8K
7
6
PLL_MODE XCLK_SEL
5
4
3
2
1
0
Figure 6 - Clock Control (CLK_CNTRL) Register
Description
Name
Mode [bits]
SEL_S8K
EN_SEC8K
Function
Selects source of 8kHz signal driven out on SEC8K pin
0 [00]
Select EX_8KA as SEC8K output
1 [01]
Select EX_8KB as SEC8K output
2 [10]
Select FRAME as SEC8K output
3 [11]
RESERVED
Enables SEC8K as output
Table 8 - EN_SEC8K and SEL_S8K bits
2-157
MT90810
Mode
[bits]
Preliminary Information
Description
APLL source
Frame Sync.
Function
0 [000]
X1 divided by
1,2, or 4
no frame
sync.
FMIC as Timing Master
• FMIC defaults to this mode after reset (Clock Control Register
is cleared).
• X1 divided by 1,2 or 4 is used as the input to the APLL.
• State machine is free running and does not synchronize to any
external 8kHz source.
• XCLK_SEL can be programmed to any mode.
• MVIP_MST bit in MCS is set.
• Used when the FMIC is to become the timing master in a
system which has no digital network connections (T1 or E1).
1 [001]
SEC8K >DPLL
2 [010]
EX8KA >DPLL
no frame
sync.
3 [011]
EX8KB >DPLL
FMIC as MVIP Master (Slaved to external 8kHz)
• DPLL is selected as the source to the APLL. Input to the DPLL
is either SEC8K,EX8KA/EX8KB.
• State machine is not synchronized to external 8kHz (SEC8K/
EX8KA/B); that is, FRAME signal is freq locked but not
necessarily phase aligned with external 8kHz.
• XCLK_SEL must be programmed to mode 0.
• MVIP_MST bit in MCS is set.
4 [100]
MVIP C4
frame sync.
to F0
FMIC as MVIP Slave
• FMIC is entirely slaved to MVIP bus timing.
• MVIP C4 is selected as input to APLL.
• State machine is synchronized to MVIP C4 and F0 inputs.
• MVIP_MST bit in MCS register must be cleared.
5 [101]
SEC8K >DPLL
frame sync.
to SEC8K
6 [110]
EX8KA >DPLL
frame sync.
to EX8KA
7 [111]
EX8KB >DPLL
frame sync.
to EX_8KB
FMIC as MVIP Master (Slaved to external 8kHz)
• DPLL is selected as the source to the APLL. Input to the DPLL
is either SEC8K,EX8KA/EX8KB.
• State machine is synchronized to external 8kHz (SEC8K/
EX8KA/B); that is, FRAME signal is freq locked and phase
aligned with external 8kHz.
• XCLK_SEL must be programmed to mode 0.
• MVIP_MST bit in MCS must be set.
Table 9 - PLL_MODE bits (control PLL and frame synchronization)
Description
Mode [bits]
X1 =
0
1
2
3
[00]
[01]
[10]
[11]
2-158
Comments
16.384MHz
X1 must be 16.384MHz when PLL is in modes 1-3 or 5-7
8.192MHz
4.096MHz
RESERVED
Table 10 - XCLK_SEL bits (control divide ratio of X1 clock)
MT90810
Preliminary Information
Bit
Name
Bit Function
7
DACK1
Read-only, reads logic value on DACK1 pin
6
DACK0
Read-only, reads logic value on DACK0 pin
5
EX8KB
Read-only, reads logic value on EX8KB pin
4
EX8KA
Read-only, reads logic value on EX8KA pin
3
INV_CLK8
When set, inverts 8.192MHz CLK8 output pin
2
INV_CLK4
When set, inverts 4.096MHz CLK4 output pin
1
INV_CLK2
When set, inverts 2.048MHz CLK2 output pin
0
INV_FRM
When set, inverts FRAME output signal
Table 11 - Local Clock Control (LOC_CLK) Register
RESERVED
7
6
5
4
3
SER_CNFG
2
1
0
Figure 7 - Serial Mode (SER_MODE) Register
Mode
[bits]
0 [00]
1 [01]
2 [10]
Description
2MHz streams
All local streams are configured to run at 2MHz.
Each channel occupies a 2Mb/s timeslot of 3.9µs.
4MHz streams
local streams 0&1 are multiplexed onto pin LDI/O[0]
local streams 2&3 are multiplexed onto pin LDI/O[2]
Each channel occupies a 4Mb/s timeslot of 1.95µs.
8MHz streams
all four local streams are multiplexed onto pins LDI/
O[0]
Each channel occupies a 8Mb/s timeslot of 0.975µs.
Multiplexing of streams onto pins
LDI/O[str] where str=stream (0-3)
2MHz,
32 channels
channel
channel
channel
channel
etc....
0
1
2
3
LDI/O[0] = local stream 0
LDI/O[1] = local stream 1
LDI/O[2] = local stream 2
LDI/O[3] = local stream 3
LDI/O[0]
LDI/O[2]
(4MHz, 64
(4MHz, 64
channels)
channels)
stream0, ch0
stream2, ch0
stream1, ch0
stream3, ch0
stream0, ch1
stream2, ch1
stream1, ch1
stream3, ch1
LDI/O[0]
(8MHz, 128
channels)
stream0, ch0
stream1, ch0
stream2, ch0
stream3, ch0
stream0, ch1
channel 0
channel 1
channel 2
channel 3
channel 4
etc....
Table 12 - SER_CNFG bits (control configuration of local serial streams)
2-159
MT90810
Preliminary Information
Mode
[bits]
3 [11]
Multiplexing of streams onto pins
LDI/O[str] where str=stream (0-3)
Description
Split 2MHz/4MHz streams
Local streams 0&1 are each configured to run at
2MHz on pins LDI/O[0] and LDI/O[1], respectively.
Local streams 2&3 are multiplexed onto pin LDI/O[2].
LDI/O[0] = local stream 0
LDI/O[1] = local stream 1
LDI/O[2]
(4MHz, 64
channels)
channel 0
stream2, ch0
channel 1
stream3, ch0
channel 2
stream2, ch1
channel 3
stream3, ch1
etc....
Table 12 - SER_CNFG bits (control configuration of local serial streams)
MODE [00] RESERVED
VARIABLE
MODE (dependent on MODE
7
6
5
4
3
2
1
AAAAAAAAAAA
AAAAAAAAAAA
AAAA
AAAAAAA
AAAA
AAAAAAAA
AAAAAAA
AAA
AAAAAAAA
AAAAAAA
7 6 5 4 3
AAAA
AAAAAAAAAAA
AAA
AAAA
AAAA
AAAAAAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAA
AAAA
AAAAAAAA
AAAAAAA
AAA
bits)AAAA
AAAAAAAA
AAAAAAA
AAA MODE [01] RESERVED
AAAA
AAAA
AAAAAAAAAAA
AAA
AAAA
AAAA
AAAAAAAAAAA
AAA
AAAA
AAAA
AAAAAAAAAAA
AAA
AAAA
AAAA
AAAAAAA
AAA
0 AAAA
7 6 5 4 3
AAAA
AAAA
AAAAAAAAAAA
AAA
AAAA
AAAA
AAA
AAAA
AAAAAAAA
AAAAAAA
AAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAAAAAAA
AAAAAAA
AAA
FRM_TYPE
AAAA
AAAA
AAA
AAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAA
AAA
AAAAAAAAAAAMODE [10/11]
BIT_RATE
AAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAA
AAA
AAAA
AAAAAAAA
AAAAAAA
AAA
7 6 5 4 3
PROG_OUT(11:8)
2
2
6
5
4
3
2
1
0
2
1
0
1
0
RESERVED
MODE [01]
7
6
5
4
3
2
STRT(7:0)
MODE [10/11] 7
6
5
4
3
2
Figure 9 - Frame Start ( 1 FRMx_STRT) Register
1. FRMx represents either FRMA for frame group A, or FRMB for group B.
2-160
1
0
STRT
PROG_OUT(7:0)
7
0
PROG_OUT(3:0)
Figure 8 - Frame Mode ( 1FRMx_MODE) Register
MODE [00]
1
1
0
MT90810
Preliminary Information
Mode [bits]
0 [00]
Description
Programmed output
FGx[0:11] are programmable output pins. All 8 bits of FRMx_START register are driven
out pins FGx[0:7] (with bit 0 corresponding to pin FGx[0] etc.) and bits 0-3 of
FRMx_MODE register are driven out pin FGx[8:11] (with bit 0 corresponding to pin
FGx[8] etc.).
1
1 [01]
DSi/DSo output enables
FGA[4:11] pins correspond to output drive enables for the MVIP DSo streams 0 to 7,
respectively.
FGB[4:11] pins correspond to output drive enables for the MVIP DSi streams 0 to 7,
respectively.
FGx[0:3] are programmable output pins. The least significant four bits of FRMx_MODE
register are driven out pins FGx[0:3] (with bit 0 corresponding to pin FGx[0] etc.).
2 [10]
Normal Framing
Frame groups A&B (FGx[0:11]) are programmed as output framing pulses for use with
the local serial data streams (see Figure 19 - “Frame Pulse Timing for Mode 2” ). The
position of the first framing signal in a group is determined by an 11 bit quantity. The
quantity is the FMIC state number minus one. The quantity determines when the first
framing signal in a group is to be asserted high.
3 [11]
Inverted Framing
Identical to Normal Framing except the polarity of the framing pulses is logically inverted.
Table 13 - Frame Group Mode bits
1. FRMx represents either FRMA for frame group A, or FRMB for group B.
Bit
Name
Description
Frame Start (FRMx_STRT) Register x
7:0
PROG_OUT(7:0)
All 8 bits are driven out FGx[7:0]
Frame Mode (FRMx_MODE) Register x
7:6
MODE
Frame Group Mode
0 [00] Programmed Output
5:4
RESERVED
3:0
PROG_OUT(11:8)
All 4 bits are driven out FGx[11:8]
Table 14 - Frame Register bits for mode 0
Bit
Name
Description
Frame Start (FRMx_STRT) Register x
7:0
RESERVED
Frame Mode (FRMx_MODE) Register x
7:6
MODE
5:4
RESERVED
3:0
PROG_OUT(3:0)
Frame Group Mode
1 [01] DSi/DSo output enable
All 4 bits are driven out FGx[3:0]
Table 15 - Frame Register bits for mode 1
2-161
MT90810
Preliminary Information
Bit
Name
Description
Frame Start (FRMx_STRT) Register x
7:0
STRT(7:0)
Lower 8 bits of the 11 bit quantity specified in Table 13 - “Frame Group
Mode bits”
Frame Mode (FRMx_STRT) Register x
7:6
MODE
Frame Group Mode
2 [10] Normal Framing
3 [11] Inverted Framing
5
FRM_TYPE
Type of framing signal for this group
0 Frame pulse is one bit cell wide
1 Frame pulse is eight bit cell wide
4:3
BIT_RATE
Frame Group bit rate register
Spacing for the framing pulses is for:
0 [00] 2Mb/s data rate
1 [01] 4Mb/s data rate
2 [10] 8Mb/s data rate
3 [11] Reserved
2:0
STRT(11:8)
Upper three bits of the 11 bit quantity specified in Table 13 - “Frame Group
Mode bits”
Table 16 - Frame Register bits for modes 2&3
Bit
Name
Description
7:3
RESERVED
Should NEVER be set under normal operating conditions
2
VCO_BYP
Bypass On-chip VCO
External VCO may be used in place of FMIC VCO
1
RESERVED
Should NEVER be set under normal operating conditions
0
SEL_XIN
Select X1 as chip master clock, direct input to FMIC state machine.
Bypass entire On-chip APLL (including VCO)
Table 17 - Diagnostic (DIAG_REG) Register
2-162
MT90810
Preliminary Information
Streams
Indirect RAM Address
Channels
decimal
hex
MVIP Stream 0
0:31
0:31
0x00:0x1f
MVIP Stream 1
0:31
32:63
0x20:0x3f
MVIP Stream 2
0:31
64:95
0x40:0x5f
MVIP Stream 3
0:31
96:127
0x60:0x7f
MVIP Stream 4
0:31
128:159
0x80:0x9f
MVIP Stream 5
0:31
160:191
0xa0:0xbf
MVIP Stream 6
0:31
192:223
0xc0:0xdf
MVIP Stream 7
0:31
224:255
0xe0:0xff
Local Stream 0
0:31
256:287
0x100:0x11f
Local Stream 1
0:31
288:319
0x120:0x13f
Local Stream 2
0:31
320:351
0x140:0x15f
0:31
352:383
0x160:0x17f
Local Stream 3
Table 18 - Data Memory Mapping
Indirect RAM Address
Streams
Channels
decimal
hex
0:31
0x00:0x1f
MVIP Stream 0
0:31
32:63
0x20:0x3f
MVIP Stream 1
0:31
64:95
0x40:0x5f
MVIP Stream 2
0:31
96:127
0x60:0x7f
MVIP Stream 3
0:31
128:159
0x80:0x9f
MVIP Stream 4
0:31
160:191
0xa0:0xbf
MVIP Stream 5
0:31
192:223
0xc0:0xdf
MVIP Stream 6
0:31
224:255
0xe0:0xff
MVIP Stream 7
0:31
256:287
0x100:0x11f
Local Stream 0
0:31
288:319
0x120:0x13f
Local Stream 1
0:31
320:351
0x140:0x15f
Local Stream 2
0:31
352:383
0x160:0x17f
Local Stream 3
0:31
Table 19 - Connection Memory Mapping
CAB7-0
7
6
5
4
3
2
1
0
Figure 10 - Connection Memory Low Byte
Bit
7-0
Name
CAB7-0
Description
Source Channel Address bits 0-7. These eight bits, together with CAB8 in
connection memory high, are used to select any one of the 384 source input
channels for the connection.
Table 20 - Connection Memory Low Bits
2-163
MT90810
Preliminary Information
OE/CE
RESERVED DC/CSTo
MC
7
6
5
4
3
2
CAB8
1
0
Figure 11 - Connection Memory High Byte
Bit
Name
Description
7:4
RESERVED
3
DC
Direction Control. controls the direction of the MVIP DSi/DSo channel pair.
When DC is set, DSi is the input channel and DSo is the output channel. When DC
is clear the direction is reversed.
2
MC
Message Channel. This bit, when set, will send the eight bits of connection memory
low directly out the corresponding output channel and stream. When the bit is
cleared, the contents of the programmed location in connection memory low act as
an address for the data memory and so determine the source of the corresponding
output channels and stream.
1
OE
Output Enable. This bit, when set, enables the output drivers on a per-channel
basis. This allows individual channels on individual streams to be made highimpedance, permitting the construction of switch matrices. When this bit is cleared,
the drivers are disable.
0
CAB8
Source Channel Address Bit 8. This bit, together with bits CAB0-7 in connection
memory low, is used to select one of 384 different source input channels for the
connection.
Table 21 - Connection Memory High Bits for MVIP channels
2-164
MT90810
Preliminary Information
Bit
Name
7-4
RESERVED
3
CSTo
Description
CSTo. The inverted value of this bit is output on the CSTo pin and is available for
general purpose system timing functions. The CSTo bit for each of the local output
channels is multiplexed onto the CSTo pin as illustrated below:
A
A
A
A
AA
AA
A
A
A
A
A
AA
AA
A
A
A
A
A
AA
AA
A
A
C4
A
A
A
A
A
A
AA
AA
A
A
A
A
A
A
A
A
A
AA
AA
A
A
A
A
AA
AA
A
A
A
A
A
CSTo output timing
A
A
A
AA
AA
A
A
LD0:0 LD1:0 LD2:0 LD3:0AA LD0:1 LD1:1 LD2:1 LD3:1AA LD0:2 LD1:2 LD2:2 LD3:2AA LD0:3
AA
AA
A
A
A
A
A
F0
2
MC
Message Channel. This bit, when set, will send the eight bits of connection memory
low directly out the corresponding output channel and stream. When the bit is cleared,
the contents of the programmed location in connection memory low act as an address
for the data memory and so determine the source of the corresponding output channels
and stream.
1
CE
Channel Enable. If the DMA_EN bit in the Control/Status register is set, then this bit
flags the control logic to perform a bidirectional DMA transfer for this input/output
channel pair. When the bit is clear, the DMA transfer for this channel pair is disabled.
If DMA operations are not enabled then this bit must be cleared.
0
CAB8
Source Channel Address Bit 8. This bit, together with bits CAB0-7 in connection
memory low, is used to select one of 384 different source input channels for the
connection.
Table 22 - Connection Memory High Bits for Local channels
2-165
MT90810
Preliminary Information
JTAG Support
Test Access Port (TAP)
The FMIC JTAG interface is designed to the
Boundary-Scan standard IEEE1149.1. The standard
specifies a design-for-testability technique called
Boundary-Scan Test (BST). A boundary-scan IC has
a shift-register stage or ‘Boundary-Scan Cell’ (BSC)
in between the core logic and the I/O buffers
adjacent to each I/O pin. The BSCs can control and
observe what happens at each I/O pin of the IC. The
operation of the boundary-scan circuitry is controlled
by a Test Access Port (TAP) Controller.
The Test Access Port (TAP) provides access to many
test support functions built into the FMIC. It consists
of three input connections and one output
connection. The following connections form the TAP:
•
Test Clock Input (TCK)
TCK provides the clock for the test logic. The
TCK must not interfere with any on-chip clock
and thus remain independent. This permits
shifting of test data into or out of the BoundaryScan register cells concurrently with the
operation of the device without interfering with
on-chip logic.
•
Test Mode Select Input (TMS)
The logic signal (0’s and 1’s) received at the
TMS input are interpreted by the TAP Controller
to control the test operations. The TMS signals
are sampled at the rising edge of the TCK
pulses. When TMS is not driven from an
external source, the test logic perceives a logic
1.
BOUNDARY -SCAN CELL(BSC)
BSC
BSC
BSC
BSC
CORE LOGIC
BSC
BSC
BSC
BSC
T
A
P
C
O
N
T
R
O
L
L
E
R
TEST DATA IN (TDI)
TEST CLOCK (TCK)
TEST MODE
SELECT (TMS)
TEST DATA OUT (TDO)
Figure 12 - A Typical Boundary-Scan IC
I[0:1] Instruction
Description
[00]
EXTEST
Boundary-Scan
register selected,
Test Enabled
This instruction is specifically provided to allow board-level interconnect
testing of opens, bridging errors etc.
When the EXTEST instruction is selected, the on-chip logic is isolated
from the FMIC’s I/O pin such that the value of the I/O pins is determined
by its boundary-scan register. Data for the execution of this instruction
can be preloaded into the boundary-scan register with the SAMPLE/
PRELOAD instruction.
[01]
SAMPLE/
PRELOAD
Boundary-Scan
register selected,
Test Disabled
Two functions can be performed by the use of this instruction. It allows a
SAMPLE (‘snapshot’) of the normal operation of the FMIC to be taken for
examination. And, prior to the selection of another test operation, a
PRELOAD can place data values into the latched parallel outputs of the
Boundary-Scan cells. During the execution of the instruction, the on-chip
logic operation is not hampered in any way.
[10]
BYPASS/
TEST
Bypass register
selected,
Test Enabled
This instruction is used to BYPASS the FMIC while sampling or loading
the data registers in other devices with scan registers in the same serial
register chain. The FMIC is in test mode and the value of it’s I/O pins is
determined by its boundary-scan register.
[11]
BYPASS/
NOTEST
Bypass register
selected,
Test Disabled
This instruction is used to BYPASS the FMIC while performing boundaryscan testing on other devices with scan registers in the same serial
register chain. The FMIC is allowed to function normally. This instruction
is automatically loaded upon reset of the FMIC, as specified in
IEEE1149.1
Table 23 - Instruction Register
2-166
MT90810
Preliminary Information
•
•
The Test Data Input (TDI)
Serial input data applied to this port is fed either
into the instruction register or into a test data
register, depending on the sequence previously
applied to the TMS input. Both registers are
described in a subsequent section. The
received input data is sampled at the rising
edge of the TCK pulses. When TDI is not driven
from an external source, the test logic
perceives a logic 1.
The Test Data Output (TDO)
Depending on the sequence previously applied
to the TMS input, the contents of either the
instruction register or a data register are
serially shifted out towards the TDO. The data
out of the TDO is clocked at the falling edge of
the TCK pulses. When no data is shifted
through the cells, the TDO driver is set to an
inactive state.
The FMIC boundary-scan register contains 84 bits.
Bit 0 in Table 24 - “Boundary Scan Register” is the
first bit clocked out. All tristate enable bits are
asserted high i.e., a logic 1 enables the
corresponding group of outputs/bidirectionals. Note
that clocking all zeros into the scan path register will
set all outputs to tristate.
Bits
Definition
0:11
FGB[11:0]
12:23
FGA[11:0]
24:31
DSo[7:0]
32
tristate enable for DSo[7:0]
33:40
DSi[7:0]
41
tristate enable for DSi[7:0]
42:45
F0 , C4 , C2 , SEC8K
Instruction Register
46
tristate enable for
In accordance with the IEEE 1149.1 standard, the
FMIC uses public instructions listed in Table 23 “Instruction Register” . The FMIC JTAG Interface
contains a two bit instruction register. Instructions
are serially loaded into the Instruction Register from
the TDI when the TAP Controller is in its Shift-IR
state. Subsequently, the instructions are decoded to
achieve two basic functions: to select the test data
register that may operate while the instruction is
current and to define the serial test data register path
that is used to shift data between TDI and TDO
during data register scanning.
47:51
FRAME, CLK8, CLK4, CLK2, CSTo
52
tristate enable for ALL output only pins
53:54
EX8KA, EX8KB
55:58
LDO[3:0]
59:62
LDI[3:0]
63:70
D[7:0]
71
tristate enable for D[7:0]
72:75
RDY, ERR, DREQ[1:0]
76:83
RD, WR, CS, ALE, A[1:0], DACK[1:0]
Test Data Registers
Table 24
- Boundary Scan Register
As specified in the IEEE 1149.1 Standard, the FMIC
JTAG interface contains two test data registers:
•
The Boundary Scan Register
The Boundary-Scan Register consists of a
series of Boundary-Scan Cells arranged to form
a scan path around the boundary of the core
logic of the FMIC.
•
The Bypass Register
The Bypass Register is a single stage shiftregister that provides a one-bit path that
minimizes the distance for test data shifting
from the FMIC’s TDI to its TDO.
2-167
MT90810
Preliminary Information
Absolute Maximum Ratings*
Parameter
Symbol
Min
Max
Units
VDD - VSS
- 0.3
6
V
VI/O
VSS - 0.3
VDD + 0.3
V
1
Supply Voltage
2
Voltage on any I/O pin
3
Current at outputs
IO
4
Storage Temperature
TS
- 65
+ 125
°C
5
Thermal Resistance
Theta Ja
80
90
°C/W
mA
* Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed.
Recommended Operating Conditions
Characteristics
Sym
Min
Typ*
Max
Units
1
Input Voltage
VDD
4.75
5.25
V
2
Operating Temperature
TOP
0
+70
°C
3
Input Voltage Low
VI
VSS
VDD
Test Conditions
* Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing.
DC Characteristics: Clocked operation (TOP=0 to 70°C; VDD=5V±5%)
Characteristics
Sym
Min
Typ
Max
30
Units
Test Conditions
mA
1
Supply Current
IDD
2
Input High Voltage for CMOS Inputs
VIH
3
Input Low Voltage for CMOS pins
VIL
4
Input High Voltage for TTL Inputs
VIH
5
Input Low Voltage for TTL Inputs
VIL
0.8
V
6
Low Level Input Leakage Current
I IL
1.0
µA
VI= VSS
7
High Level Input Leakage Current
IIH
1.0
µA
VI= VDD
8
Input Pin Capacitance
CI
9
Output High Voltage
VOH
10
Output Low Voltage
VOL
11
Output High Voltage
VOH
12
Output Low Voltage
VOL
VSS+0.4
13
High Impedance Leakage
IOZ
1.0
14
Output Pin Capacitance
CO
15
Schmidt Trigger Positive Threshold
Vt+
16
Schmidt Trigger Negative Threshold
Vt-
2-168
3.5
V
1
2
V
V
4
pF
VDD -0.4
VSS+0.4
V
IOH= 4mA
V
IOL= 12mA
VDD -0.4
IOH= 2mA
10
µA
pF
3
0.6
IOL= 6mA
V
V
MT90810
Preliminary Information
AC Electrical Characteristics- Clock and Stream Timing
Characteristics
Sym
Min.
Typ.
Max.
Units
30
ns
1
Data Propagation Delay
tPD
0
2
Data Setup Time
tS
30
ns
3
Data Hold Time
tH
10
ns
4
Data bit 7 Tristate
tD7
60
90
ns
5
F0b/FRAME Setup Time
tFS
50
150
ns
6
F0b/FRAME Hold Time
tFH
50
150
ns
7
F0b/FRAME Pulse Width
tFW
200
300
ns
8
CLK8 Period
tC8P
110
122
134
ns
9
CLK8 High Width
tC8H
55
61
67
ns
10
CLK8 Low Width
tC8L
55
61
67
ns
11
C4b/CLK4 Period
tC4P
232
244
256
ns
12
C4b/CLK4 High Width
tC4H
110
122
134
ns
13
C4b/CLK4 Low Width
tC4L
110
122
134
ns
14
C2o/CLK2 Period
tC2P
474
488
502
ns
15
C2o/CLK2 High Width
tC2H
220
244
268
ns
16
C2o/CLK2 Low Width
tC2L
220
244
268
ns
Test Conditions
Load Cap
=200pF
For all Timing
16 MHz
8 MHz
tC4P
C4b
tC4L
tC4H
tC2P
C2o
F0b
tC2L
tC2H
tFS
tFH
tPD
tFW
DSO Output
DSI Output
BIT 7*
tD7
tS
BIT 6-0
tH
DSO Input
DSI Input
Note: *MVIP Output streams are high impedance during the first cycle of Bit 7
Figure 13 - MVIP Stream Timing
2-169
MT90810
Preliminary Information
tFW
FRAME
tFS
tFH
tC8P
CLK 8
tC8L
tC8H
tC4P
CLK 4
tC4L
tC4H
tC2P
CLK 2
(2 MHz
Bit Rate)
tC2L
tC2H
tPD
LDO
tS
LDI
(4 MHz
Bit Rate)
tH
tPD
tPD
LDO
tS
LDI
(8 MHz
Bit Rate)
tH
tPD
LDO
tS
LDI
tH
Note: *Timing for CLK is shown for LOC_CLK register set to 00hex
Figure 14 - Local Stream Timing
16 MHz Clock
(FMIC Internal Signal)
tPD
FGA [0:11]
FGB [0:11]
Figure 15 - Local Frame Timing
2-170
MT90810
2042
2044
2046
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
Preliminary Information
8 MHz
Clock
F0b
C4b
C2o
DSi/
DSo
In
Out
0
7
6
5
4
3
2
1
0
7
Frame Group programmed for 2Mb/s Data Streams
start of frame group can be programmed to occur on any 8 MHz clock boundary
FGx0
1 bit cell
8 bit cells
frame pulse can be programmed to be 1 bit cell or 8 bit cells wide
FGx1
Frame Group programmed for 4Mb/s Data Streams
FGx0
FGx1
FGx2
Frame Group programmed for 8Mb/s Data Streams
FGx0
FGx1
FGx2
Notes: x is either A for frame group A, or B for frame group B.
12 framing pulses per group, FGx0 to FGx11 are available in PQFP package.
Figure 16 - Frame Pulse Timing for Mode 2
2-171
MT90810
Preliminary Information
AC Electrical Characteristics - GCI Timing
Characteristics
Sym
Min.
Typ.
Max.
Units
1
Clock Period
tCK
232
244
256
ns
2
Clock High/Low Width
tCH,
tCL
110
122
134
ns
3
Frame Setup
tFRS
50
150
ns
4
Frame Hold
tFRH
50
150
ns
5
Clock Edge to Data Valid
tPD
30
ns
6
Data Setup
tLDS
30
ns
7
Data Hold
tLDH
10
ns
FMIC
FRAME
FSC
CLK4
DCL
LDO
DU/DD
LDI
DU/DD
Test Conditions
Load Cap = 200pF for all
timing
GCI
device
Figure 19 - FMIC to GCI Connections
See Detail a
CLK4/
DCL
Note: FE=0
FRAME/
FSC
Ch. 31
Bit 7
DU/DD
Ch. 0
Bit 0
Ch. 0
Bit 3
Ch. 0
Bit 2
Ch. 0
Bit 1
Note: bit 0 identifies the most significant bit
tCL
tCH
tCK
2.0V
DCL
0.8V
2.0V
FSC
tFRS
0.8V
tFRH
LDO/
DU/DD
2.0V
0.8V
tPD
tLDS
tLDH
LDI/
DU/DD
2.0V
0.8V
Detail a
Figure 20 - GCI Timing
2-172
MT90810
Preliminary Information
AC Electrical Characteristics - Microprocessor Timing
Characteristics
Sym
Min.
Typ.
Max.
Units
1
Address Setup
tAS
5
ns
2
Address Hold
tAH,
5
ns
3
Data Access from RDY High
tDAC
4
Microprocessor Access to Data
Ready
Register (Fast) Access
Memory (Slow) Access
tACC
5
Microprocessor to RDY low
tRDY
7
Data Hold
tDH
5
ns
6
Data Setup
tDS
5
ns
8
Data Enable Off
tDOFF
20
ns
25
ns
50
800
ns
ns
25
ns
Test Conditions
Load Cap = 100pF for all
timing
A[0:1]
tAH
tAS
CS
tRDY
RDY
tAS
tDAC
RD
tACC
tDOFF
AD[0:7]
(read)
WR
tDS
tDH
AD[0:7]
(read)
Note:
RDY is only driven low during memory (slow) cyles.
Figure 21 - Intel Non-multiplexed Bus Timing (ALE=VSS)
2-173
MT90810
Preliminary Information
tAH
AD[0:7]
Read Data
Add
tAS
ALE
tDOFF
CS
tACC
RD
tRDY
tDAC
RDY
Notes:
RDY is only driven low during memory (slow) cyles.
tDOFF is measured from either CS or RD going high, whichever is later.
Figure 22 - Intel Multiplexed Bus Timing for Read Cycle (ALE is active)
tAH
AD[0:7]
Add
Write Data
tAS
ALE
tDH
CS
tDAC
tACC
WR
tRDY
RDY
Notes:
RDY is only driven low during memory (slow cyles).
tDH is measured from either CS or WR going high, whichever is earlier.
Figure 23 - Intel Multiplexed Bus Timing for Write Cycle (ALE is active)
2-174
MT90810
Preliminary Information
A[0:1]
R/W [WR]
tAS
tAH
DS [RD]
CS
tACC
DTACK
tDOFF
tDAC
AD[0:7]
Read Data
Figure 24 - Motorola Non-multiplexed Bus Timing for Read Cycle (ALE=VDD)
A[0:1]
R/W [WR]
tAH
tAS
DS [RD]
CS
tACC
DTACK
tDS
tDH
AD[0:7]
Figure 25 - Motorola Non-multiplexed Bus Timing for Write Cycle (ALE=VDD)
2-175
MT90810
Preliminary Information
AC Electrical Characteristics - DMA Timing
Characteristics
1
Sym
C2o low to DACK1 asserted
Min.
Typ.
Max.
tCDAK1
Units
ns
DMA
controller
dependent
2
C2o low to DACK0 asserted
tCDAK0
ns
3
DACK1 asserted to RD low
tDAKR
4
DACK0 asserted to WR low
tDAKW
5
C2 low to DREQ1 asserted
tCDRQ1
0
30
ns
6
C2 low to DREQ0 asserted
tCDRQ0
0
30
ns
7
RD low (on 4th DMA read pulse) to
DREQ1 removed
tRDRQ
0
30
ns
8
WR low (on 4th DMA write pulse) to
DREQ0 removed
tWDRQ
0
30
ns
9
RD pulse width (DMA=fast read)
tRW
100
ns
8
WR pulse width (DMA=fast write)
tWW
100
ns
ns
ns
2Mb/s timeslot (3.9µs)
F0b
C2o
Detail a
tCDAK1
DREQ1
DACK1
RD
tCDAK0
tDAKR
DREQ0
DACK0
WR
tDAKW
Note:
DMA Read and Write cycles are asynchronous to C2o.
Figure 26 - DMA Interface Timing
2-176
Test Conditions
MT90810
Preliminary Information
C2o
tCDRQ
DREQ/1
async. to C2
DACK0/1
tWDRQ
tRDRQ
WR/RD
tRW
tWW
Figure 27 - DMA Timing Detail A
1.008 ± 0.016
(25.6 ± 0.4)
0.787 ± 0.004
(20 ± 0.1)
51
80
81
Index
0.772 ± 0.015
(19.6 ± 0.4)
0.551 ± 0.004
(14 ± 0.1)
50
31
100
1
30
0.026 ± 0.004
(0.65 ± 0.1)
0.012 ± 0.004
(0.30 ± 0.1)
0.106 ± 0.004
(2.7 ± 0.1)
0.110
(2.8)
0.006 ± 0.002
(0.15 ± 0.05)
0 - 12°
Coplanarity: 0.006 (0.15) max.
0.059± 0.012
(1.5 ± 0.3)
Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
Figure 28 - Mechanical Data
2-177
MT90810
Notes:
2-178
Preliminary Information