ETC VS23S010

IN
AR
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深圳市源合汇通 一级代理
VS23S010 Datasheet
电话13751145915
QQ2355355260
VS23S010 - 1 Megabit SPI SRAM
with Serial and Parallel Interface
and Integrated Pattern Generator
Features
Description
• Flexible 1.5V - 3.6V operating voltage
• 131,072 x 8-bit SRAM organization
• Serial Peripheral Interface (SPI) compatible
– SPI operating modes
∗ Byte read and write
∗ Sequential mode
– Supports Single, Dual and Quad
input read and write
– Fast operation: the whole memory
can be filled or read in 262176 cycles (Quad-I/O SPI)
– XHOLD and XWP pins
Alternatively, a 8-bit parallel interface can be
used to access the SRAM instead of the SPI.
To sum up, there are three separate operating modes in VS23S010:
• SPI Single, Dual, or Quad operation and
4 General Purpose I/O pins
• SPI Single, Dual, or Quad operation and
simultaneous pattern generation
IM
• 8-bit Parallel Interface (Simplified 8080
and NAND FLASH Type Interface)
– Sequential read and write in 4 byte
blocks
The VLSI Solution VS23S010 is an easy-touse and versatile serial SRAM device. The
memory is accessed via a SPI compatible
serial bus. The device also contains pattern
generation logic, which can be configured to
continuously output data from the memory array, for example to implement a video frame
buffer.
– Fast operation, the whole memory
can be filled in 131076 cycles and
read in 131077 cycles
EL
• Integrated pattern generator
– 4-bit and 2-bit output modes
– Configurable frame length
– IRQ output for synchronization
• 8-bit Parallel Interface operation
Applications
•
•
•
•
Microcontroller RAM extension
VoIP and internet data stream buffer
Audio data buffer
Video frame buffer
• High operating frequencies
– Up to 36 MHz for SPI
– Over 48 MHz for pattern generator
– 15 MHz for 8-bit parallel interface
PR
• Low-power CMOS technology
– Read current 130 µA at 1 MHz (SO=0,
TA =+25◦ C, VDD=3.3V)
– Standby current 35 µA (TA =+25◦ C,
VDD=3.3V)
2
3
4
5
6
7
8
VS23S010A
– FM CLK /3 MHz for SPI when pattern generator enabled
XHOLD/IO3
VCC
XCSPAR/IRQ
XWR
XRD/MCLK
XRESET
XCS
SO/IO1
16
15
14
13
12
11
10
9
SCLK
SI/IO0
PIO7
PIO6
PIO5
PIO4
GND
XWP/IO2
Figure 1: SOIC16 300 mils wide package,
compatible with standard pin out.
• Industrial temperature range
– -40◦ C to + 85◦ C
• Pb-Free and RoHS compliant
Version: 0.6, 2012-06-14
1
IN
AR
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深圳市源合汇通 一级代理
VS23S010 Datasheet
电话13751145915
QQ2355355260
Operating Modes
control
IO
clock
IO
VS23S010 operates in one of three modes:
SPI, SPI and pattern generator or 8-bit parallel mode.
data
IO
data
IO
XCS
SCLK
SI/IO0
SO/IO1
XWP/IO2
XHOLD/IO3
PIO4
Micro−controller
VS23S010
PIO5
PIO6
PIO7
XCSPAR/IRQ
XWR
8 Bit
Parallel Interface
XRD/MCLK
XRESET
SPI connection, minimum configuration
control
IO
XCS
clock
IO
SCLK
data
IO
SI/IO0
data
IO
1,048,576 bit
(128K x 8)
SRAM
Array
SO/IO1
control
IO
XWP/IO2
control
Pattern
Generator
IO
XHOLD/IO3
PIO4
Micro−controller
VS23S010
PIO5
PIO6
PIO7
XCSPAR/IRQ
XWR
XRD/MCLK
SPI
Serial Interface
IM
XRESET
SPI Dual−I/O−mode connection
control
EL
Figure 2: SPI and Pattern Generator can be
enabled at the same time. The pattern output is in pins PIO4..PIO7, which excludes the
operation of the 8-bit parallel interface when
pattern generator is active.
control
IO
PR
When 8-bit parallel interface is used to access SRAM, SPI and pattern generator must
be inactive.
Following are connection example pictures for
different operating modes.
Version: 0.6, 2012-06-14
SCLK
data
IO
SI/IO0
data
IO
SO/IO1
data
IO
XWP/IO2
data
IO
XHOLD/IO3
PIO4
Micro−controller
VS23S010
PIO5
PIO6
PIO7
XCSPAR/IRQ
XWR
XRD/MCLK
XRESET
In SPI mode SRAM and control registers can
be accessed. Dual-I/O and Quad-I/O modes
are used only for SRAM read and write.
When pattern generator is enabled SPI can
be used simultaneously. There is however
an additional limit to maximum SPI clock frequency in this mode.
XCS
clock
IO
SPI Quad−I/O−mode connection
control
IO
clock
IO
data
IO
data
IO
XCS
SCLK
SI/IO0
SO/IO1
XWP/IO2
XHOLD/IO3
Micro−controller
clock
reset
control
IO
data
data
data
data
XWR
XRD/MCLK
VS23S010
XRESET
XCSPAR/IRQ
PIO4
PIO5
PIO6
PIO7
DAC
SPI connection (minimum configuration), pattern generator enabled
2
control
IO
clock
IO
data
IO
data
IO
data
IO
data
IO
Micro−controller
clock
reset
control
IO
data
data
data
data
XCS
SCLK
SI/IO0
IN
AR
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深圳市源合汇通 一级代理
VS23S010 Datasheet
电话13751145915
QQ2355355260
SO/IO1
XWP/IO2
XHOLD/IO3
XWR
XRD/MCLK
VS23S010
XRESET
XCSPAR/IRQ
PIO4
PIO5
PIO6
PIO7
DAC
SPI connection Quad−I/O−mode, pattern generator enabled
XCS
data
IO
data
IO
data
IO
data
IO
Micro−controller
data
IO
data
IO
data
IO
data
IO
control
IO
clock
IO
clock
IO
reset
SI/IO0
SO/IO1
XWP/IO2
XHOLD/IO3
PIO4
PIO5
PIO6
PIO7
VS23S010
XCSPAR/IRQ
XWR
XRD/MCLK
XRESET
IM
IO
SCLK
PR
EL
8−bit parallel interface mode
Version: 0.6, 2012-06-14
3
深圳市源合汇通 一级代理
VS23S010 Datasheet
电话13751145915
QQ2355355260
IN
AR
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CONTENTS
Contents
VS23S010
1
Table of Contents
4
List of Figures
6
1 Disclaimer
7
2 Definitions
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4 Packages and Pin Descriptions
4.1 Wide SOIC16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
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5 Connection Guidelines
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EL
IM
3 Characteristics & Specifications
3.1 Absolute Maximum Ratings . . . . . .
3.2 Recommended Operating Conditions .
3.2.1 SPI (Single I/O Mode) . . .
3.2.2 Pattern Generator . . . . . .
3.2.3 8-bit Parallel Interface . . . .
3.3 DC Characteristics . . . . . . . . . . .
3.4 Current Consumption . . . . . . . . . .
3.4.1 SPI Mode . . . . . . . . . .
3.4.2 Pattern Generator Mode . .
3.4.3 8-bit Parallel Interface Mode
3.5 AC Characteristics . . . . . . . . . . .
3.5.1 General . . . . . . . . . . .
3.5.2 SPI Mode . . . . . . . . . .
3.5.3 Pattern Generator Mode . .
3.5.4 8-bit Parallel Interface Mode
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22
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23
23
24
25
7 SPI Commands and Addressing
7.1 SPI Read Commands . . . . . . . . . . . . .
7.1.1 Dual-Output Read . . . . . . . . .
7.1.2 Quad-Output Read . . . . . . . .
7.2 SPI Write Commands . . . . . . . . . . . . .
7.2.1 Dual-Input Write . . . . . . . . . .
7.2.2 Quad-Input Write . . . . . . . . .
7.3 SPI Miscellaneous Commands . . . . . . .
7.3.1 Read Status Register . . . . . . .
7.3.2 Read Manufacturer and Device ID
7.3.3 Read GPIO Control Register . . .
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26
26
27
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29
30
30
31
31
PR
6 Device Operation
6.1 SPI . . . . . . . . . . . . . . . . .
6.2 Dual-I/O and Quad-I/O Operation
6.3 Pattern Generator . . . . . . . . .
6.3.1 Known Issues . . . . .
6.4 8-Bit Parallel Interface . . . . . .
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Version: 0.6, 2012-06-14
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4
深圳市源合汇通 一级代理
VS23S010 Datasheet
电话13751145915
QQ2355355260
7.3.4
7.3.5
IN
AR
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CONTENTS
Write GPIO Control Register . . . . . . . . . . . . . . . . . . . . . . .
Read GPIO State Register . . . . . . . . . . . . . . . . . . . . . . . .
8 Pattern Generator Commands
8.1 Read Pattern Generator Frame Length . .
8.2 Write Pattern Generator Frame Length . .
8.3 Read Pattern Generator Control Register .
8.4 Write Pattern Generator Control Register .
8.5 Read Pattern Generator Counter Register
33
33
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35
35
36
38
40
40
9 8-Bit Parallel Interface Commands and Addressing
9.1 8-Bit Parallel Interface Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2 8-Bit Parallel Interface Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
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42
10 Document Version Changes
45
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46
PR
EL
IM
11 Contact Information
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Version: 0.6, 2012-06-14
5
深圳市源合汇通 一级代理
VS23S010 Datasheet
电话13751145915
QQ2355355260
IN
AR
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LIST OF FIGURES
List of Figures
IM
PR
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
SOIC16 300 mils wide package, compatible with standard pin out. . . . . . . . .
SPI and Pattern Generator can be enabled at the same time. The pattern output
is in pins PIO4..PIO7, which excludes the operation of the 8-bit parallel interface
when pattern generator is active. . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XHOLD Timing, SPI and Dual-I/O Input Modes . . . . . . . . . . . . . . . . . . .
XHOLD Timing, SPI and Dual-I/O Output Modes . . . . . . . . . . . . . . . . . .
XWP Timing, SPI and Dual-I/O Modes . . . . . . . . . . . . . . . . . . . . . . . .
XRESET Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pattern Generator Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-bit Parallel Interface Timing, XRD as clock enable . . . . . . . . . . . . . . . .
8-bit Parallel Interface Timing, XWR as clock enable . . . . . . . . . . . . . . . .
Device Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pattern Generator Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing of on-chip reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-Bit Parallel Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Dual-Output Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Quad-Output Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Dual-Input Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Quad-Input Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Read Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Read Manufacturer and Device ID . . . . . . . . . . . . . . . . . . . . . . . .
SPI Read GPIO Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Write GPIO Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Read GPIO State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Read Pattern Generator Frame Length . . . . . . . . . . . . . . . . . . . . .
Pattern Generator Start, Four-output Mode . . . . . . . . . . . . . . . . . . . . .
Pattern Generator Start, Two-output Mode . . . . . . . . . . . . . . . . . . . . .
Pattern Generator IRQ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Write Pattern Generator Frame Length . . . . . . . . . . . . . . . . . . . . .
SPI Read Pattern Generator Control . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Write Pattern Generator Control . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Read Pattern Generator Counter . . . . . . . . . . . . . . . . . . . . . . . .
8-Bit Parallel Interface Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8-Bit Parallel Interface Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EL
1
2
Version: 0.6, 2012-06-14
1
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6
深圳市源合汇通 一级代理
VS23S010 Datasheet
电话13751145915
QQ2355355260
1
Disclaimer
DEFINITIONS
IN
AR
Y
2
This is a preliminary data sheet. All properties and figures are subject to change.
2
Definitions
B Byte, 8 bits.
b Bit.
GPIO General Purpose I/O
POR Power On Reset
SPI Serial Peripheral Interface
SRAM Static Random Access Memory
PR
EL
IM
TBD To Be Defined
Version: 0.6, 2012-06-14
7
深圳市源合汇通 一级代理
VS23S010 Datasheet
电话13751145915
QQ2355355260
3
Characteristics & Specifications
3.1
Absolute Maximum Ratings
Parameter
Positive Supply
Current at Any Non-Power Pin1
Voltage at Any Digital Input
Operating Temperature
Storage Temperature
ESD Protection on Any Pin3
2
3
Symbol
VDD
Min
-0.3
-0.3
-40
-65
2.0
Max
3.6
±50
VDD+0.32
+85
+150
Unit
V
mA
V
◦C
◦C
kV
Higher current can cause latch-up.
Must not exceed 3.6 V
Human Body Model (HBM) MIL-STD-883E Method 3015.7
3.2
Recommended Operating Conditions
IM
1
CHARACTERISTICS & SPECIFICATIONS
IN
AR
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3
Parameter
Ambient Operating Temperature
Voltage
3.2.1
Symbol
TA
VDD
Min
-40
1.5
Typ
Max
+85
3.6
Unit
◦C
V
Test Conditions
SPI (Single I/O Mode)
EL
TA = +85 ◦ C
Symbol
FSCLK
SPI Clock Frequency (Write)
FSCLK
PR
Parameter
SPI Clock Frequency (Read)
Version: 0.6, 2012-06-14
Min
Typ
Max
12
18
33
36
27
27
48
48
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Test Conditions
VDD = 1.5 V
VDD = 1.8 V
VDD = 3.0 V
VDD = 3.3 V
VDD = 1.5 V
VDD = 1.8 V
VDD = 3.0 V
VDD = 3.3 V
8
深圳市源合汇通 一级代理
VS23S010 Datasheet
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3.2.2
Pattern Generator
TA = +25 ◦ C
Parameter
Pattern Generator Clock
Frequency 1
Symbol
FM CLK
1
CHARACTERISTICS & SPECIFICATIONS
IN
AR
Y
3
Min
Typ
48
Max
(TBD)
Unit
MHz
Test Conditions
VDD = 3.3 V
Pattern generator clock (XRD/MCLK) frequency has to be at least 3 times SCLK frequency,
when both pattern generator and SPI are used.
3.2.3
8-bit Parallel Interface
TA = +85 ◦ C
8-bit Parallel Mode Clock
Frequency 1 (Write)
Min
FXW R
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Test Conditions
VDD = 1.5 V, XWR = VDD
VDD = 1.8 V, XWR = VDD
VDD = 3.0 V, XWR = VDD
VDD = 3.3 V, XWR = VDD
VDD = 1.5 V, XRD = VDD
VDD = 1.8 V, XRD = VDD
VDD = 3.0 V, XRD = VDD
VDD = 3.3 V, XRD = VDD
DC Characteristics
PR
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage at IO = -1.0 mA
Low-Level Output Voltage at IO = 1.0 mA
Input Leakage Current at any I/O pin
Rise Time of All Output Pins, Load = 50 pF
RAM Data Retention Voltage 2
2
Max
6
9
15
15
24
24
30
30
8-bit parallel interface clock is logical and of XWR and XRD/MCLK input pins.
3.3
1
Typ
EL
1
Symbol
FXRD
IM
Parameter
8-bit Parallel Mode Clock
Frequency 1 (Read)
Min
0.7×VDD
-0.2
0.7×VDD
Typ
Max
VDD+0.31
0.3×VDD
0.3×VDD
1.0
50
-1.0
1.0
Unit
V
V
V
V
µA
ns
V
Must not exceed 3.6V
This is the limit to which VDD can be lowered without losing RAM data.
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3.4
Current Consumption
CHARACTERISTICS & SPECIFICATIONS
IN
AR
Y
3
TA = +25 ◦ C, XCS=XCSPAR=VDD, XRESET=XWR=XRD/MCLK=SCLK=GND, other inputs
connected to VDD or GND.
Parameter
Stand-by Current
3.4.1
Min
Typ
35
210
165
105
105
Max
SPI Mode
VDD = 3.3 V, TA = +85 ◦ C
Min
Test Conditions
VDD = 1.95 V - 3.6 V
VDD = 1.8 V - 1.9 V
VDD = 1.7 V
VDD = 1.5 V
VDD = 3.3 V, TA = +85 ◦ C
Typ
VDD Current, SPI Dual Output Read
VDD Current, SPI Quad Output Read
VDD Current, SPI Single Port Write
& Read, Two Patterns1
0.1
0.6
1.3
Unit
µA
µA
µA
mA
mA
mA
mA
mA
Test Conditions
FSCLK = 1 MHz, SO = 0
FSCLK = 10 MHz, SO = 0
FSCLK = 24 MHz, SO = 0
FSCLK = 24 MHz, SO = 0
FSCLK = 24 MHz, SO = 0
FSCLK = 1 MHz, TA = +25 ◦ C
FSCLK = 10 MHz, TA = +25 ◦ C
FSCLK = 24 MHz, TA = +25 ◦ C
Current is heavily data-dependent.
3.4.2
EL
1
Max
130
325
900
1.05
1.20
IM
Parameter
VDD Current, SPI Single Output Read
Unit
µA
µA
µA
µA
µA
Pattern Generator Mode
VDD = 3.3 V, TA = +85 ◦ C
PR
Parameter
VDD Current, Pattern Generator
On, A5h Pattern
VDD Current, Pattern Generator
On, SPI Single Port Operations,
Moving Asteroids-Type Graphic
Version: 0.6, 2012-06-14
Min
Typ
1.0 - 2.5
Max
3.6
Unit
mA
mA
Test Conditions
FM CLK = 48 MHz,
No Load On PIOs
FM CLK = 48 MHz, 8-divider On,
FSCLK = 12 MHz, No Load
on PIOs, TA = +25 ◦ C
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3.4.3
8-bit Parallel Interface Mode
VDD = 3.3 V, TA = +85 ◦ C
Parameter
Current, Parallel Read
Min
Current, Parallel Read
& Write, Increasing Data1
1
Typ
5.0
10.8
14.7
Current is heavily data-dependent.
3.5
3.5.1
AC Characteristics
General
Max
220
700
1.05
Unit
µA
µA
mA
mA
mA
mA
Test Conditions
FXRD = 1 MHz, Data Out = 00h
FXRD = 10 MHz, Data Out = 00h
FXRD = 15 MHz, Data Out = 00h
FXRD = FXW R = 1 MHz, TA = +25 ◦ C
FXRD = FXW R = 10MHz, TA = +25 ◦ C
FXRD = FXW R = 15MHz, TA = +25 ◦ C
IM
VDD = 3.3 V, TA = -40 ... +85 ◦ C
CHARACTERISTICS & SPECIFICATIONS
IN
AR
Y
3
Min
0.45 ∗ TM AX
0.45 ∗ TM AX
5
3
0
Max
7
7
9
Unit
ns
ns
ns
ns
ns
ns
ns
ns
TM AX is the minimum clock cycle time in each mode.
PR
1
Symbol
Tclkh
Tclkl
Tds
Tdh
Tdis
Tv
Tvpio
Toh
EL
Parameter
Clock High Time 1
Clock Low Time 1
Data In Setup Time
Data In Hold Time
Output Disable Time
Output Valid Time
Output Valid Time of PIO4-7
Output Hold Time
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3.5.2
SPI Mode
VDD = 3.3 V, TA = -40 ... +85 ◦ C
Symbol
Txcsh
Txcsls
Txcslh
Txcshs
Txcshh
Txhls
Txhlh
Txhhs
Txhhh
Txhlz
Txhhz
Txwls
Txwlh
Txwhs
Txwhh
Min
14
6
5
8
0.5 ∗ TSCLK + 5
5
3
5
3
6
XCS
Txcsls
6
Txcslh
Tclkh
SCLK
SO
Tclkl
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Txcsh
Txcshh
Txcshs
Tdh
EL
Tds
Max
5
3
5
3
IM
Parameter
XCS High Time
XCS Low Setup Time
XCS Low Hold Time
XCS High Setup Time
XCS High Hold Time
XHOLD Low Setup Time
XHOLD Low Hold Time
XHOLD High Setup Time
XHOLD High Hold Time
XHOLD Low To Output High-Z
XHOLD High To Output Low-Z
XWP Low Setup Time
XWP Low Hold Time
XWP High Setup Time
XWP High Hold Time
SI
CHARACTERISTICS & SPECIFICATIONS
IN
AR
Y
3
MSB
High−Impedance
PR
Figure 3: SPI Input Timing
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XCS
SCLK
SI
Toh
Tv
CHARACTERISTICS & SPECIFICATIONS
IN
AR
Y
3
Tv
Tdis
SO
High−Impedance
High−Impedance
IM
Figure 4: SPI Output Timing
XCS
EL
XHOLD
Txhls
Txhhh
Txhhs
Txhlh
SCLK
PR
SI
SO
High−Impedance
Figure 5: XHOLD Timing, SPI and Dual-I/O Input Modes
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CHARACTERISTICS & SPECIFICATIONS
IN
AR
Y
3
XCS
XHOLD
Txhls
Txhhs
Txhhh
Txhlh
SCLK
SI
Txhhz
Txhlz
SO
High−Impedance
High−Impedance
High−Impedance
IM
Figure 6: XHOLD Timing, SPI and Dual-I/O Output Modes
EL
XCS
XWP
Txwls
Txwhh
Txwhs
Txwlh
SCLK
PR
SI
SO
High−Impedance
Figure 7: XWP Timing, SPI and Dual-I/O Modes
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3.5.3
Pattern Generator Mode
VDD = 3.3 V, TA = -40 ... +85 ◦ C
Parameter
XRESET Active Time
XRESET Inactive to Ready
IRQ High-Z To Output
PIO4-7 To Pattern Generator Output
IRQ Output To High-Z
PIO4-7 From Pattern Generator Output
IRQ Low From SCLK Rising Edge
XRESET
Txresl
XRD/MCLK
CHARACTERISTICS & SPECIFICATIONS
IN
AR
Y
3
Symbol
Txresl
Txresv
Tirqzo
Min
0.5
Max
4 ∗ TXRD/M CLK
7*TM CLK
Unit
µs
ns
ns
Tirqoz
7*TM CLK
ns
Tirql
4*TM CLK
ns
IM
Txresv
On−chip XRESET to Pattern Generator
and to 8−Bit Parallel Interface blocks
PR
EL
Figure 8: XRESET Timing
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XCS
Pattern generator enable command
SCLK
Tirqzo
Pattern generator disable command
Tirql
MCLK
Output
Tirqoz
IM
High−Impedance or GPIO Mode
PIO7
High−Impedance or GPIO Mode
Output
High−Impedance or GPIO Mode
Output
High−Impedance or GPIO Mode
Output
PIO6
PIO5
EL
PIO4
High−Impedance
IRQ
CHARACTERISTICS & SPECIFICATIONS
IN
AR
Y
3
Output
PR
Figure 9: Pattern Generator Timing
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3.5.4
8-bit Parallel Interface Mode
VDD = 3.3 V, TA = -40 ... +85 ◦ C
Symbol
Txresl
Txresv
Txcph
Txcpls
Txcplh
Txcphs
Txcphh
Txwrls
Txwrlh
Txwrhs
Txwrhh
Txrdls
Txrdlh
Txrdhs
Txrdhh
Min
0.5
Max
4 ∗ TXRD/M CLK
20
5
0.5 ∗ TXRD/M CLK + 2
5
0.5 ∗ TXRD/M CLK + 2
6
2
6
2
6
2
6
2
IM
Parameter
XRESET Active Time
XRESET Inactive to Ready
XCSPAR High Time
XCSPAR Low Setup Time
XCSPAR Low Hold Time
XCSPAR High Setup Time
XCSPAR High Hold Time
XWR Low Setup Time
XWR Low Hold Time
XWR High Setup Time
XWR High Hold Time
XRD Low Setup Time
XRD Low Hold Time
XRD High Setup Time
XRD High Hold Time
CHARACTERISTICS & SPECIFICATIONS
IN
AR
Y
3
XCSPAR
Txcpls
Txcph
Txcplh
Tclkh
XWR
Txcphh
Tclkl
Txcphs
Txrdhh
EL
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Txrdhs
Txrdls
XRD/MCLK
Tdis
Tds
IO7−0
Tdh
Txrdlh
Tv
High−Impedance
Input
High−Impedance
Output
Input
PR
Figure 10: 8-bit Parallel Interface Timing, XRD as clock enable
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CHARACTERISTICS & SPECIFICATIONS
IN
AR
Y
3
Txcph
XCSPAR
Txcpls
Txcplh
Tclkh
XRD/MCLK
Txcphh
Tclkl
Txcphs
Txwrhh
Txwrhs
Txwrls
XWR
Tdis
Tds
IO7−0
Tdh
High−Impedance
Txwrlh
Tv
High−Impedance
Input
Output
Input
Figure 11: 8-bit Parallel Interface Timing, XWR as clock enable
AC Test Conditions
PR
EL
IM
AC Waveform:
Input Pulse Level
0.1×VDD to 0.9×VDD
Input Rise/Fall Time
5 ns
◦
Operating Temperature
-40 C to +85 ◦ C
CL = (TBD) pF
Timing Measurement Reference Level:
Input
0.5×VDD
Output
0.5×VDD
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4
4.1
PACKAGES AND PIN DESCRIPTIONS
IN
AR
Y
4
Packages and Pin Descriptions
Wide SOIC16
VS23S010-SW16 is in Wide SOIC16 package (300 mils).
Wide SOIC16 is a lead (Pb) free and also RoHS compliant package. RoHS is a short name of
Directive 2002/95/EC on the restriction of the use of certain hazardous substances in electrical
and electronic equipment.
Wide SOIC16 package dimensions can be found at http://www.vlsi.fi/.
The VS23S010-SW16 has the following pin out:
Pin
Type
DIOS
VCC
XCSPAR/IRQ
2
3
PWR
DIOS
XWR
XRD/MCLK
4
5
DIS
DIS
XRESET
6
XCS
SO/IO1
7
8
XWP/IO2
9
GND
PIO4
10
11
PIO5
PIO6
DIS
DIS
DIO
DIOS
GND
DIO
12
DIO
13
DIO
14
DIO
PR
PIO7
Function
Active low Hold for SPI and Dual-I/O SPI /
IO3 for Quad-I/O SPI and 8-bit parallel interface
Power supply
Active low chip select of 8-bit parallel interface /
IRQ output of pattern generator
One input for clock of 8-bit parallel interface
Another input for clock of 8-bit parallel interface /
clock for pattern generator
Active low reset for 8-bit parallel interface and pattern
generator
Active low chip select for SPI
SO for SPI /
IO1 for Dual-I/O and Quad-I/O SPI and 8-bit parallel
interface
Active low write protect for SPI and Dual-I/O SPI /
IO2 for Quad-I/O SPI and 8-bit parallel interface
Ground
IO4 for 8-bit parallel interface /
OUT0 of pattern generator /
GPIO0
IO5 for 8-bit parallel interface /
OUT1 of pattern generator /
GPIO1
IO6 for 8-bit parallel interface /
OUT2 of pattern generator /
GPIO2
IO7 for 8-bit parallel interface /
OUT3 of pattern generator /
GPIO3
SI for SPI /
IO0 for Dual-I/O and Quad-I/O SPI and 8-bit parallel
interface
SCLK for SPI
IM
XHOLD/IO3
SOIC16
Pin
1
EL
Pad Name
SI/IO0
15
DIO
SCLK
16
DIS
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Pin types:
Description
Digital input, Schmitt-trigger
Digital input/output
Digital input/output, Schmitt-trigger
Not connected
Power supply pin
Ground pin
PR
EL
IM
Type
DIS
DIO
DIOS
NC
PWR
GND
PACKAGES AND PIN DESCRIPTIONS
IN
AR
Y
4
Version: 0.6, 2012-06-14
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5
Connection Guidelines
CONNECTION GUIDELINES
IN
AR
Y
5
If XHOLD is unused, connect a pull-up resistor to it. Also if XWP is unused, connect a pull-up
resistor to it.
If 8-bit parallel interface is unused, connect a pull-up resistor to XCSPAR/IRQ pin. Also tie XWR
to low. If 8-bit parallel interface is active, tie XRD/MCLK to high and use XWR as clock input.
Another possibility is to tie XWR to high and use XRD/MCLK as clock input.
If 8-bit parallel interface and pattern generator are not used, tie XRD/MCLK to high or low. Also
tie XRESET to low. If pattern generator is active, use XRD/MCLK as clock.
PR
EL
IM
Unused PIO pins should have a pull-down or pull-up resistor.
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6
Device Operation
DEVICE OPERATION
IN
AR
Y
6
The device consists of four main blocks: SPI, Pattern Generator, 8-bit Parallel Interface and
SRAM. SPI and Pattern Generator can be enabled simultaneously and they must both be disabled when 8-bit Parallel Interface is used. The SRAM can be written and read by SPI and 8-bit
Parallel Interface. The pattern generator can only read the SRAM.
XCSPAR/IRQ
Pattern Generator
XRD/MCLK
XRESET
XWR
SI/IO0
SO/IO1
XWP/IO2
SPI
XHOLD/IO3
PIO4−7
4
SCLK
SRAM
131072 x 8 bits
IM
8−bit Parallel Interface
XCS
6.1
EL
Figure 12: Device Organization
SPI
PR
The VS23S010 and pattern generator are controlled by a set instructions that are sent from
a host controller, commonly referred as SPI Master. The SPI Master communicates with the
VS23S010 via the SPI bus which is comprised of four signal lines: Chip Select (XCS), Serial
Clock (SCLK), Serial Input (SI) and Serial Output (SO).
The VS23S010 supports SPI protocol operation mode 0, which is very commonly used. Data
is always latched in on the rising edge of the SCLK and always output on the falling edge of the
SCLK.
SPI block does not have a separate Reset pin. There is an on-chip power-up delay logic, which
is used to reset the selected SPI registers: Pattern Generator Frame Length Register, Pattern
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XCS
SCLK
SI
MSB
DEVICE OPERATION
IN
AR
Y
6
LSB
SO
MSB
LSB
Figure 13: SPI Mode 0
Generator Control Register and GPIO Control Register. SPI block logic is clocked by the SCLK
pin. Following is a table describing the registers of the VS23S010.
6.2
Symbol
STATUS
ID
GPIOCTRL
GPIOSTATE
PGLENGTH
PGCTRL
PGCNT
R/W
R
R
RW
R
RW
RW
R
Default Value
80h
ABh
00h
Initialization
Power-Up
Power-Up
Power-Up
0000h
00h
000000h
Power-Up
Power-Up
Power-Up
IM
Register
Status
Manufacturer and Device ID
GPIO Control
GPIO State
Pattern Generator Frame Length
Pattern Generator Control
Pattern Generator Counter
Dual-I/O and Quad-I/O Operation
EL
In Dual-I/O SPI mode two data bits are read or written during one SCLK cycle. SI/IO0 pin is
the lower bit and SO/IO1 pin is the higher bit in Dual-I/O mode. Both pins are inputs during the
write and outputs during the read.
In Quad-I/O SPI mode four data bits are read or written during one SCLK cycle. SI/IO0 pin is
the lowest bit, SO/IO1 pin is the second bit, XWP/IO2 is the third bit and finally XHOLD/IO3 is
the fourth bit in Quad-I/O mode. The pins are inputs during the write and outputs during the
read.
Pattern Generator
PR
6.3
Pattern Generator outputs two or four bit data from SRAM per pattern generator clock cycle.
8-bit byte is output LSB part first. Pins PIO4-7 are the pattern generator outputs. For the
synchronization of data stream there is a programmable IRQ output.
The pattern generator clock frequency can be divided from the XRD/MCLK pin frequency by
2,4 or 8. This allows the use of wide range of XRD/MCLK frequencies.
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DEVICE OPERATION
IN
AR
Y
6
SPI can also be used to access the SRAM when pattern generator is enabled. When both
blocks are active, there is a limitation to SCLK frequency: it has to be 1/3 or less of the
XRD/MCLK frequency.
Figure 14 shows the data organization of the pattern generator outputs in the two modes. IRQ
timing principle is also shown. IRQ is deasserted by rising edge of the SCLK pin.
The pattern generator logic is reset by setting the XRESET pin low. Setting the XRESET pin
high exits the reset state. Entering the reset state is done immediately asynchronously and
exiting the reset state requires three XRD/MCLK cycles. Figure 15 shows the timing of the
XRESET pin and active-low, on-chip reset signal.
XRD/MCLK
D3
D7
D3
PIO6
D2
D6
D2
PIO5
D1
D5
D1
PIO4
D0
D4
D0
IRQ
SCLK
D7
D1
D3
D5
D7
D1
D3
D5
D7
D6
D0
D2
D4
D6
D0
D2
D4
D6
D5
D4
IM
PIO7
Four−bit mode
Two−bit mode
Figure 14: Pattern Generator Modes
Three XRD/MCLK Cycles
EL
XRESET
XRD/MCLK
XRESET to Pattern Generator
and to 8−Bit Parallel Interface blocks
PR
Figure 15: Timing of on-chip reset signal
6.3.1
Known Issues
In pattern generator mode, the largest size of the pattern is 64 kilobytes (the maximum pattern
end address is 0FFFFh).
Version: 0.6, 2012-06-14
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6.4
DEVICE OPERATION
IN
AR
Y
6
8-Bit Parallel Interface
In parallel mode it is possible to write and read SRAM in the blocks of four bytes. 8-bit parallel
interface is a stand-alone function and during its operation SPI and pattern generator have to
be inactive. Clock for the parallel interface is generated on-chip by the logical and of the XWR
and XRD/MCLK pin states. Data pins in this mode are from LSB: SI/IO0, SO/IO1, XWP/IO2,
XHOLD/IO3, PIO4, PIO5, PIO6 and PIO7. They are inputs in instruction, address and write
phase and outputs in SRAM data read phase.
Parallel interface timing is similar to SPI: Data is always latched in on the rising edge of the
clock and always output on the falling edge of the clock. When pins are switched from input
to output, there is a delay of one clock cycle before the outputs are driven by VS23S010. The
reset logic and timing for the 8-Bit Parallel Interface is the same as for the pattern generator.
XCSPAR
XRD/MCLK
PIO7
D7
D7
PIO6
D6
D6
PIO5
D5
D5
PIO4
D4
D4
XHOLD/IO3
D3
D3
XWP/IO2
D2
SO/IO1
SI/IO0
IM
XWR
D7
D7
D7
D7
D7
D7
D7
D7
D7
D6
D6
D6
D6
D6
D6
D6
D6
D6
D6
D5
D5
D5
D5
D5
D5
D5
D5
D5
D5
D4
D4
D4
D4
D4
D4
D4
D4
D4
D4
D3
D3
D3
D3
D3
D3
D3
D3
D3
D3
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D2
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D1
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
D0
EL
D7
PR
XCS
Input data
Output data
Figure 16: 8-Bit Parallel Interface Signals
Version: 0.6, 2012-06-14
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7
SPI COMMANDS AND ADDRESSING
IN
AR
Y
7
SPI Commands and Addressing
A valid SPI instruction or operation is started by first asserting the XCS pin. After that, the
host controller clocks out a valid 8-bit opcode on the SPI bus. Following the opcode instruction
dependent information (address or data bytes) are sent by the host controller. Data is sent MSB
first. Operation is ended by deasserting the XCS pin.
Opcodes which are not supported by the VS23S010 will be ignored. Also if XCS is deasserted
when the whole byte is not clocked out the operation of the byte in question will be aborted.
Addressing of the VS23S010 requires three bytes to be sent, address bits A23-A0. Since the
maximum address is 1FFFFh the address bits A23 to A17 will be ignored by the device.
Opcode
Data Bytes
0000 0011
0011 1011
0110 1011
3
3
3
1+
1+
1+
02h
A2h
32h
0000 0010
1010 0010
0011 0010
3
3
3
1+
1+
1+
05h
9Fh
84h
82h
86h
0000 0101
1001 1111
1000 0100
1000 0010
1000 0110
0
0
0
0
0
1+
1+
1+
1+
1+
0101 0111
0010 0001
0101 0101
0100 0001
0101 0011
0
0
0
0
0
2
2
1+
1+
3
EL
57h
21h
55h
41h
53h
SPI Read Commands
PR
7.1
Address Bytes
03h
3Bh
6Bh
IM
Command
Read Commands
Read
Dual-Output Read
Quad-Output Read
Write Commands
Write
Dual-Input Write
Quad-Input Write
Miscellaneous Commands
Read Status Register
Read Manufacturer and Device ID
Read GPIO Control Register
Write GPIO Control Register
Read GPIO State Register
Pattern Generator Commands
Read Pattern Generator Frame Length
Write Pattern Generator Frame Length
Read Pattern Generator Control Register
Write Pattern Generator Control Register
Read Pattern Generator Counter Register
The Read command can be used to sequentially read a continuous stream data from the device
by providing clock signal once the initial starting address has been specified. The device has
on internal address counter that increments on every cycle.
To perform a read operation, XCS must first be asserted and read opcode must be clocked into
device. After the opcode three address bytes are clocked into the device to specify the starting
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SPI COMMANDS AND ADDRESSING
IN
AR
Y
7
address location of the first byte to read within SRAM.
After address bytes additional SCLK clock cycles will result in data being output on the SO pin.
Data is output MSB first. When the last byte (1FFFFh) of the SRAM has been read, the reading
will continue from the beginning of the array (00000h).
Deasserting the XCS pin will terminate the read operation and SO pin goes to high-impedance
state.
XCS
SCLK
Opcode
SI
0
0
0
0
0
MSB
Address A23−A0
0
1
1 A A A A A
MSB
A A A
Data byte 1
High−Impedance
SO
D D D D D D D D D D
MSB
MSB
7.1.1
IM
Figure 17: SPI Read
Dual-Output Read
Dual-Output Read is similar to Read command except that two bits of data are clocked out of
the device on every clock cycle.
EL
To perform a Dual-Output Read XCS pin is first asserted. After that opcode 3Bh and three
address bytes are sent by the host controller.
After the three address bytes are clocked in, the device will output data on SI/IO0 and SO/IO1
pins. The data is clocked out MSB first and MSB is on pin SO/IO1. During the first clock cycle
bit6 will be on SI/IO0 pin, on the next cycle bit5 is on SO/IO1 and bit4 on SI/IO0 and so on.
When the last byte (1FFFFh) of the SRAM has been read, the reading will continue from the
beginning of the array (00000h).
PR
Deasserting the XCS pin will terminate the read operation and SI/IO0 and SO/IO1 pins go to
high-impedance state.
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XCS
SCLK
Opcode
SI/IO0
0
0
1
1
1
Address A23−A0
0
1
MSB
1 A A A A A
MSB
High−Impedance
SO/IO1
SPI COMMANDS AND ADDRESSING
IN
AR
Y
7
A A A
Data byte 1
D6
D4
D2
D0
D7
D5
D3
D1
MSB
Data byte 2
D6
D4
D2
D0
D7
D5
D3
D1
MSB
D6
D4
D7
D5
MSB
Figure 18: SPI Dual-Output Read
7.1.2
Quad-Output Read
Quad-Output Read is similar to Read command except that four bits of data are clocked out of
the device on every clock cycle.
IM
To perform a Quad-Output Read XCS pin is first asserted. After that opcode 6Bh and three
address bytes are sent by the host controller.
EL
After the three address bytes are clocked in, the device will output data on SI/IO0, SO/IO1,
XWP/IO2 and XHOLD/IO3 pins. The data is clocked out MSB first and MSB is on pin XHOLD/IO3.
During the first clock cycle bit6 will be on XWP/IO2 pin, bit5 on pin SO/IO1 and bit4 on SI/IO0,
on the next cycle bit3 is on XHOLD/IO3 and bit2 on XWP/IO2 and so on. When the last byte
(1FFFFh) of the SRAM has been read, the reading will continue from the beginning of the array
(00000h).
Deasserting the XCS pin will terminate the read operation and SI/IO0, SO/IO1, XWP/IO2 and
XHOLD/IO3 pins go to high-impedance state.
7.2
SPI Write Commands
PR
Prior to writing the device must be selected by bringing XCS pin low. Once the device is selected the Write command can be started by issuing a Write instruction (opcode 02h) followed
by a 23-bit address. The device works in sequential mode where after the initial data byte
additional bytes can be clocked into device. The internal address pointer is automatically incremented. When the internal address pointer reaches its maximum value (1FFFFh) it rolls over
to 00000h. This allows the operation to continue indefinitely, however, previous data will be
overwritten.
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XCS
SCLK
Opcode
SI/IO0
0
1
1
0
SPI COMMANDS AND ADDRESSING
IN
AR
Y
7
Data
byte 1
Address A23−A0
1
0
1
1 A A A A A
MSB
MSB
High−Impedance
SO/IO1
High−Impedance
XWP/IO2
High−Impedance
XHOLD/IO3
A A A
Data
byte 2
D4
D0
D4
D0
D4
D0
D4
D0
D4
D0
D5
D1
D5
D1
D5
D1
D5
D1
D5
D1
D6
D2
D6
D2
D6
D2
D6
D2
D6
D2
D7
D3
D7
D3
D7
D3
D7
D3
D7
D3
MSB
MSB
Figure 19: SPI Quad-Output Read
SCLK
IM
XCS
Opcode
SI
0
0
0
0
SO
0
0
1
0 A A A A A
Data in
A A A D D D D D D D D
MSB
MSB
EL
MSB
Address A23−A0
High−Impedance
Figure 20: SPI Write
7.2.1
Dual-Input Write
PR
Dual-Input Write command is similar to Write command except that two bits of data are clocked
in the device on every clock cycle and opcode is A2h.
7.2.2
Quad-Input Write
Quad-Input Write command is similar to Write command except that four bits of data are clocked
in the device on every clock cycle and opcode is 32h.
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XCS
SCLK
Opcode
SI/IO0
1
0
1
0
0
Address A23−A0
0
1
0 A A A A A
MSB
MSB
High−Impedance
SO/IO1
SPI COMMANDS AND ADDRESSING
IN
AR
Y
7
Data byte in
A A A
Data byte in
D6
D4
D2
D0
D7
D5
D3
D1
MSB
D6
D4
D2
D0
D7
D5
D3
D1
MSB
Figure 21: SPI Dual-Input Write
XCS
SCLK
Opcode
0
0
1
MSB
SO/IO1
0
0
1
0 A A A A A
A A A
XHOLD/IO3
Data
Data
Data
Data
byte in byte in byte in byte in
D4
D0
D4
D0
D4
D0
D4
D0
D5
D1
D5
D1
D5
D1
D5
D1
D6
D2
D6
D2
D6
D2
D6
D2
D7
D3
D7
D3
D7
D3
D7
D3
MSB
High−Impedance
High−Impedance
EL
XWP/IO2
1
IM
SI/IO0
Address A23−A0
High−Impedance
MSB
MSB
MSB
MSB
Figure 22: SPI Quad-Input Write
7.3
Read Status Register
PR
7.3.1
SPI Miscellaneous Commands
The Read Status command is started by asserting XCS pin. After that the host controller sends
the opcode, 05h. The device responds by clocking out a byte wide constant, value 80h. This
command is for compatibility and status register has no other information. When XCS pin is
deasserted, the clocking out of the constant is ended and SO pin goes to high-impedance state.
Note, Status Register is read-only register.
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Output Data
80h
Status Register Value
Default
XCS
SCLK
Opcode
SI
0
0
0
0
0
1
MSB
SPI COMMANDS AND ADDRESSING
IN
AR
Y
7
0
1
Data byte 1
High−Impedance
SO
1
0
0
0
0
MSB
0
0
0
1
0
MSB
7.3.2
IM
Figure 23: SPI Read Status Register
Read Manufacturer and Device ID
EL
The Read Manufacturer and Device ID command is started by asserting XCS pin. After that
the host controller sends the opcode, 9Fh. The device responds by clocking out a byte wide
constant, value ABh. When XCS pin is deasserted, the clocking out of the constant is ended
and SO pin goes to high-impedance state.
Note, Manufacturer and Device ID is read-only register.
Output Data
ABh
Read GPIO Control Register
PR
7.3.3
Manufacturer and Device ID Value
Default
The Read GPIO Control Register command is started by asserting XCS pin. After that the
host controller sends the opcode, 84h. The device responds by clocking out a byte wide value.
When XCS pin is deasserted, the clocking out of the register value is ended and SO pin goes
to high-impedance state.
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XCS
SCLK
Opcode
SI
1
0
0
1
1
1
1
MSB
SPI COMMANDS AND ADDRESSING
IN
AR
Y
7
1
Data byte 1
High−Impedance
SO
1
0
1
0
1
0
1
MSB
1
1
0
MSB
Figure 24: SPI Read Manufacturer and Device ID
SCLK
IM
XCS
Opcode
1
0
0
0
0
1
0
0
EL
SI
MSB
SO
High−Impedance
Data byte 1
D D D D D D D D D D
MSB
MSB
Figure 25: SPI Read GPIO Control
3-0
PIOnD
Name
PIO7-4 Direction
Type
RW
PIOnO
PIO7-4 Output State
RW
PR
Bits
7-4
Version: 0.6, 2012-06-14
0
1
0
1
Description
Input (default)
Output
Low (default)
High
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AR
Y
7
PIOnD PIOnD bits set the direction of PIO7-4 pins, when pattern generator is not used. Default value “0” sets a PIO as input. Bit 7 sets PIO7 direction, bit 6 PIO6 direction and so on.
High value “1” sets the PIO as output with a value set in PIOnO bits.
PIOnO PIOnO bits set the PIO7-4 output state. Default is “0”, which sets the state low. Bit 3
sets PIO7 output state, bit 3 PIO6 output state etc.
High value “1” sets the corresponding PIO state to high.
Note, that enabling pattern generator sets PIO7-4 pins as outputs of pattern generator. Also
8-bit parallel interface overrides GPIO functionality of PIO7-4.
7.3.4
Write GPIO Control Register
Bit 7
PIO7D
Write GPIO Control Register Format
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PIO5D PIO4D PIO7O PIO6O PIO5O
Bit 0
PIO4O
Read GPIO State Register
EL
7.3.5
Bit 6
PIO6D
IM
To write the GPIO Control register XCS pin must be first asserted and opcode 82h clocked into
the device. After that byte-wide value is clocked in the device via SI pin. The value is input
MSB (bit 7) first. The state of the PIO7-4 pins is changed according to the received byte after
the SCLK goes low.
The Read GPIO State Register command is started by asserting XCS pin. After that the host
controller sends the opcode, 86h. The device responds by clocking out a byte wide value.
When XCS pin is deasserted, the clocking out of the register value is ended and SO pin goes
to high-impedance state.
GPIO State Description
PIO7 logic state
PIO6 logic state
PIO5 logic state
PIO4 logic state
XHOLD logic state
XWP logic state
don’t cares, 0h
PR
Output Bit
7
6
5
4
3
2
1-0
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XCS
SCLK
Opcode
SI
1
0
0
0
0
MSB
SPI COMMANDS AND ADDRESSING
IN
AR
Y
7
Data in
0
1
0 D D D D D D D D
MSB
High−Impedance
SO
High−Impedance or output
IM
PIO7−4
Figure 26: SPI Write GPIO Control
EL
XCS
SCLK
Opcode
SI
1
0
0
0
0
1
1
0
PR
MSB
SO
Version: 0.6, 2012-06-14
Data byte 1
High−Impedance
D D D D D D D D D D
MSB
MSB
Figure 27: SPI Read GPIO State
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8
PATTERN GENERATOR COMMANDS
IN
AR
Y
8
Pattern Generator Commands
Pattern generator is controlled via SPI. Pattern generator activation is started by first writing the
desired value to Pattern Generator Control Register. After that a write of non-zero value to Pattern Generator Frame Length Register starts the pattern generator. The pattern generator can
only be disabled by writing zero to Pattern Generator Frame Length Register. Setting XRESET
pin to low stops the pattern generation logic, but the pattern generator starts immediately after
the XRESET pin is set to high again (Pattern Generator Frame Length register is not reset).
Pattern generator uses XRD/MCLK pin as clock.
8.1
Read Pattern Generator Frame Length
The two-byte Pattern Generator Frame Length register can be read to determine, if pattern
generator is enabled and to determine the Pattern Generator Frame Length value.
IM
To read the Pattern Generator Frame Length register XCS pin must be first asserted and opcode 57h clocked into the device. After that two byte value is clocked out from the device via
SO pin. The two byte value is output MSB (bit 15) first. When XCS pin is deasserted, the
clocking out of data is ended and SO pin goes to high-impedance state.
If Pattern Generator Frame length value is zero, then pattern generator is disabled.
Output Data
0000h
Non-zero value
Pattern Generator Frame Length Value and Description
Default after power-up, pattern generator is disabled
Pattern generator is enabled
EL
XCS
SCLK
Opcode
SI
0
1
0
1
0
1
1
1
MSB
PR
Data byte 1
SO
High−Impedance
Data byte 2
D D D D D D D D D D D D D D D D
MSB
Figure 28: SPI Read Pattern Generator Frame Length
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8.2
PATTERN GENERATOR COMMANDS
IN
AR
Y
8
Write Pattern Generator Frame Length
By writing a value other than zero to the two-byte Pattern Generator Frame Length register the
pattern generator is enabled. When you are enabling the pattern generator, first write a correct
value to Pattern Generator Control Register and then after that enable the pattern generator.
Disabling of the pattern generator is done by writing zero value to Pattern Generator Frame
Length register. After the device power-up the Pattern Generator Frame Length register has
value zero.
To write the Pattern Generator Frame Length register XCS pin must be first asserted and opcode 21h clocked into the device. After that two byte value is clocked in the device via SI
pin. The two byte value is input MSB (bit 15) first. When XCS pin is deasserted the pattern
generator output PIO4-7 will be disabled or enabled after 5 to 7 MCLK cycles.
XCS
Pattern generator enable command
SCLK
5 − 7 MCLK cycles
IM
MCLK
Data from
Data from
Data from
address 0h
address 1h
address 2h
D3
D3
D3
High−Impedance or GPIO Mode
PIO7
D7
MSB
D7
MSB
D7
MSB
High−Impedance or GPIO Mode
PIO6
D2
D6
D2
D6
D2
D6
D1
D5
D1
D5
D1
D5
D0
D4
D0
D4
D0
D4
High−Impedance or GPIO Mode
EL
PIO5
High−Impedance or GPIO Mode
PIO4
High−Impedance
IRQ
Output
PR
Pattern Generator Control Register Value is 0h.
Figure 29: Pattern Generator Start, Four-output Mode
The Pattern Generator Frame Length register value determines the SRAM address, from which
the data is output, when the IRQ pin goes to go high. The output data pixel, after which IRQ
is asserted is (P atternGeneratorF rameLength) ∗ 4 + 3. The data byte is read from SRAM
address
(P atternGeneratorF rameLength)∗2+1. The IRQ pin can be deasserted by the host controller
by setting the SCLK pin high. There is a small delay (2 to 4 MCLK cycles) from SCLK rise to
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XCS
Pattern generator enable command
SCLK
PATTERN GENERATOR COMMANDS
IN
AR
Y
8
5 − 7 MCLK cycles
MCLK
Data from
address 0h
High−Impedance or GPIO Mode
PIO7
Data from
address 1h
Data from
address 2h
D1 D3 D5 D7 D1 D3 D5 D7 D1 D3 D5 D7 D1
MSB
High−Impedance or GPIO Mode
PIO6
MSB
MSB
D0 D2 D4 D6 D0 D2 D4 D6 D0 D2 D4 D6 D0
High−Impedance or GPIO Mode
PIO5
High−Impedance or GPIO Mode
PIO4
High−Impedance
Output
Output
IM
IRQ
Output
Pattern Generator Control Register Value is 8h.
Figure 30: Pattern Generator Start, Two-output Mode
the device setting low the IRQ pin. Figure 31 shows the timing principle of IRQ.
PR
EL
Note, that if SPI is used, when pattern generator is enabled, SCLK frequency has to be 1/3rd
of MCLK frequency or less.
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MCLK
Data from
address 80Bh
PIO7
D7
D3
D7
MSB
D3
D7
MSB
D3
MSB
PIO6
D6
D2
D6
D2
PIO5
D5
D1
D5
D1
PIO4
D4
D0
D4
D0
PATTERN GENERATOR COMMANDS
IN
AR
Y
8
D3
Data from
address 80Dh
D7
D3
MSB
D6
D2
D6
D2
D6
D2
D5
D1
D5
D1
D5
D1
D4
D0
D4
D0
D4
D0
Pixel Pixel
1018h 1019h
2−4 MCLK cycles
IM
SCLK
D7
MSB
Pixel Pixel
1016h 1017h
IRQ
Data from
address 80Ch
Pattern Generator Control Register Value is 00h.
Pattern Generator Frame Length Register value is 0405h, so IRQ rises after
data for pixel 0405h * 4h + 3h = 1017h from SRAM address 0405h * 2h + 1h = 80Bh is output.
Figure 31: Pattern Generator IRQ Timing
EL
XCS
SCLK
Opcode
SI
0
0
1
0
0
MSB
0
0
Data in 2
1 D D D D D D D D D D D D D D D D
MSB
High−Impedance
PR
SO
Data in 1
Figure 32: SPI Write Pattern Generator Frame Length
8.3
Read Pattern Generator Control Register
The Read Pattern Generator Control Register command is started by asserting XCS pin. After
that the host controller sends the opcode, 55h. The device responds by clocking out a byte
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PATTERN GENERATOR COMMANDS
IN
AR
Y
8
wide value. When XCS pin is deasserted, the clocking out of the register value is ended and
SO pin goes to high-impedance state.
XCS
SCLK
Opcode
SI
0
1
0
1
0
1
MSB
0
1
Data byte 1
High−Impedance
SO
D D D D D D D D D D
MSB
MSB
Figure 33: SPI Read Pattern Generator Control
Name
Pattern Generator Mode
Type
RW
PGM
2
PGRC
Pattern Generator Counter Reset
RW
1
PGC8
Pattern Generator Clock 8-divider
RW
0
PGC4
Pattern Generator Clock 4-divider
RW
EL
IM
Bit
3
0
1
0
1
0
1
0
1
Description
Four-output mode (default)
Two-output mode
Counter is not reset (default)
Counter is reset
8-divider is disabled (default)
8-divider is enabled
4-divider is disabled (default)
4-divider is enabled
PGM Bit PGM bit controls the output data width and frequency of the pattern generator. In
default mode after power-up bit value is “0”, which means that all four outputs PIO4-7 are used.
PR
If bit is set to “1” only outputs PIO6-7 are used. Also the output frequency is twice the output
frequency of four-output mode so that the data throughput is same in both modes. In this mode
PIO4-5 are outputs, but their states are don’t cares.
PGRC Bit PGRC bit controls whether the pattern generator address counter is reset or not
when SRAM address defined by Pattern Generator Frame Length register is reached. In default
mode after power-up bit value is “0”, which means that pattern generator address counter is
not reset. Pattern generator address counter increments until last address 1FFFFh of SRAM
is reached and rolls then over to 00000h. In this mode the whole content of the SRAM will be
output by the device.
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PATTERN GENERATOR COMMANDS
IN
AR
Y
8
If PGRC bit is set to “1”, pattern generator address counter is reset when SRAM address
defined by Pattern Generator Frame Length register is reached.
PGC8 Bit PGC8 bit controls the output frequency of the pattern generator data. Default state
is “0” when a data bit stays for two MCLK cycles at the output in four-bit mode.
If PGC8 bit is set to “1” then a data bit stays for eight MCLK cycles at the output in four-bit
mode. This control bit makes it possible to use higher frequency clock at MCLK input.
PGC4 Bit PGC4 bit controls the output frequency of the pattern generator data. Default state
is “0” when a data bit stays for two MCLK cycles at the output in four-bit mode.
If PGC4 bit is set to “1” then a data bit stays for four MCLK cycles at the output in four-bit mode.
This control bit makes it possible to use higher frequency clock at MCLK input.
Note, that PGC8 and PGC4 bit are not allowed to be set “1” both at the same time.
Write Pattern Generator Control Register
IM
8.4
Pattern Generator Control Register values can be changed only when pattern generator is
disabled.
Bit 7
0
8.5
EL
To write the Pattern Generator Control register XCS pin must be first asserted and opcode 41h
clocked into the device. After that byte-wide value is clocked in the device via SI pin. The value
is input MSB (bit 7) first. Bits 7-4 of the byte are reserved and have to be always 0h.
Write Pattern Generator Control Register Format
Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
PGM PGRC PGC8 PGC 4
Read Pattern Generator Counter Register
PR
The Read Pattern Generator Counter Register command is started by asserting XCS pin. After
that the host controller sends the opcode, 53h. The device responds by clocking out a three
byte wide value. When XCS pin is deasserted, the clocking out of the register value is ended
and SO pin goes to high-impedance state.
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XCS
SCLK
Opcode
SI
0
1
0
0
0
PATTERN GENERATOR COMMANDS
IN
AR
Y
8
Data in
0
MSB
0
1
0
0
0
0 D D D D
MSB
High−Impedance
SO
EL
XCS
IM
Figure 34: SPI Write Pattern Generator Control
Pattern Counter Register Value is updated here
SCLK
Opcode
SI
0
1
0
1
0
0
1
1
MSB
PR
Data byte 1
SO
High−Impedance
0
0
0
0
0
Data byte 2
0 D D D D
Data byte 3
D D D D D D D D D
MSB
LSB
Figure 35: SPI Read Pattern Generator Counter
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9
8-BIT PARALLEL INTERFACE COMMANDS AND ADDRESSING
IN
AR
Y
9
8-Bit Parallel Interface Commands and Addressing
8-bit parallel interface is an 8080 and NAND Flash type interface. It is a stand-alone function
of the device and when it is used the SPI interface and pattern generator must be inactive. So,
XCS must be “1” and pattern generator must be disabled when 8-bit parallel interface is used.
A valid 8-bit interface operation is started by first asserting XCSPAR pin. After that the host
controller clocks out a valid 8-bit opcode. Following the opcode are three address bytes sent by
the host controller. If there is a write operation the host sends data bytes to the device. In read
operation the device starts clocking out data one clock cycle after the address. The operation
is ended by deasserting the XCSPAR pin.
9.1
8-Bit Parallel Interface Read
The Read command can be used to sequentially read a continuous stream data from the device
by providing clock signal once the initial starting address has been specified. The device has
on internal address counter that increments on every cycle.
IM
To perform a read operation, XCSPAR must first be asserted and read opcode 02h must be
clocked into device. After the opcode three address bytes are clocked into the device to specify
the starting address location of the first byte to read within SRAM. Note, that two LSBs of the
address have to be zeros always.
After address bytes additional clock cycles will result in data being output on the parallel interface. When the last byte (1FFFFh) of the SRAM has been read, the reading will continue from
the beginning of the array (00000h).
9.2
EL
Deasserting the XCSPAR pin will terminate the read operation and parallel interface goes to
high-impedance state.
8-Bit Parallel Interface Write
PR
Prior to writing the device must be selected by bringing XCSPAR pin low. Once the device is
selected the Write command can be started by issuing a Write instruction (opcode 02h) followed
by a 24-bit address. Note, that two LSBs of the address have to be zeros always.
The device works in sequential mode where after the initial data byte additional bytes can be
clocked into device. The internal address pointer is automatically incremented. When the
internal address pointer reaches its maximum value (1FFFFh) it rolls over to 00000h. This
allows the operation to continue indefinitely, however, previous data will be overwritten. Note,
that the amount of written data bytes has to be a multiple of four, e.g. 4, 8, 12, 16 and so on.
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8-BIT PARALLEL INTERFACE COMMANDS AND ADDRESSING
XCSPAR
XRD/MCLK
XWR
IN
AR
Y
9
Data Data Data Data
byte 1 byte 2 byte 3 byte 4
0
A23
A15
A7
D7
D7
D7
D7
D7
D7
D7
D7
PIO6
0
A22
A14
A6
D6
D6
D6
D6
D6
D6
D6
D6
PIO5
0
A21
A13
A5
D5
D5
D5
D5
D5
D5
D5
D5
PIO4
0
A20
A12
A4
D4
D4
D4
D4
D4
D4
D4
D4
XHOLD/IO3
0
A19
A11
A3
D3
D3
D3
D3
D3
D3
D3
D3
XWP/IO2
0
A18
A10
A2
D2
D2
D2
D2
D2
D2
D2
D2
SO/IO1
1
A17
A9
A1
D1
D1
D1
D1
D1
D1
D1
D1
D0
D0
D0
D0
D0
D0
EL
IM
PIO7
SI/IO0
1
A16
A8
A0
D0
D0
XCS
Opcode
Address
Output data
High−Impedance
High−Impedance
PR
Figure 36: 8-Bit Parallel Interface Read
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8-BIT PARALLEL INTERFACE COMMANDS AND ADDRESSING
XCSPAR
XRD/MCLK
XWR
IN
AR
Y
9
Data Data Data Data
byte 1 byte 2 byte 3 byte 4
0
A23
A15
A7
D7
D7
D7
D7
D7
D7
D7
D7
PIO6
0
A22
A14
A6
D6
D6
D6
D6
D6
D6
D6
D6
PIO5
0
PIO4
0
XHOLD/IO3
0
XWP/IO2
0
SO/IO1
1
SI/IO0
0
IM
PIO7
A13
A5
D5
D5
D5
D5
D5
D5
D5
D5
A20
A12
A4
D4
D4
D4
D4
D4
D4
D4
D4
A19
A11
A3
D3
D3
D3
D3
D3
D3
D3
D3
A18
A10
A2
D2
D2
D2
D2
D2
D2
D2
D2
A17
A9
A1
D1
D1
D1
D1
D1
D1
D1
D1
A16
A8
A0
D0
D0
D0
D0
D0
D0
D0
D0
EL
A21
XCS
Opcode
Address
Input data
High−Impedance
PR
Figure 37: 8-Bit Parallel Interface Write
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10
DOCUMENT VERSION CHANGES
IN
AR
Y
10
Document Version Changes
This chapter describes the most important changes to this document.
Version 0.6, 2012-06-14
• Updated clock frequency and power consumption information.
• Reorganized document according to functionality.
Version 0.5, 2012-02-03
• Added information for SOIC16 package.
Version 0.4, 2011-08-15
PR
EL
IM
• Added information for VS23S010A engineering samples.
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11
CONTACT INFORMATION
Contact Information
AR
VLSI Solution Oy
Entrance G, 2nd floor
Hermiankatu 8
FI-33720 Tampere
FINLAND
Y
11
PR
EL
IM
IN
Fax: 13751145915
FAX:0755-83957653
Email: [email protected]
URL: http://www.vlsi.fi/
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